1.

) Flash the FPGAs

Flash the FPGAs with the appropriated bitfile. The transceiver Toolkit bitfiles are located on the
aurora9 server in this folder:
/home/extoll/TransceiverToolkit/4000/
There is a bitfile for each direction:

2.) Open Transceiver Toolkit
After successful programming of the FPGAs, open the Toolkit in QuartusII.

3.) Load design into Transceiver Toolkit
The toolkit Window opens and you have to select the bitfile you want to use. Take the same
bitfile under the same location as if you want to program a FPGA.




4.) Activate transmitter
The serial loopback requires, that the transmitter of the lane you want to check is sending PRBS
pattern. For example. If you want to serial loopback test lane3 you have to activate transmitter
of lane 3.
If the linking of the bitfile was successful, the toolkit looks like this. The upper 8 lanes are FPGA0
and the lower 8 lanes are FPGA1.
Select a lane you want to start transmitting and click on the Control transmitter Channel




FPGA0
FPGA1
5.) Configure transmitter
After clicking the button Control transmitter Channel this tab shows up.

Now klick on the start button. The lane starts sending PRBS7 pattern.
Go back to the Transceiver Toolkit tab. This shows something like this. Green color is good!


6.) Eye measurement
At the Transceiver Toolkit tab, click on the Receiver Channels subtab. Again the upper 8
lanes are the receive lanes of FPGA0 and the lower 8 lanes are the receive lanes of FPGA1.

OK







FPGA0
FPGA1
7.) Start Eye measurement
Select a lane to check the Eye for. For example lane0. Then click on the Receiver EyeQ button.
This tab will show up.


Change the Run length value from time limit to maximum tested bits Change the 3.0 x
10^12 to 3.0 x 10^7. This will send 30 million bits per measure point instead of 3 trillion bit per
measure point.
Change the target bit error rate to 10^-12. This is the desired BER we want to achiev.
Check the checkbox to enable the serial loopback. If everything goes right, the result should look
like this: