EXPERIMENT NO.

1
AIM: Write a VHDL program to design various logic gates AND, OR, NOT, NAND,
NOR, XOR, XNOR.
TOOLS USED: Xilin !"# "imulator $.%i
AND GATE:
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' and% is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
c 6 out "TD)LO*!+7(
end and%(
arc0itecture 8e0avioral o1 and% is
&egin
c9:a and &(
end 8e0avioral(
SYMBOL:
OUTPUT:
OR GATE:
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' or% is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
c 6 out "TD)LO*!+7(
end or%(
arc0itecture 8e0avioral o1 or% is
&egin
c9:a or &(
end 8e0avioral(
SYMBOL:
OUTPUT:
NOT GATE:
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' not% is
4ort 5 a 6 in "TD)LO*!+(
& 6 out "TD)LO*!+7(
end not%(
arc0itecture 8e0avioral o1 not% is
&egin
&9:not a(
end 8e0avioral(
SYMBOL:
OUTPUT:
NAND GATE:
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' nand% is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
c 6 out "TD)LO*!+7(
end nand%(
arc0itecture 8e0avioral o1 nand% is
&egin
c9:a nand &(
end 8e0avioral(
SYMBOL:
OUTPUT:
NOR GATE:
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' nor% is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
c 6 out "TD)LO*!+7(
end nor%(
arc0itecture 8e0avioral o1 nor% is
&egin
c9:a nor &(
end 8e0avioral(
SYMBOL:
OUTPUT:
XOR GATE:
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' or% is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
c 6 out "TD)LO*!+7(
end or%(
arc0itecture 8e0avioral o1 or% is
&egin
c9:a or &(
end 8e0avioral(
SYMBOL:
OUTPUT:
XNOR GATE:
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' nor% is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
c 6 out "TD)LO*!+7(
end nor%(
arc0itecture 8e0avioral o1 nor% is
&egin
c9:a nor &(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 2
AIM: Write a VHDL program to design 0al1 adder.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' ans0ul is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
s 6 out "TD)LO*!+(
c 6 out "TD)LO*!+7(
end ans0ul(
arc0itecture 8e0avioral o1 ans0ul is
&egin
s9:a or &(
c9:a and &(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 3
AIM: Write a VHDL program to design 1ull adder.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' ans0ul is
4ort 5 a 6 in "TD)LO*!+(
& 6 in "TD)LO*!+(
cin 6 in "TD)LO*!+(
s 6 out "TD)LO*!+(
cout 6 out "TD)LO*!+7(
end ans0ul(
arc0itecture 8e0avioral o1 ans0ul is
&egin
s9:a or & or cin(
cout9:5a and &7 or 5& and cin7 or 5a and cin7(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 4
AIM: Write a VHDL program to design ;6$ decoder.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' decoder is
4ort 5 6 in "TD)LO*!+)V#+TOR 5< do2nto =7(
' 6 out "TD)LO*!+)V#+TOR 5> do2nto =77(
end decoder(
arc0itecture 8e0avioral o1 decoder is
&egin
'9:?=======%? 20en 9:?===? else
?======%=? 20en 9:?==%? else
?=====%==? 20en 9:?=%=? else
?====%===? 20en 9:?=%%? else
?===%====? 20en 9:?%==? else
?==%=====? 20en 9:?%=%? else
?=%======? 20en 9:?%%=? else
?%=======?(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 5
AIM: Write a VHDL program to design $6% multipleer.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' multipleer is
4ort 5 6 in "TD)LO*!+)V#+TOR 5> do2nto =7(
s 6 in "TD)LO*!+)V#+TOR 5< do2nto =7(
' 6 out "TD)LO*!+7(
end multipleer(
arc0itecture 8e0avioral o1 multipleer is
&egin
process 5,s7
&egin
i1 5s:?===?7 t0en '9:5=7(
elsi1 5s:?==%?7 t0en '9:5%7(
elsi1 5s:?=%=?7 t0en '9:5<7(
elsi1 5s:?=%%?7 t0en '9:5;7(
elsi1 5s:?%==?7 t0en '9:5-7(
elsi1 5s:?%=%?7 t0en '9:5@7(
elsi1 5s:?%%=?7 t0en '9:5,7(
else '9:5>7(
end i1(
end process(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 6
AIM: Write a VHDL program to design %6$ demultipleer.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' demulti is
4ort 5 i 6 in "TD)LO*!+(
s 6 in "TD)LO*!+)V#+TOR 5< do2nto =7(
' 6 out "TD)LO*!+)V#+TOR 5> do2nto =77(
end demulti(
arc0itecture 8e0avioral o1 demulti is
&egin
process 5i,s7
varia&le a,&,c6std)logic(
&egin
a6:not s5=7(
&6:not s5%7(
c6:not s5<7(
'5=79:a and & and c and i(
'5%79:a and & and s5<7 and i(
'5<79:a and s5%7 and c and i(
'5;79:a and s5%7 and s5<7 and i(
'5-79:s5=7 and & and c and i(
'5@79:s5=7 and & and s5<7 and i(
'5,79:s5=7 and s5%7 and c and i(
'5>79:s5=7 and s5%7 and s5<7 and i(
end process(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 7
AIM: Write a VHDL program to design - &it comparator.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' comparator is
4ort 5 a 6 in "TD)LO*!+)V#+TOR 5; do2nto =7(
& 6 in "TD)LO*!+)V#+TOR 5; do2nto =7(
e 6 out "TD)LO*!+(
l 6 out "TD)LO*!+(
g 6 out "TD)LO*!+7(
end comparator(
arc0itecture 8e0avioral o1 comparator is
&egin
process 5a,&7 is
&egin
i1 5a:&7 t0en
e9:A%A(
l9:A=A(
g9:A=A(
elsi1 5a9&7 t0en
e9:A=A(
l9:A%A(
g9:A=A(
else
e9:A=A(
l9:A=A(
g9:A%A(
end i1(
end process(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 8
AIM: Write a VHDL program to design - &it adder/su&tractor.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' addsu&tract is
4ort 5 a 6 in "TD)LO*!+)V#+TOR 5; do2nto =7(
& 6 in "TD)LO*!+)V#+TOR 5; do2nto =7(
s 6 in "TD)LO*!+(
' 6 out "TD)LO*!+)V#+TOR 5; do2nto =77(
end addsu&tract(
arc0itecture 8e0avioral o1 addsu&tract is
&egin
process 5a,&,s7 is
&egin
i1 5s:A=A7 t0en '9:aB&(
elsi1 5s:A%A7 t0en '9:a/&(
end i1(
end process(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 9
AIM: Write a VHDL program to design a arit0matic logic unit.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' alu% is
4ort 5 a 6 in "TD)LO*!+)V#+TOR 5; do2nto =7(
& 6 in "TD)LO*!+)V#+TOR 5; do2nto =7(
s 6 in "TD)LO*!+)V#+TOR 5< do2nto =7(
' 6 out "TD)LO*!+)V#+TOR 5> do2nto =77(
end alu%(
arc0itecture 8e0avioral o1 alu% is
&egin
process 5a,&,s7
&egin
i1 5s:?===?7 t0en '9:?====?C5aB&7(
elsi1 5s:?==%?7 t0en '9:?====?C5a/&7(
elsi1 5s:?=%=?7 t0en '9:aD&(
elsi1 5s:?=%%?7 t0en '9:?====?C5a and &7(
elsi1 5s:?%==?7 t0en '9:?====?C5a or &7(
elsi1 5s:?%=%?7 t0en '9:?====?C5a nand &7(
elsi1 5s:?%%=?7 t0en '9:?====?C5a nor &7(
else '9:?====?C5a or &7(
end i1(
end process(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 10
AIM: Write a VHDL program to design a mod/%= counter.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' aEa' is
4ort 5 reset 6 in "TD)LO*!+(
clF 6 in "TD)LO*!+(
dout 6 out "TD)LO*!+)V#+TOR 5; do2nto =77(
end aEa'(
arc0itecture 8e0avioral o1 aEa' is
&egin
counter 6 process 5clF,reset7 is
varia&le m 6 integer range = to %= 6: =(
&egin
i1 5reset:A%A7 t0en
m 6: =(
elsi1 5rising)edge 5clF77 t0en
m 6: m B %(
end i1(
i1 5m:%=7 t0en
m 6: =(
end i1(
dout 9: conv)std)logic)vector 5m,-7(
end process counter(
end 8e0avioral(
SYMBOL:
OUTPUT:
EXPERIMENT NO. 11
AIM: Write a VHDL program to design a &cd to > segment encoder.
TOOLS USED: Xilin !"# "imulator $.%i
PROGRAM:
li&rar' !###(
use !###."TD)LO*!+)%%,-.ALL(
use !###."TD)LO*!+)AR!TH.ALL(
use !###."TD)LO*!+).N"!*N#D.ALL(
//// .ncomment t0e 1ollo2ing li&rar' declaration i1 instantiating
//// an' Xilin primitives in t0is code.
//li&rar' .N!"!3(
//use .N!"!3.V+omponents.all(
entit' ans0ul is
4ort 5 6 in "TD)LO*!+)V#+TOR 5; do2nto =7(
' 6 out "TD)LO*!+)V#+TOR 5, do2nto =77(
end ans0ul(
arc0itecture 8e0avioral o1 ans0ul is
&egin
2it0 select
'9:?%%%%%%=? 20en ?====?,
?=%%====? 20en ?===%?,
?%%=%%=%? 20en ?==%=?,
?%%%%==%? 20en ?==%%?,
?=%%==%%? 20en ?=%==?,
?%=%%=%%? 20en ?=%=%?,
?==%%%%%? 20en ?=%%=?,
?%%%====? 20en ?=%%%?,
?%%%%%%%? 20en ?%===?,
?%%%==%%? 20en ?%==%?,
?=======? 20en ot0ers(
end 8e0avioral(
SYMBOL:
OUTPUT: