DC Lab - 22 - 4-2013

Department of Electronics and Communication Engineering Digital Communications Lab
EXPERIMENT: 1
TIME DIVISION MULTIPLEXING

AIM:

1. To study the operation of time division multiplexing.
2. To study the mechanism of level1 (Three wire method) transmission.
3. To study the mechanism of level2(Two wire method) transmission.
4. To study the mechanism of level3(One wire method) transmission.

APPARATUS:

1. Time division multiplexing modulator and demodulation trainer
2. C.R.O
3. Patch Cards

THEORY:

One of the greatest benefits to derive from the sampling is that of time division
multiplexing (TDM). By inter leaving samples of several source wave forms in time; it is
possible to transmit enough information to a receiver, via only one channel to recover all
message waveform. This process is called TIME DIVISION MULTIPLEXING.
The time allocated to one sample of one message is called a time slot. The time
interval over which all message are sampled at least once is called a frame. This position of
the time slot not used by any of the sampling pulse is called the guard time. In practical
system, some time slot may be allocated to other function like signaling, monitoring,
synchronization etc.

Synchronization:

To maintain proper position of sample pulses in the multiplexer it is necessary to
synchronize the sampling process. Because the sampling operation is usually electronic, there
is typically a clock pulse. In that it serves as a reference for all pulses. In TDM there are three
levels of synchronization.

Level 1 (Three wire method):
In this method the transmitter clock and synchronization pulses are directly linked to
the receiver.

Level 2 (Two wire method):
In this method the transmitter synchronization pulse are directly linked to the receiver,
But the clock pulses for receiver was derived from the transmitted information.

Level 3 (One wire Method):
In this method the synchronizing and clock pulses for the receiver are derived form
the transmitted (TDM) information.

Since due to higher costs, for long distance communication level 1 and level
2methods are not economical hence level 3methods is used.

PROCEDURE:

1. Connect the TDM module for three wire method.
2. Connect 250Hz, 500Hz,1KHz and DC signal of in function generator to the
transmitter.
3. Observe the outputs at transmitter and receiver.
4. Connect the TDM module for two wire method (By placing PLL input switch at
L2 position) and repeat 2 and 3.
5. Connect TDM module for one wire method (By placing PLL I/P switch at L3
position) and adjust threshold control for distortion less O/p and repeat 2 and 3.

Methods of synchronization:


OBSERVATIONS:

CHANNEL
INPUT SIGNAL RECEIVER OUTPUT
AMPLITUDE
V
P-P
VOLTS
FREQUENCY
(Hz)
AMPLITUDE
V
P-P
VOLTS
FREQUENCY
(Hz)

MODEL WAVEFORMS:

RESULT: Operation of TDM is studied. Level 1,2,3 transmission methods are studied.


EXPERIMENT: 2

PULSE CODE MODULATION

AIM:

To study pulse code modulation communication system.

APPARATUS:

1. PCM transmitter module (DCL-03)
2. PCM receiver module (DCL-04)
3. Regulated Power Supply
4. Digital Multimeter

THEORY:

Pulse Code Modulation is a technique, where analog signal issampled and samples are
transmitted as coded words of finite bit (Binary Digit) length. In pulse code modulation, first
the samples are quantized, and they encoded before transmitting as a serial bit stream.
Quantizing is the process where the samples are made to assume one of the finite sets
of discrete levels. Here is the first the whole signal level is divided into a fixed number of
discrete levels. The samples are rounded-off to the nearest discrete level. Then corresponding
to the level chosen a code word is assigned to the sample this process is called
ENCODING. The process of quantizing and encoding together is called ANLOG TO
DIGITAL CONVERSION.
The parallel data word available after the analog to digital conversion is converted to
a serial data stream after coding and sent through the channel. This coded data stream is said
to be PCM coded data and is transmitted by the serially by the PCM transmitter.
For recovering the data stream,first the serial data is converted to parallel finite bit
length code word. Then receiver identifies the code word and assigns the signal levels for the
received code word. The functional block that performs this task of accepting sequences of
binary digit and generating appropriate sequences of levels is called DIGITAL TO
ANALOGCONVERSION to sequences of levels that appear at the output of the D/A
converter is filtered to recover back the base band signal.

Synchronization Techniques:

For the recovery of information from the transmitted data stream, the transmitter and
receiver should be perfectly synchronized. Synchronization between transmitter and receiver
is achieved in two stages.
1. Bit synchronization
2. Frame synchronization

Bit Synchronization:

To recover the information from the serial bit stream, the receiver has to know if the
received data bit at a given instant of time is one or zero. For determining the data bit, the
clocks of transmitter and receiver are to be perfectly synchronized.

For achieving synchronization normally known as bit synchronization the clocks of
the transmitter (Tx clock)can be sent along with the data. This calls for an additional channel
for clock transmission. So normally a phase locked loop(PLL) is used at the receiver for
recovering the clock. This phase locked loop is made to lock with the incoming data whose
VCO reproduced the clock at the receiver.

Frame Synchronization:

For ensuring proper recovery of code words and proper assignment of channel
informations of the demultiplexing unit, the receiver has to know where the data begins
exactly for this, at the start of every frame, a 14bit pseudo ransom sequence(PRBS) is sent,
which forms the header of the data pattern. Subsequently what follows is data corresponding
to the number of channels multiplexed.
The frame sync pulse can be sent by the transmitter along with the data and clock to
achieve frame synchronization. But normally it is not sent, since it calls for an additional
channel.
To recover the frame sync at the receiver from the data stream, a sequence similar to
the one transmitted, is generated at the receiver.
The PRBS detector compares the generator sequence with the incoming data and
locks wherever the incoming data matches with the generated sequence. The PRBS sequence
is chosen is such a way that it has minimum correction with the data bits. Once the PRBS
detector is locked, it generates a frame sync pulse.
BLOCK DIAGRAM:

PROCEDURE:

1. Connect the circuit as shown in the block diagram. Make connections between
transmitter (DCL-03) and receiver (DCL-04) and put the clock generator in FAST
mode.
2. Select parity selection switch to NONE mode on both kits transmitter and receiver.
And ensure that all the switched faults are in OFF position. On both transmitter and
receiver kits.
3. Connect a DC voltage from regulated power supply to the transmitter I/P and vary its
voltage from 0 to 1V and 4 to 5V insteps of 40mV.
4. Take observation at:

On Transmitter (DCL 03):
A. input signal to ADC(10MVx out)
B. ADC output (B1 to B7)

On Receiver (DCL 04):
A. Input to DAC (B1 TO B7)
B. Output to DAC (AT DAC OUTPUT)

5. Draw a graph between A/D input voltage and A/D output data. Find the step size.

OBSERVATIONS:

ADC
i/p
mV
ADC OUTPUT DAC INPUT
DAC
o/p
mV
B1 B2 B3 B4 B5 B6 B7 B1 B2 B3 B4 B5 B6 B7

MODEL GRAPH:


RESULT: PCM system is studied. Outputs are observed.


EXPERIMENT: 3

DIFFERENTIAL PULSE CODE MODULATION AND DEMODULATION

AIM:

To Study differential pulse code modulation technique

APPARATUS:

ADCL 07 Kit
Connecting chords
Power supply
20MHz Dual Trace Oscilloscope
Note: Keep the switch faults in OFF position.

THEORY:

DPCM is a good way to reduce the bit rate for voice transmission. However it causes
some other problems that deals with voice quality. DPCM quantizes and encodes the
difference between a previous sample input signal and a current sample input signal. DPCM
quantizes the difference signal using uniform quantization. Uniform quantization generates
an SNR that is small for small input sample signals and large input sample signals. Therefore,
the voice quality is better at higher signals.

The first part of DPCM works exactly like PCM (that is why it is called differential
PCM). The input signal is sampled at a constant sampling frequency (more than the input
frequency). Then these samples are modulated. At this point, the DPCM process takes over.
The sampled input signals are stored in what is called a predictor. The predictor takes the
stored sample signal and sends it through a differentiator. The differentiator compares the
previous sample signal and sends its difference to quantizing and coding phase of PCM (this
phase can be a uniform quantizing or companding with A-law or -law). After quantizing and
coding, the difference signal is transmitted to its final destination. At the receiving end of the
network, everything is reversed. First the difference signal is decoded and de-quantized. This
difference is added to sample signal stored in the predictor and send through a low-pass filter
that reconstructs the original input signal.


BLOCKDIAGRAM:

PROCEDURE:

1. Refer to the block diagram and carry out the following connections and switch
settings.
2. Connect power supply in proper polarity to the kit ADCL 07 and switch it ON.
3. Keep the clock frequency at 512KHz, by changing the jumper position of JP1 in the
clock
generator section.
4. Keep the amplitude of the onboard sine wave, of frequency 500Hz to 1V
pp

DPCM MODULATION:

5. Connect the 500Hz sine wave to the IN post of Analog Buffer.
6. Connect OUT post of Analog Buffer to IN post of DPCM modulator section.
7. Observe the sample output at the given test point. The input signal is sampled at the
clock
frequency of 16KHz.
8. Observe the linear predictor output at the PREDICTED OUT post of the linear
predictor in the DPCM modulation section.
9. Observe the differential pulse code modulated data (DPCM ) at the DPCM OUT post
of the DPCM modulator section.
10.Observe the DPCM data at DPCM post by varying input signal from 0 to 12V.


DPCM DEMODULATION:

11. Connect the DPCM modulated data from the DPCM OUT post of the DPCM modulator
to the IN post of the DPCM demodulator.
12. Observe the demodulated data at the output of summation block.
13. Observe the integrated demodulated data at the DEMOD OUT post of the DPCM
demodulator.
14. Connect the demodulated data from the DEMOD OUT post of the DPCM demodulator
to the IN post of the low-pass filter.
15. Observe the reconstructed signal at the OUT post of the filter. Use RST switch for clear
observation of output.
16. Now, simultaneously reduce the clock frequencies from 512KHz to 256KHz, 128KHz
and 64KHz by changing the jumper position of JP1 and observe the difference in the
DPCM modulated and demodulated data. As the frequency of clock decreases, DPCM
demodulated data at DEMOD OUT becomes distorted.
17. Observe various waveforms as mentioned below (Fig.1.2)

OBSERVATION:

ON KIT ADCL 07
Observe the following waveforms on the oscilloscope and plot on the paper.

1. 500Hz, 1V
pp
input sine wave.
2. Sampled out at the provided test point SAMPLER OUT.
3. Linear predictor out at PREDICTED OUT post.
4. DPCM data DPCM OUT post.
5. Line interface out at the given output test point of interface block in DPCM
demodulation.
6. Demodulated DPCM data at the point of point of summation block in DPCM
demodulation.
7. Integrated demodulated data at the DEMOD OUT post of DPCM demodulator.
8. Reconstructed sine wave at the OUT post of the filter.
9. Observe the data at different clock rates.


MODEL GRAPHS AND WAVEFORMS:




RESULT: Differential PCM modulation and demodulation are studied .Outputs are observed
at different clock rates.


EXPERIMENT: 4

DELTA MODULATION AND DEMODULATION

AIM:

1. To Study the construction of delta modulation and demodulation circuit.
2. To observe the output of integrator, transmitted bit sequence and demodulator
output.
3. To verify the slope overloading condition.

APPARATUS:

1. Delta Modulation and Demodulation trainer
2. C.R.O

THEORY:

Delta modulation is a system of digital modulation developed after pulse code
modulation. In this system at each sampling time, say the Kth sampling time, the difference
between the sampling time K and the sample value at the previous sampling time(K-1) is just
encoded into just a single bit.
A serious problem in delta modulation schemes arises due to the rate of raise
overloading. When input signal is changing, then integrator output follows the input signal is
step wise fashion as long as successive samples of input signal do not differ by an amount
greater than the step size , then the integrator can no longer follow the input signal. This
type of overload is not determined by the amplitude of message signal but grater by it, slope.
Hence the name comeslope overload.

BLOCK DIAGRAM:


PROCEDURE:

Delta Modulator:

1. Connect the clock signal from clock generator, to the delta modulator clock input.
2. In order to ensure for correct operation of the system connect data input of delta
modulator to 0 Volts DC. Then adjust the level control in bipolar converter, until
the integrator output(at TPQ) will be a triangle wave centered around 0I,e the
output from the transmitters BISTABLE circuit(at TP7) will now be a steam of 1
and 0.
3. Now apply a sinusoidal modulating signal of amplitude 1vp-p and observe the
output of delta modulator (At TP7) and integrator output (at TP9).
4. Repeat the step 3 with modulating signal amplitude.

Slope overloading condition:

1. Increase the modulating signal amplitude until, the integrator output is a perfect
triangle and the modulator output is a stream of 1 or 0.
2. Find the modulating signal amplitude at that condition. Verify the slope overloading
condition with theoretical value.

OBSERVATIONS:

Modulating signal frequency (fx)= ___________________
Clock or sampling frequency (fs)= ___________________
Step Size ()= ________________
At slope overloading condition, the amplitude of modulating signal:
Theoretical =______________
Practical = _______________


MODEL GRAPH:

RESULT: Construction of Delta modulation and demodulation are studied. Slope
overloading condition is verified.


EXPERIMENT: 5

FREQUENCY SHIFT KEYING

AIM:

To find the construction of FSK modulator and demodulator circuit and their
operation.

APPARATUS:

1. FSK modulator and demodulator trainer
2. C.R.O
3. Patch Cards

THEORY:

Binary FSK is a form of constant amplitude angle modulation and the modulating
signal is a binary pulse stream that varies between two discrete voltage levels but not
continuous changing analog signal. In FSK the carrier amplitude (V
c
) remain constant with
modulation and the carrier radian frequency (e
c
) shift by an amount equal to e/2. The
frequency shift (e/2) is proportional to the amplitude and polarity of the input binary signal.
For example a binary 1 could +1 Volt producing frequency shift of +e/2 and -e/2
respectively. The rate at which the carrier frequency shift is equal to the rate of change of the
binary input signal V
m
(t)(that is the input bit rate). Thus the output carrier frequency deviates
(shift) between e
c
+e/2 and e
c
-e/2 at the rate equal to f
m
.
BLOCK DIAGRAM:


PROCEDURE:

1. Measure the frequency and amplitude of the carrier signal.
2. Connect the modulator circuit shown in the fig., and select data by using dip
switches.
3. Observe the output of FSK modulator on the CRO and find the frequency of the
carrier where 1 is transmitted and 0 is transmitted.
4. Repeat 2 and 3 for different input data values.
5. Connect the output of modulator to demodulator and observe the output of
demodulator. We can observe that the output of demodulator is similar to
transmitted data.

OBSERVATIONS:

1. Carrier Signal Amplitude = _________________
2. Carrier Signal Frequency = _________________
3. Carrier Signal Frequency (f
max
) = _______________ (1) is transmitted)
4. Carrier Signal Frequency(f
min
)= __________________
(0 is transmitted)
Frequency Deviation (f)=
2
min max f f

Demodulation:

DATA INPUT DEMODULATOR OUTPUT
01010101
11000110
00110100
11100111
00110011


MODEL WAVEFORMS:

RESULT: Construction of FSK modulator and demodulator circuit and their
operation are studied.


EXPERIMENT: 6

PHASE SHIFT KEYING

AIM:

To study the construction of PSK Modulator and demodulator circuit and
theiroperation.

APPARATUS:

1. PSK Modulator and Demodulator trainer
2. C.R.O
3. Patch Cards

THEORY:

To transmit the digital data from one place to another, we have to choose the
transmission medium. The simplest possible method to connect the transmitter to the receiver
with a piece of wire. This works satisfactorily for shot distance in some cases. But for long
distance communication and in situations like communication feasible. Here we hence to Opt
for the radio transmission.
It is not possible to send the digital data directly over the antenna because the antenna
of practiced size works on very high frequencies, much higher than our data transmission
rate.
To be able to transmit the data over antenna, we have to module the signal i.e. Phase
Shfit, frequency or amplitude etc., is varied in accordance with the digital data. At receiver
we separate the signal from digital information by the process of demodulation. After this
process we are left with high frequency signal (Called as carrier signal) which we discard and
the digital information, which we utilize.
The variation of particular parameter variation of the carrier wave give rise to various
modulation techniques. Some of the basic modulations techniques are ASK,FSK,PSK,DPSK
AND QPSK.

Phase Shift Keying (PSK):

Phase Shift Keying is a relatively new system, ion which the carrier may be phase
shifted by +900 for a mark, and by -900 for a space. PSK has a number of similarities to FSK
in many aspects, as in FSK, frequency of the carrier is shifted according to the modulating
square wave.


BLOCK DIAGRAM:

PROCEDURE:

1. Connect the modulator circuit as shown in the fig.
2. Observe the output of modulator for different data input.
3. Connect the demodulator circuit as shown in the fig.
4. Observe the demodulator output for different data input

OBSEVASTION:

DATA INPUT DEMODULATOR OUTPUT
1010110101

1010010100

1100011000

1000010000


MODEL GRAPH:

RESULT:Construction of PSK Modulator and demodulator circuit and their operation are
studied.


EXPERIMENT: 7

DIFFERENTIAL PHASE SHIFT KEYING

AIM:

To study operation of differential phase shift keying modulation and demodulation
techniques.

APPARATUS:

1. DPSK Modulation and Demodulation trainer.
2. C.R.O
3. Patch Cards.

THEORY:

The DPSK is a non-coherent version of PSK. The DPSK eliminates the need of
coherent response signal at the receiver by combining two basic operations at the transmitter.
1. Differential encoding of the input binary wave
2. Phase shit keying
The DSPK transmitter and receiver are equipped with storage capability, So that it can
measure the relative difference between the wave forms received during two successive bit
intervals.
In the transmitter circuit the output of modulator(i,e with 180 phase shift carrier) is
0 when the present data bit d(t) and previous modulator output bit b(t-Tb) are equal or it is
equal 1 when d(t) and b(t-Tb) are different, because b(t) is generated according to the rule.
b(t)= d(t) b(t-Tb)

BLOCK DIAGRAM:


PROCEDURE:

1. Apply a data input to the modulator and observe the output of modulator and
compare with theoretical value.
2. Connect the modulator input to demodulator and compare the demodulator output
with modulator data input.
3. Repeat 2 and 3 for different data input


OBSERVATION:

CASE-I
DATA INPUT d(t) 1 1 0 0 1 1 0 0 0 0
B(t-Tb) 0 1 0 0 0 1 0 0 0 0
DIFFERENTIAL DATA OUTPUT b(t) 1 0 0 0 0 0 0 0 0 0
DEMODULATOR OUTPUT 1 1 0 0 1 1 0 0 0 0

CASE-II
DATA INPUT d(t) 1 1 1 1 0 0 0 0 0 0
B(t-Tb) 0 1 0 1 0 0 0 0 0 0

CASE-III
DATA INPUT d(t) 1 1 0 0 0 0 0 0 0 0
B(t-Tb) 0 1 0 0 0 0 0 0 0 0

CASE-IV
DATA INPUT d(t) 1 0 1 0 1 0 1 0 1 0
B(t-Tb) 0 1 1 0 0 1 1 0 0 1


MODEL GRAPH:

RESULT: Operation of differential phase shift keying modulation and demodulation
techniques are studied. Output waveforms are observed.


EXPERIMENT: 8
COMPANDING

AIM: Implementation of -law companding and expansion of signal.

PROGRAM:

#include <stdio.h>
#include <math.h>
#define M 255
Float orignal [100], x[100], y[100], com[100], ex[100];
Void main ()
{
int 1;
float amp;
intsgn[100], sgn_y[100];
FILE *fp;
fp=fopen (D:\\ M_low_companding.text,wr);
fprintf(fp, \ Ninput sine\ t COMPANDING\ t OUTPUT SINE\n);
printf(Enter amplidude level=);
scanf(%f,&amp);
for (i=0; i<100; i++)
{
x[i]=amp*sin(2*3.14*i*1000/16000);
original [i]=x[i];
if (x[i]>0.0)
sgn[i]=1;
else
{
if(x[i]<0.0)
{
Sgn[i]=-1;
x[i] = x[i]*(-1);
}
else
if(x[i] ==0.0);
sgn[i]=0;
}
}
for (i=0; i<100; i++)
{
com[i]=(sgn[i]*log(1+(M*x[i])))/ log(M+1);
y[i]= com[i];
if(com[i]=0.0)
sgn_y[i]=1;
else
{
if(com[i]<0.0)
{
Sgn_y[i]=-1;

y[i] = com[i]*(-1);
}
}
else if(com[i]==0.0)
sgn_y[i]=0;
}
}
for (i=0; i<100; i++)
{
ex[i]=(sgn_y*(pow((1+M),y[i]-1)/M);
}
for(i=0; i<100; i++)
{
fprint(fp,%f \ t % f \ t% f\n, orignal[i], com[i], ex[i]);
}
}

THEORY:

Companding is a non uniform quantization. It is requried to be implemented to
improve the signal to noise ratio of a signal. Because in n uniform quantization. The step
sime is constant. So SNR value is directly proportional to the input signal. It it is a weak
signal its SNR value is less SNR value is more for strong signal.
The remedy is to use companding is a term derived from two words i.e., compression
and expansion as under.
Companding = compression + Expanding
In practice it is difficult to implement the non-uniform quantization because it is known in
advance about the changes in the signal level. Therefore a particular method is used the weak
signals are amplified and strong signals are attenuated before applying them to a uniform
quantizer. This process is called a compression and the block that provides it is called as a
compressor. At the receiver exactly opposite is followed by expansion -law companding is
one of the types of companding.

-law companding:-

In this, the compressor characteristic is continuous. It is approximately linear for
smaller values of input levels and logarithmic for high input level.
The -law companding is mathematically expressed as

) 1 ( ln
) max 1 ( ln
) (sgn ) (
+
+
=
x x
x x F
Where0 < 1
max
s
x
x


F(x) represent the output and x represents the input to the compressor
max x
x
is the
normalized value of input with respect to the maximum value x
max
. (sgn x) represents + 1
i.e., +ve and ve values of input and output.
The -law compressor characteristics practically used =255, =0 represents the
uniform quantization.The -law companding is used for speech and music signals. It is used
for PCM telephone systems in United States.

PROCEDURE:

1. Open code composer studio make sure the DSP kit is turned ON.
2. Load program using File load_program. Which is saved in program, CD-ROM at
following location.
PATH: PROGRAMS \ M_law \ debug \ M_law.out
3. Then run program from debug Run.
4. When the program is run, it will ask to enter amplitude level. Enter amplitude level
5. To view original signal
select view graph time and frequency.
6. To M=255 and calculate companded value by using formula (1) plot the graph.
7. To view compressed signal
Select view graph time and frequency
8. For expansion use formula (2) plot graph to view expanded signal
Select view graph time and frequency


TABULAR FORM:
- Law binary encoding table
Biased Input value
Compressed code word
Chord step
Bit 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 a b c d x 0 0 0 a b c d
0 0 0 0 0 0 1 a b c d x x 0 0 1 a b c d
0 0 0 0 0 1 a b c d x x x 0 1 0 a b c d
0 0 0 0 1 a b c d x x x x 0 1 1 a b c d
0 0 0 1 a b c d x x x x x 1 0 0 a b c d
0 0 1 a b c d x x x x x x 1 0 1 a b c d
0 1 a b c d x x x x x x x

1 1 0 a b c d

1 a b c d x x x x x x x x 1 1 1 a b c d

- Law binary decoding table
Compressed code word
Biased Input value
Chord step
Bit 6 5 4 3 2 1 0
Bit 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 a b c d 0 0 0 0 0 0 0 1 a b c d 1
0 0 1 a b c d 0 0 0 0 0 0 1 a b c d 1 0
0 1 0 a b c d 0 0 0 0 0 1 a b c d 1 0 0
0 1 1 a b c d 0 0 0

1 a b c d 1 0 0 0
1 0 0 a b c d 0 0 0 1 a b c d 1 0 0 0 0
1 0 1 a b c d 0 0 1 a b c d 1 0 0 0 0 0
1 1 0 a b c d 0 1 a b c d 1 0 0 0 0 0 0
1 1 1 a b c d 1 A b c d 1 0 0 0 0 0 0 0


MODEL WAVEFORMS:

RESULT: Implementation of -law companding and expansion of signal is studied.


EXPERIMENT:9

SOURCE ENCODER AND DECODER

AIM: Image compression using Huffman coding

PROGRAM:

# include <stdio.h>
# include<math.h>
# define N64
# include <coe.h>
Char image in [N][N];
Char image out [N][N];
void main()
{
int out [N][N];
int temp [256];
intnist [256];
intI,j,count,value,b=0,k=0;
FILE*fp;
fp=fopen(E:\\ nist.ext,wr);
fprintf (fp,\n\n table \n\n);
fprint (fp,i/p pixels \t 0-of-pixel\t new pixel\n);
for (value=0:value<256;value++)
{
count=0;
for(i=0;i<N;i++)
{
for(j=0;j<N;j++)
{
if(ln [i][i]=value)
count++;
}
}
Nist(value)=count;
If(count!=0)
{
temp[b]=value;
f printf(fp,%d\t\t%d\t\t%d\m,valuesnist[value],b);
b++;
}
}
for(k=0;k<b;k++)
{
for(i=0;i<n;i++)
{
For(j=0;j<n;j++)
{

if(temp[k]==in[i][j]
out[i][j]=k;
}}}
f printf(fp,\n\n\n i/p -pixels\t o/p pixels);
for(i=0;j<n;i++)
for(j=0;j<n;j++)
{
f printf(fp,\n%d \t%d,in[i][j],out[i][j]);
image-in[i][j]=in[i][j];
image-out[i][j]=out[i][j];
}
}

THEORY:

HUFFMAN CODING: Huffman coding is an algorithm for the lossless compression of files
based on the frequency of occurrence of a symbol in the file that is being compessed .The
Huffman algorithm is based on statistical coding which means that the probability of symbol
has a direct bearing of on the length of its representation.The most probable occurence of the
symbol is the shorten will be its bit size representation . In any file certain characters are
used more than any others. Using binary representation,the number of bits are required to
present each character depends upon the number of characters that have to be represented
using one bit we can represent two characters i.e, 0 represents the first character and 1
represents the second characters and so on.. unlike ASCII code which is a fixed length code
using seven bits per characters.
Huffman compression is a variable length coding system that assigns smaller code for
more frequently used characters in order to reduce the size of files being compressed and
transferred.
The basic idea in Huffman coding is to assign short code to those input blocks with the
high probabilities and long code word to those with low probabilities.This concept is smaller
to that of morse code.

PROCEDURE:

1. Open code compressor studio ,make sure that DSP kit is turned on.
2. Load program using File->load program which is saved in program,CD-ROM at
following location.
Path:programs\Huffman coding\Debug\Huffman coding out.
3. Then run program from Debug->Run.

PRECAUTIONS:
1. check the steps in a manner before sum of a program.
2. Avoid error by following rules of that particular software.
3. Observe output carefully without errors.

RESULT : Image compression using Huffman coding is done


EXPERIMENT:10

LINEAR BLOCK CODE-ENCODER AND DECODER

AIM:

To Study linear block code encoder and decoder

APPARATUS:

1. Experiment Kits DCL-03 and DCL-04
2. C.R.O
3. Connecting Wires

THEORY:

ODD PARITY MODE:

ODD parity generator generates the coded sequence, which consists of 6bits of data
plus one odd parity bit for transmission. The least significant bit(B1) of the data word from
the ADC is replaced with the parity bit. The coded sequence will be:
ODD parity bit, B2,B3,B4,B5,B6,B7
ODD parity checker checks the number of ones in the data stream and determines if a
single bit error had occurred during transmission. PARITY ERROR LED gives the
indication.

EVEN PARITY MODE:

EVEN parity generator generates the coded sequence, which consists of 6bits of data
plus EVEN parity bit for transmission. The least significant bit(B1) of the data word from the
ADC is replaced with the parity bit. The coded sequence will be:
EVEN parity bit, B2,B3,B4,B5,B6,B7
EVEN parity checker checks the number of ones in the data stream and determines if
a single bit error had occurred during transmission. PARITY ERROR LED gives the
indication.

HAMMING PARITY MODE:

Humming code generator generates the coded sequence, which consists of 4bit of data
plus 3bits of error check bits(K1,K2,K3) for the transmission. The least significant
bits(B1,B2,B3) of the data word form:
K1,K2,K3,B4,B5,B6,B7
Hamming error detect/correction logic computes K1,K2,K3 at the receiver and locates
the error bit position. Once the error bit position is located, the error is corrected by bit
reversal.


PROCEDURE:

1. Connect the modules DCL-03 & DCL-04 as shown in the figure.
2. Set speed selection switch FAST mode.
3. Select parity selection switch to EVEN PARITY mode on the both kits DCL-03
and DCL-04.
4. Observe the sequence of data bit on both kits for different data inputs.

ON KIT DCL-03:

1. A/D CONVERTER
2. PARITY CODED DATA
3. ERROR CODE GENARATOR

ON KIT DCL-04:

1. SHIFT REGISTER
2. DATA LATCH
3. D/A CONVERTER
4. PARITY ERROR
5. Create a single bit fault in any one of the 4 MSB bits by using the switches of
SF1 on the kit DCL-03, observe the status of PARITY ERROR.
6. Repeat the step 2,3,4 and 5 for ODD PARITY & HAMMING PARITY MODE.

OBSEVATION:

TRANSMITTER RECEIVER
A/D
CONVERTER
PARITY
CODE
GENARATOR
ERROR
CODE
GENARATOR
DATA
LATCH
D/A
CONVERTER
PARITY
ERROR
EVEN PARITY MODE
*000000 0000000 0000000 0000000 0000000 OFF
*111110 1111110 1111110 1111110 1111110 OFF
*111110 1110110 1110110 1110110 0110110 ON
ODD PARITY MODE
*000000 1000000 1000000 1000000 0000000 OFF
*111110 0111110 0111110 0111110 0111110 OFF
*111110 0111110 0110110 0010110 0110110 ON
HAMMING CODE
***0000 0000000 0000000 0000000 0000000 0000000
***1000 1101000 1101000 1101000 0001000 0000000
***1110 0001110 0001110 0001110 0001110 0000000
***0000 0000000 0001000 0001000 0000000 0001000
***0000 0000000 0000100 0000100 0000000 0000100
***0000 0000000 0000010 0000010 0000000 0000010
***0000 0000000 0000001 0000001 0000000 0000001

RESULT: Error controlling methods are studied. Linear block code-encoder and decoder are
studied

EXPERIMENT: 11

BINARYCYCLIC CODE -ENCODER AND DECODER

AIM: To study CRC encoding and decoding

APPARATUS: ADCL-08 Board and its power supply.

THEORY: A CYCLIC REDUNDANCY CHECK (CRC) or polynomial code check sum is
a non-secured has to function designed to detect accidental changes to race computer data and
is commonly used in digital networks and storage devices such as hard disk drives. A CRC-
enabled devices calculates a short, fixed-length binary sequence, known as the CRC code on
just CRC, for each block of data and sends or stores them both together when a block is read
or received the device repeats the calculation if the new CRC does not match the one
calculated earlier, then the rereading (or) requesting the block be sent again.

CRCs are so called because the clock (data verification) code is redundancy (it adds
zero information) and algorithm is based on cyclic codes the term CRC may refer to the
check code or to the function that calculates it, which accepts data streams of any length as
code CRCs are popular because they are simple to implement in binary hardware, are easy to
analyze mathematically, and are particularly good at detecting common errors caused by
noise in transmission channels.

THEORY OF OPERATION:
The theory of a CRC calculation is straight forward data is treated by the CRC
algorithm as a binary number. This number is divided by another binary number called the
polynomial the rest of the division is the CRC check sum, which is appended to the
transmitted message the receiver divides the message (including the calculated CRC) by the
same polynomial. The transmission was successful. However, if the result is not equal to
zero, and error occurred during the transmission.

The CRC-16 polynomial is shown in equation(1 ) below
P(x) = x
16
+x
15
+1 - - - 1

The polynomial can be (transmitted) translated into a binary value because the divisor
is viewed as a polynomial with binary coefficients. For example, theCRC-16
1000000000000101b. all coefficients like X
2
or X
15
, are represented by a logical 1 in the
binary value (because the divisor is viewed as a polynomial).

CRC Hardware Implementation:-
The CRC calculation is realized with a shift register and XOR gates Fig.1 shows a
CRC generator for the CRC-16 polynomial. Each bit of the data is shifted into the CRC shift
register (Flip-Flops) after being XORed with the CRCs most significant bit.

Example:- In ADCL-08 kit the generator polynomial for CRC is x
4
+x
3
+1. i.e.,(11001).
Select data pattern as 11100100. Internally 4 zeros appended after actual shift data
for transmitting bit CRC. Thus data will be 111001000000.


To calculate the CRC divide the input data by generator polynomial as shown below

111001000000 1101 111001000000 / 11001

11001) 111001000000 ( 11111
11001
0010110
11001
011110
11001
0011100
11001
10100
11001
01101 CRC
Thus generated CRC for the data pattern is 1101 and final transmitted data will be
(data +CRC) 111001001101

In receiver side the same generator polynomial is used to calculate the CRC of the
received data. If remainder is zero then received data has no error. CRC can correct single bit
error
In ADCL-08 two errors can be introduced in data at 5
th
and 8
th
position using switch
SW2 at receiver. CRC is being calculated is shown below for data without any errors

111001001101 11001
11001) 111001001101 ( 11111
11001
0010110
11001
011110
11001
0011111
11001
0011001
11001
00000 Remainder is zero

Indicated received data has zero errors.

If one error is introduced to data using SW2 (left side switch) in 5
th
position of data
them data with error will received at receiver side. The receiver calculates CRC using same
polynomial if there is some remainder then using lookup table the bit to correct the data with
error are found out and simply invert that bit to correct the data
Data without error at receiver = 111001001101
Data with error in 5
th
position = 111011001101
CRC calculation is as shown below.


111011001101 11001

11001) 111011001101( 11111
11001
0010010
11001
010110
11001
011111
11001
0011010
11001
000111
The remainder in this case is 111. This corresponding LED indication is observed on
B
2
, B
3
, B
4
at CRC decoder section the value 111 corresponds to bit position (the
remainder)5in lookup table and that particular bit is inverted and corrected data at receiver is
available which 111001001101 is similarly for another error bit which is in 8
th
position the
remainder will be 101 which is indicated on B
1
and B
4
at CRC decoder section.

PROCEDURE:

1. The connections are made as per the block diagram.
2. Connect the power supply to the kit and switched it ON.
3. Set the data pattern as shown in the block diagram using SW1. Observe the 8 bit serial
data at serial data post.
4. Connect the serial data to DATA IN POST of CRC GENERATOR.
5. Observe the CRC encoded signal at DATA OUT POST of CRC generator.
6. Connect the DATAOUT to DATA IN post of CRC ERROR ADDER to introduce 2 bit
manual error. Introduce error by switch SW2
7. To decode the signal connect DATAOUT to IN POST of CRC DECODER block.
8. Observe the CRC decode and corrected signal at OUTPOST of CRC DECODER,
calculate CRC at receiver end and display it an LED B
1
to B
4.
.

OBSERVATIONS:
1. Input data at serial data post of generator.
2. CRC encoded data at DATAOUT post of CRC generator.
3. CRC data with error at DATAOUT POST of CRC ERROR ADDER.
4. Calculated CRC at receiver on LED B
1
to B
4
.


BLOCK DIAGRAM:

MODEL WAVEFORMS:

RESULT:CRC encoding and decoding is studied.


EXPERIMENT: 12

CONVOLUTION CODE - ENCODER AND DECODER

AIM:To study the construction of convolution code encoder and decoder.

APPARATUS :
1. Convolution encoder and decoder kit
2. Patch chords
3. Power supply
4. 30 MHz dual trace oscilloscope
THEORY :

A convolution code work by adding some Structured redundant information to the
users data and then correcting errors using this information. A convolutional encoder is
a linear system . A binary convolution encoder can be represented as a shift register.
The outputs of the encoder are modulo 2 sums of the values in the certain registers cells
The input to the encoder is either the unencoded sequence( or) the unencoded sequence
added with the values of some register s cells. ( for recursive codes ) .

BLOCK DIAGRAM:

PROCEDURE:

1. Connect the circuit diagram as per diagram.
2. Connect the power supply in properly to the kit ADCL-06 and switch it on.
3. Keep the data clock, select the switch SW2 towards slow position.
4. Select the data pattern using select switch SW1 in the data generator block.
5. Connect the data generator to DATA in of convolution encoder.
6. Observe RDY pin convolutionally encoded data will observed at out1 and out2 port.
The convolutionaly encoded data are varied from the instant when RDY goes high.
7. Connect the out1 and out2 ports of convolution block to IN1 and IN2 of hard
decision viterbi decoder block.
8. Observe the decoder data of out1 and respeat the procedure by keeping data clock
select switch towards fast position.


MODEL GRAPHS:

In put sequence : 1000000
Output sequence : 11011111001011
The o/p sequence for the i/p one is called impulse response of the encoder.
Then for the i/p sequence M=1111111, the o/p the linear addition of the times shifted i/p
impulse as follows.
Input output
1
11011111001011
1 11011111001011
1 11011111001011
1 11011111001011
1 11011111001011
1 11011111001011
1 11011111001011

Modulo 2 Sum 1110011010001111000110010111


-Observe that, this is the same o/p obtained demonstrating that convolution code (or)
trainer. It is form this property of generating the o/p by the linear addition of the time shift
impulse (or) the convolution of the i/p sequences with the impulse response of the encoder.
That we are

OBSERVATIONS:
1. Serial data w.r.t 0 data clock.
2. Out1 with respect to RDY1
3. Out2 with respect to RDY1
4. Out1 with respect to out2.
5. Dataout1 with respect to serial data.

PRECAUTIONS:
1. All the connections should be tight.
2. Readings should be taken without any error.

RESULT:

The convolution encoded and decoder was studied.
The output of the out1 and out2 were the Xored o/p of the convolution encoder and
the output of the verify decoder was same that of the serial data.


EXPERIMENT: 13
Additional Experiments
MSK MODULATION AND DEMODULATION

AIM :To study the minimum shift keying modulation and demodulation.

APPARATUS:
ADCL -08 Board
Power supply.
BLOCK DIAGRAM:

THEORY :

In digital modulation minimum shift keying (MSK ) is a type of continuous phase
frequency shift keying that was developed in the late 1960s similar to OQPSK, MSK is
encoded with bits alternating between quaternary components , with the q components
delayed by half the symbol period. However, instead of square pulses as OQPSK uses, MSK
encodes each bit as a half sinusoidal. This results in constant modulus signal, which reduces
problems caused by non- linear distortion. In addition to being verified viewed as related to
OQPSK , MSK can be viewed as a continuous phase frequency shift keyed signal with a
frequency separation of one half the bit rate.
Minimum shift keying MSK is a form of FSK ( frequency shift keying ) or phase
shift keying (PSK). MSK uses changes phase to represent 0s and 1s with the phase shift
used depending on the previous phase value. MSK acts like FSK with minimum difference
between the frequencies of to FSK signals resulting in a power spectral density that falls off
much faster than QPSK (quadrature phase shift keying ) so MSK can operate in a smaller
ratio band width than QPSK. GSM uses a variant of MSK and QPSK,GMSK (Gaussian
MSK).
Minimum frequency shift keying or minimum shift keying (MSK) is a particularly
spectrally efficient form of coherent FSK. In MSK the difference between the higher and
lower frequency is identical to half the bit rate consequently the wave form used to represent
a 0 and 1. Bit differ by exactly half a carrier period . this is the smallest FSK modulation
index that can be chosen such that the wave form for 0 and 1 are the orthogonal . a variant of
MSK called GMSK is used in GSN mobile phone standard .
In ADCL -08 the carrier is transmitted according to symbol given in following table.


S.no Symbol Carriers
1
2
3
4
00
01
10
11
HIGH frequency (
)
LOW frequency (
)
LOW frequency (
)
HIGH frequency (
)

Frequency of high frequency carrier = 384.6 KHz
Frequency of low frequency carrier = 256.4 KHz.
High frequency (384.60 KHz) is 1.5 times the low frequency (256.4 KHz)

PROCEDURE :

1. Do the connections as per block diagram shown in figure.
2. Connect the power supply to the kit and switch it on.
3. Set the data pattern as shown in block diagram using SW1. Observed the 8 bit serial
data at serial data post.
4. Observe the carrier uses for modulation at sin1 and sin2 posts.
5. Connect serial data to data 1N post of DEBIT CODER.
6. Observe EVEN and ODD data w.r.t their clocks.
7. Observe MSK Modulated signal at MOD OUT post of CARRIER MODULATOR.
8. To demodulate the MSK signal connect MODOUT to IN post of MSK demodulator
section
9. Observe the modulated EVEN and ODD signal at MSK DEMODULATOR and
compare it with debit coder.
10. Observe the demodulated signal at OUT post of MSK demodulator and compare it
with original signal i.e. with signal at SERIAL DATA.



OBSERVATIONS :

1. In put data at SERIAL DATA.
2. EVEN and ODD clock signals of debit coder.
3. Carrier frequency SIN 1 to SIN2 .
4. MSK modulated signal at MODOUT.
5. Recovered data at out post of MSK demodulator.
RESULT:

Minimum shift keying modulation and demodulation are studied.Output waveforms are
observed.


EXPERIMENT: 14

PSEUDO RANDOM SEQUENCE

AIM:

1. To study the generation of PSEUDO RANDOM SEQUENCE
2. To study the method of synchronization between transmitter and receiver.

APPARATUS:

1. Experiment modules DCL-03 and DCL-04
2. C.R.O
3. Connecting wires

THEORY:

For ensuring proper Frame Synchronization between the transmitter and the receiver,
a 14bit Pseudo Random sequence is transmitted along with the data. A 4-Bit Shift Register
with an EX-OR gate at the feedback generates the Pseudo Random Sequence, which is a
unique pattern that has minimum correlation with data. The clock frequency for Pseudo
Random Sequence generator is the same as the frequency of the transmitted serial data. Note
that PRBS is generated and transmitted only when the sync remain high. When the sync is
low, No PRBs is generated and at that time, the serial data is transmitted over the line.
The PRBS sequence generated on the kit DCL-03 is of the following format:
10001001101011.

DCL 03 and DCL 04 Modules:

Serial data rate: Fast: 240 Bit per Second
Slow: 1bit per 813 mSec. and 1bit per 22 Sec.

Sampling frequency:Fast: 16KHz
Slow: 1 sample per 11 Sec. and 1 sample per 22 sec.

Channel data patterns:

I. NONE: (LSB)B1 B2 B3 B4 B5 B6 B7(MSB)
II. ODD PARITY: P1 B2 B3 B4 B5 B6 B7
III. EVEN PARITY: P1 B2 B3 B4 B5 B6 B7
IV. HAMMING CODE: K1 K2 K3 B4 B5 B6 B7
CHECK DATA BIT

K1 Even parity for data bits B4 B5 B7
K2 Even parity for data bits B4 B6 B7
K3 Even parity for data bit B5 B6 B7


PSEDUO random sequence:

BLOCK DIAGRAM:


PROCEDURE:

To study the PRBS generation and transmission:

1. Set the speed selection switch SW1 on DCL-03 to SLOW mode.
2. Observe the flow of the PRBS in LEDs D1,D2,D3,D4(LED display for PRBS
sequence is complimentary) and verify with the truth table.
3. Set the speed selection switch SW1 on DCL-03 to FAST mode.
4. Connect data o/p to one channel of the C.R.O and TXSYNC to another channel of
the C.R.O.
5. Observe that whenever the sync pulse remains high PRBS are generated and
transmitted and whenever the sync pulse remain low the data was generated and
transmitted through Tx to Rx the line.

To study the synchronization of T
X
to R
X
by using PRBS:

1. Connect the circuit as shown in the figure
2. Verify the data transmitted and received. We can observe that both are same even
when the TXSYNC was not connected to the receiver.

OBSERVATIONS:

TRUTH TABLE FOR PRBS
CLOCK THEORITICAL PRACTICAL
D1 D2 D3 D4 D1 D2 D3 D4
1 1 0 0 0 0 0 0 1
2 0 1 0 0 1 0 1 1
3 0 0 1 0 1 1 0 1
4 1 0 0 1 0 1 1 0
5 1 1 0 0 0 0 1 1
6 0 1 1 0 1 0 0 1
7 1 0 1 1 0 1 0 0
8 0 1 0 1 1 0 1 0
9 1 0 1 0 0 1 0 1
10 1 1 0 1 0 0 1 0
11 1 1 1 0 0 0 0 1
12 1 1 1 1 0 0 0 0
13 0 1 1 1 1 0 0 0
14 0 0 1 1 1 1 0 0
15 0 0 0 1 1 1 1 0


DATA O/P AT A/D CONVERTER ON
TRANSMITTER
DATA I/P TO D/A CONVERTER ON
RECEIVER
D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0 1 1 1 0 0 0
1 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 0 0 1 1 1 1 0 0 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1

RESULT:-Generation of PSEUDO RANDOM SEQUENCE IS studied.
The method of synchronization between transmitter and receiver is studied.


















REFERENCES
Communications Systems B.P. Lathi
Digital And Analog Communications Simon Haykin
Digital And Analog Communication systems K. Sam Shanmugam
Electronic and Radio Engineering FE Terman
Electronics and Communication System Gorge Kennedy
Falcon User Manuals
Hi Q electronics User Manuals
Principles of Communications Systems H.Taub and D.L Schiling

DC Lab - 22 - 4-2013

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