Microelectronics Processing Technology

6.152J / 3.155J

Spring 2004
MOSCap01.doc MOS Capacitor Page 1 of 9

Metal Oxide Semiconductor (MOS) Capacitor

The MOS capacitor structure is shown in Figure 1. The metal plate is a heavily doped n
+
-
poly-silicon layer which behaves as a metal. The insulating layer is silicon dioxide and the other
plate of the capacitor is the semiconductor layer which in our case is n-type silicon whose
resistivity is 1-10 -cm corresponding to a doping of 10
15
cm
-3
.

The capacitance of the MOS structure depends on the voltage (bias) on the gate. For the purposes
of this discussion, we shall refer to the contact to the semiconductor as the body (B) while the
poly-silicon is called the gate (G). Typically a voltage is applied to the gate while the body is
grounded and the applied voltage is V
G
but more accurately V
GB
. The two (V
G
& V
GB
) will be
used interchangeably in this document.

n-Si
n
+
-Poly-Si
B ody
Gate


Oxide

Figure 1: The MOS Capacitor structure. The substrate (body) is grounded and a voltage V
GB
is
applied to the poly-silicon gate.

The capacitance depends on the voltage that is applied to the gate (with respect to the body). The
dependence is shown in Figure 2 and there are roughly three regimes of operation separated by
two voltages. The regimes are described by what is happening to the semiconductor surface.
These are (1) Accumulation in which mobile carriers of the same type as the body accumulates
at the surface [electrons] (2) Depletion in which the surface is devoid of any mobile carriers
leaving only a space charge or depletion layer, and (3) Inversion in which mobile carriers of the
opposite type to the body [holes] aggregate at the surface to invert the conductivity type. The
two voltages that demarcate the three regimes are (a) Flatband Voltage (V
FB
) which separates
the accumulation regime from the depletion regime and (b) the Threshold Voltage (V
T
) which
demarcates the depletion regime from the inversion regime.

Let us now look at our particular device MOS capacitor with an n-type body / substrate.


V
GB
V
T
C
MOS
(V
T
)=C
min

V
FB
Inversion
Depletion Accumulation
C
QS
C
HF
C
max
C
min
C
max
=AC
ox

C
MOS

Figure 2: Capacitance vs. Gate Voltage (CV) diagram of a MOS Capacitor. The flatband voltage
(V
FB
) separates the Accumulation region from the Depletion regime. The threshold voltage (V
T
)
separates the depletion regime from the inversion regime. C
HF
is high frequency capacitance
while C
QS
is quasi-static or low frequency capacitance.

Surface Accumulation (V
GB
>V
FB
)

An applied positive gate voltage larger than the flatband voltage (which will be defined shortly)
(V
GB
> V
FB
) induces positive charge on the metal gate and negative charge in the
semiconductor. The only negative charges available are electrons and they accumulate at the
surface. The electron concentration at the surface is above the bulk value, thus leading to a
condition that is called surface accumulation. The charge distribution and equivalent circuit is
shown in Figure 3. The flatband voltage (V
FB
) is the voltage at which there is no charge on the
plates of the capacitor and hence there is no electric field across the oxide. Its numerical value
depends on the doping of the semiconductor and on any residual interface charge that may exist
at the interface between the semiconductor and the insulator. When the surface of the
semiconductor is accumulated, a plot of the charge per unit area (Q
N
) at the semiconductor /
oxide interface versus the applied voltage (V
GB
) is linear and the slope is the oxide capacitance
per unit area., C
ox
., which is given by
ox
MOS,accumulation max ox
ox
C C A C
t
A

= = =
where
ox
is the permittivity of the oxide and it is 3.9
o
.
o
is the permittivity of free space or air.

o
=8.854x10
-14
Fcm
-1
. The unit for C
ox
is Fcm
-2
. Figure 4 is a plot of the charge per unit area
(Q
N
) as a function of the applied voltage (V
GB
).
MOSCap01.doc MOS Capacitor Page 2 of 9
-t
ox
0
x
+
+
+
+
+
-
-
-
-
-

charge density
Oxide
Poly-Si
Silicon
C
ox
+ + + + +
- - - - -
Oxide
G
B
Figure 3: Charge distribution in a MOS Capacitor biased into accumulation. The electron
distribution at the Si/SiO
2
interface could be approximated as a -distribution.


Figure 4: Accumulation charge density as a function of the applied voltage. The slope of the line
is the oxide capacitance per unit area, C
ox
.

Surface Depletion (V
T
<V
GB
<V
FB
)

If the applied gate voltage is brought below the flat band voltage (remember the flat band voltage
is the gate voltage at which there is no charge in the MOS capacitor), a negative charge is
induced at the interface between the poly-silicon gate and the oxide. This leads to a positive
charge being induced at the other interface i.e. the oxide / semiconductor interface. This could
only be accomplished by pushing all the mobile negative carriers (electrons) away and
exposing the fixed positive charge from the donors. Hence the surface of the semiconductor is
depleted of mobile carriers leaving behind a positive space charge. Figure 5 shows the charge
distribution under these circumstances. The space charge layer resulting behaves also like a
capacitor having a capacitance per unit area (C
D
), which depends on V
GB
and is given by
MOSCap01.doc MOS Capacitor Page 3 of 9

( )
( )
GB d
Si
V C
GB D
V x

=

where
Si
is the permittivity of the silicon and it is 11.7
o
.
o
is the permittivity of free space or
ir.
o
=8.854x10
-14
Fcm
-2
. x
d
is the depleted silicon layer thickness. The unit of C
D
is Fcm
-2
.
on
apacitance per unit area (C
D
) are connected in series. Thus the capacitance of the MOS
a

From Figure 5, we observe that the oxide capacitance per unit area (C
ox
) and depleted silic
c
structure when it is in the surface depletion regime is given by
depletion ox D
ox D
MOS,depletion depletion
ox D
1 1 1
C C C
= +
C C
C A C A
C C
= =
+


The unit for C
depletion
is Fcm
-2
. The silicon depletion layer thickness increases as the gate voltage
decreased because more electrons are pushed away exposing more fixed positive ionized

Figure 5: Charge distribution in a MO
ircuit diagram. x
d
is the depleted silicon layer thickness.

is
dopants leading to thicker space charge layer. The capacitance of the depleted silicon decreases
and hence the MOS capacitance decreases as the gate voltage is decreased.

-t
ox
0
x

Oxide
Poly-Si
charge density
Silicon
C
ox
-
-
-
-
-
x
d
+ +
+
+ +
C
D
Ionized
Donors
Mobile
Electrons
- - - - -
Oxide
p
+
-poly
+ + + + +
n-Si
Ionized Donors
B
Mobile electrons G
S Capacitor biased into depletion and the equivalent
c
MOSCap01.doc MOS Capacitor Page 4 of 9
Surface Inversion (V
GB
<V
T
)

If the applied gate voltage is lowered below the threshold voltage (V
T
), the semiconductor
surface inverts its conduction type from n-type to p-type in our particular situation. It is natural
to ask why such a thing would occur? Before we answer the question let us define the threshold
voltage (V
T
) as the gate voltage at which the conductivity type of the surface layer changes from
n-type to p-type because more holes have been attracted to the surface comparable to the number
of electrons that existed at the surface at flatband. It demarcates the depletion region from the
inversion region. We shall now proceed to answer the question about why the surface inverts.

Starting from flatband, as the gate voltage is lowered negative mobile carriers (electrons) are
pushed away from the Si/SiO
2
interface, a positive space charge is exposed. We approximate
this as a depletion layer in which we make the assumption that the layer is devoid of all mobile
carriers. However, this is only an approximation. What happens in reality is that the density of
electrons decreases exponentially from the surface going into the bulk. An important fact
pertinent to this discussion is that we assumed that system is in quasi-equilibrium, hence the law
of mass action is still valid. Thus at the surface, the number of electrons decreases as
the applied voltage decreases. Correspondingly, the number of holes at the surface increases as
the applied gate voltage decreases. This is depicted in Figure 6. At a particular voltage called the
threshold voltage (V
T
) the concentration of holes at the surface exceeds the concentration of
electrons in the bulk. The conductivity type of the silicon surface is inverted. Figure 7 shows the
charge distribution of the MOS capacitor in inversion. There is a mobile charge delta-distribution
at the silicon / silicon dioxide interface. Additional increases in the applied gate voltage only
leads to a linear increase in the charge per unit area of the inversion layer. Figure 8 shows the
dependence of the charge density on the applied gate voltage. The inversion layer charge density
is given by

2
i o o
n n p =
[ ] ) (
2
= Ccm V V C Q
T GB ox P


The above expression for the hole density in the inversion layer will be used when considering
the p-MOSFET.

An important fact we need to state is that once the inversion layer forms, the depletion layer
thickness reaches a maximum. The total voltage drop across the semiconductor is pinned at a
maximum value. Increases in the gate voltage applied to the structure is dropped mostly across
the oxide layer as reflected by the expression for inversion layer charge. Thus when the gate
voltage is equal to the threshold voltage, the depleted layer capacitance per unit area reaches a
minimum C
Dmin
and likewise the MOS capacitance. This capacitance is C
min
and it is given by

( )
ox Dmin
MOS T min depletion,min
ox Dmin
Si
Dmin
dmax
C C
C V C A C A
C C
where
C
x
= = =
+

=
MOSCap01.doc MOS Capacitor Page 5 of 9




Figure 6: Semilog plots of the carrier concentration distribution for the MOS capacitor in (a)
accumulation, (b) flatband, (c) depletion and (d) inversion.
MOSCap01.doc MOS Capacitor Page 6 of 9

Figure 7: Ch
the Si/SiO2 interface could be approximated as a

Figure 8: Inversion layer hole charge density as a function of the applied voltage (low frequency
& quasi-static situation). The slope of the line is the oxide capacitance per unit area, C
ox
.

Where do the holes that form the inversion layer come from? In a MOS capacitor in
depletion or inversion, the holes and electrons are generated in the depleted silicon surface
region. The holes are attracted to the Si/SiO
2
interface while the electrons are pushed into the
bstrate. However the holes could also come from a p-doped region that is in close proximity to
e MOS capacitor such as the source/drain region of a p-MOSFET.

d dmax
ions. If you
will like to derive it, I will refer you to 6.012 Text. Microelectronics: An Integrated Approach,
Howe and Sodini.
arge distribution in a MOS Capacitor biased into inversion. The hole distribution at
-distribution.
-t
ox
0
x

charge density
Oxide
Poly-Si
Silicon
C
ox
-
-
-
-
-x
dmax
+ +
+
+ +
C
Dmin
Ionized
Donors
Mobile
Electrons
+
+
+
+
+
Holes at interface
- - - - -
Oxide
Mobile electrons
+ + + + +
n-Si
Ionized Donors
+ + + + +
Holes
Poly-Si
p
+
-poly
G
B

su
th

What are the expressions for x
d
and x
dmax
? I will not try to derive the equations that give you
x and x because they are rather involved, but I will have give you the express
MOSCap01.doc MOS Capacitor Page 7 of 9

( )
( )
( )
2
ox B GB
Si
d GB
ox Si D
B m n n
n
n
D
n
i
2C V
x V 1 1
C qN
where
0.55V
N kT
ln
q n
+
+

+

= +

= =
=
=

( )
D
n Si
d T d
qN
x V x
2 2
max

= =


The next question to be asked is that why are there two value
in the inversion regime?
s of capacitance at any voltage

The capacitance of the structure is usually measured by imposing a DC bias voltage which in our
case will be V
GB
superposed on the DC bias is a small signal which is an alternating current (ac).
This could be a high frequency ac signal (f=1 MHz) or low frequency signal (f<1 kHz). The
frequency of the signal affects the capacitance versus voltage (CV) curve for an MOS capacitor.

The capacitance depends on the measurement frequency and what other structures are connected
to the basic MOS capacitor. At very low frequencies (sometimes referred to as quasi-static
conditions), the generation rate of holes (and electrons) in the depleted silicon surface layer is
fast enough and hence holes are swept to the Si/SiO2 interface where the thin layer holes forms a
sheet of charge. Thus the inversion layer capacitance per unit area under quasi-static conditions
is given

ox
MOS,inversion,QS max
ox
t
C A C

= =
t high frequencies, the generation rate is not fast enough to allow the formation of a hole charge A
density at the Si/SiO
2
interface. In this case the silicon surface depletion layer thickness is still at
its maximum value x
dmax
and the corresponding inversion layer capacitance per unit area at high
frequency is C
min
and it is given by

ox
C
C C A C A = = =
Dmin
MOS,inversion,HF min depletion,min
C
C C +

regions that are in close proximity.
ox Dmin

The inversion layer capacitance of a p-MOSFET even at high frequencies has the same value as
the quasi-static MOS capacitor (C
max
) because there is a ready supply of holes coming from the
p-type source/drain
MOSCap01.doc MOS Capacitor Page 8 of 9
What are the flatband and threshold voltages?

Flatband Voltage

In theory, the flatband voltage should be


In real devices, there is a positive charge located at the Si/SiO
2
interface and it modifies the
-2
( ) ( )
FB B m n n
n
n
D
n
i
V
0.55V
N kT
ln
q n
+
+
= = =
=
=
equation thus
( )
ox
I n m FB
Q V

=

where Q
I
is the Si/SiO
2
interface charge density (#cm )


Threshold Voltage

ox
t
( )
n D Si
ox
ox
n FB T
qN
t
V V

2 2 2 =

m
=
n+
is the gate (metal) potential

n
is the



potential of n-Si substrate
n
i
is the intrinsic carrier concentration of Si (=1x10
10
cm
-3
@ 300K)
t
ox
is oxide thickness

ox
,
Si
the oxide & Si dielectric constants
N
D
is the substrate doping
Q
I
is the oxide charge density at the interface
MOSCap01.doc MOS Capacitor Page 9 of 9