Combinational Logic: Digital Integrated Circuits © Prentice Hall 1995

Digital Integrated Circuits Prentice Hall 1995 Combinational Logic
COMBINATIONAL
LOGIC
Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS
Combinational vs. Sequential Logic
Logic
Circuit
Logic
Circuit
Out
Out
In
In
(a) Combinational (b) Sequential
State
Output = f(In)
Output = f(I n, Previous I n)
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
V
DD
or V
ss
via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Static CMOS
V
DD
V
SS
PUN
PDN
In1
In2
In3
F = G
In
1
In
2
In
3
PUN and PDN are Dual Networks
PMOS Only
NMOS Only
NMOS Transistors in Series/Parallel
Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X
Y
A
B
Y = X if A OR B
NMOS Transistors pass a strong 0 but a weak 1
PMOS Transistors in Series/Parallel
Connection
X
Y
A B
Y = X if A AND B = A + B
X
Y
A
B
Y = X if A OR B = AB
PMOS Transistors pass a strong 1 but a weak 0
PMOS switch closes when switch control input is low
Complementary CMOS Logic Style Construction (cont.)
Example Gate: NAND
Example Gate: NOR
Example Gate: COMPLEX CMOS GATE
V
DD
A
B
C
D
D
A
B C
OUT = D + A (B+C)
4-input NAND Gate
Out
In
1
In
2
In
3
In
4
In
3
In
1
In
2
In
4
In
1
In
2
In
3
In
4
V
DD
Out
GND
V
DD
In1 In2 In3 In4
Vdd
GND
Out
Standard Cell Layout Methodology
V
DD
V
SS
Well
signals
Routing Channel
metal1
polysilicon
Two Versions of (a+b).c
a c b a b c
x
x
GND
V
DD
V
DD
GND
(a) Input order {a c b}
(b) Input order {a b c}
Logic Graph
V
DD
c
a
x
b
c
a
b
GND
x
V
DD
x
c
b a
i
j
i
j
PDN
PUN
Consistent Euler Path
GND
x
V
DD
x
c
b a
i
j
{ a b c}
Example: x = ab+cd
GND
x
a
b
c
d
V
DD x
GND
x
a
b
c
d
V
DD x
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
a c d
x
V
DD
GND
(c) stick diagram for ordering {a b c d}
b
Properties of Complementary CMOS Gates
High noise margins:
V
OH
and V
OL
are at V
DD
and GND, respectively.
No static power consumption:
There never exists a direct path between V
DD
and
V
SS
(GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Properties of Complementary CMOS
Gates
High noise margins:
V
OH
and V
OL
are at V
DD
and GND, respectively.
No static power consumption:
There never exists a direct path between V
DD
and
V
SS
(GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Transistor Sizing
V
DD
A
B
C
D
D
A
B C
1
2
2
2
6
6
12
12
F
for symmetrical response (dc, ac)
for performance
Focus on worst-case
Input Dependent
Propagation Delay Analysis - The Switch
Model
V
DD
V
DD
V
DD
C
L
F
C
L
C
L
F
F
R
p
R
p
R
p
R
p
R
p
R
n
R
n
R
n
R
n
R
n
A
A
A
A
A
A
B
B
B
B
(a) Inverter
(b) 2-input NAND
(c) 2-input NOR
t
p
= 0.69 R
on
C
L
(assuming that C
L
dominates!)
=
R
ON
What is the Value of R
on
?
Numerical Examples of Resistances for 1.2m
CMOS
Analysis of Propagation Delay
V
DD
C
L
F
R
p
R
p
R
n
R
n
A
A
B
B
2-input NAND
1. Assume R
n
=R
p
= resistance of minimum
sized NMOS inverter
2. Determine Worst Case Input transition
(Delay depends on input values)
3. Example: t
pLH
for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
4. Example: t
pHL
for 2input NAND
- Worst case : TWO NMOS in series
t
pLH
= 0.69R
p
C
L
t
pHL
= 0.69(2R
n
)C
L
Design for Worst Case
V
DD
C
L
F
A
A
B
B
2
2
1 1
V
DD
A
B
C
D
D
A
B C
1
2
2 2
2
2
4
4
F
Here it is assumed that R
p
= R
n
Influence of Fan-In and Fan-Out
on Delay
V
DD
A
B
A
B
C
D
C D
t
p
a
1
FI a
2
FI
2
a
3
FO + + =
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
FanIn: Quadratic Term due to:
1. Resistance Increasing
2. Capacitance Increasing
(t
pHL
)
t
p
as a function of Fan-In

1 3 5 7 9
fan-in
0.0
1.0
2.0
3.0
4.0
t
p

(
n
s
e
c
)
t
pHL
t
p
t
pLH
linear
quadratic
AVOI D LARGE FAN-I N GATES! (Typically not more than FI < 4)
Fast Complex Gate - Design
Techniques
Transistor Sizing:
As long as Fan-out Capacitance dominates
Progressive Sizing:
C
L
In
1
In
N
In
3
In
2
Out
C
1
C
2
C
3
M1 > M2 > M3 > MN
M1
M2
M3
MN
Distributed RC-line
Can Reduce Delay with more than 30%!
Fast Complex Gate - Design Techniques
(2)
In
1
In
3
In
2
C
1
C
2
C
L
M1
M2
M3
In
3
In
1
In
2
C
3
C
2
C
L
M3
M2
M1
(a) (b)
Transistor Ordering
critical path
critical path
(3)
Improved Logic Design
(4)
Buffering: Isolate Fan-in from Fan-out
C
L
C
L
Example: Full Adder
V
DD
V
DD
V
DD
V
DD
A B
C
i
S
C
o
X
B
A
C
i A
B B A
C
i
A B C
i
C
i
B
A
C
i
A
B
B A
C
o
= AB + C
i
(A+B)
28 transistors
A Revised Adder Circuit
V
DD
C
i
A
B B A
B
A
A B
Kill
Generate
"1"-Propagate
"0"-Propagate
V
DD
C
i
A B C
i
C
i
B
A
C
i
A
B
B
A
V
DD
S
C
o
24 transistors
Ratioed Logic
V
DD
V
SS
PDN
In
1
In
2
In
3
F
R
L
Load
V
DD
V
SS
In
1
In
2
In
3
F
V
DD
V
SS
PDN
In
1
In
2
In
3
F
V
SS
PDN
Resistive
Depletion
Load
PMOS
Load
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
V
T
< 0
Goal: to reduce the number of devices over complementary CMOS
Ratioed Logic
V
DD
V
SS
PDN
In
1
In
2
In
3
F
R
L
Load
Resistive
N transistors + Load
V
OH
= V
DD
V
OL
=
R
PN
R
PN
+ R
L
Assymetrical response
Static power consumption
t
pL
= 0.69 R
L
C
L
Active Loads
V
DD
V
SS
In
1
In
2
In
3
F
V
DD
V
SS
PDN
In
1
In
2
In
3
F
V
SS
PDN
Depletion
Load
PMOS
Load
depletion load NMOS pseudo-NMOS
V
T
< 0
Load Lines of Ratioed Gates
0.0 1.0 2.0 3.0 4.0 5.0
V
out
(V)
0
0.25
0.5
0.75
1
I
L
(
N
o
r
m
a
l
i
z
e
d
)
Resistive load
Pseudo-NMOS
Depletion load
Current source
Pseudo-NMOS
V
DD
A B C D
F
C
L
V
OH
= V
DD
(similar to complementary CMOS)
k
n
V
DD
V
Tn
( )
V
OL
V
OL
2
2
-------------
\ .
|
| |
k
p
2
------ V
DD
V
Tp
( )
2
=
V
OL
V
DD
V
T
( )
1 1
k
p
k
n
------ (assuming that V
T
V
Tn
V
Tp
) = = =
SMALLER AREA & LOAD BUT STATIC POWER DI SSI PATI ON!!!
Pseudo-NMOS NAND Gate
V
DD

GND
Improved Loads
A B C D
F
C
L
M1
M2
M1 >> M2
Enable
V
DD
Adaptive Load
Improved Loads (2)
V
DD
V
SS
PDN1
Out
V
DD
V
SS
PDN2
Out
A
A
B
B
M1 M2
Dual Cascode Voltage Switch Logic (DCVSL)
Example
B
A A
B
B B
Out
Out
XOR-NXOR gate
Pass-Transistor Logic
I
n
p
u
t
s
Switch
Network
Out
Out
A
B
B
B
N transistors
No static consumption
NMOS-only switch
A = 5 V
B
C = 5 V
C
L
A = 5 V
C = 5 V
B
M
2
M
1
M
n
Threshold voltage loss causes
static power consumption
V
B
does not pull up to 5V, but 5V - V
TN
Solution 1: Transmission Gate
A
B
C
C
A B
C
C
B
C
L
C = 0 V
A = 5 V
C = 5 V
Resistance of Transmission Gate
(W/L)
p
=(W/L)
n
=
1.8/1.2
0.0 1.0 2.0 3.0 4.0 5.0
Vout
0.0
10000.0
20000.0
30000.0
R

(
O
h
m
)
R
n
R
eq
R
p
Pass-Transistor Based Multiplexer
A
M2
M1
B
S
S
S
F
VDD
GND
V
DD

In
1
In
2
S S
S
S
Transmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
Delay in Transmission Gate Networks
V
1 V
i -1
C
5 5
0 0
V
i V
i+1
C
C
5
0
V
n-1 V
n
C
C
5
0
In
V
1
V
i V
i+1
C
V
n-1 V
n
C
C
In
R
eq
R
eq
R
eq
R
eq
C C
(a)
(b)
C
R
eq
R
eq
C C
R
eq
C C
R
eq
R
eq
C C
R
eq
C
In
m
(c)
Elmore Delay (Chapter 8)
R
1
C
1
R
2
C
2
R
i-1
C
i-1
R
i
C
i
R
N
C
N
V
in N
1 2 i-1 i
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin
t
N
R
i
C
j
j i =
N
i 1 =
N
C
i
R
j
j 1 =
i
i 1 =
N
= =
Delay Optimization
Transmission Gate Full Adder
A
B
P
C
i
V
DD
A
A A
V
DD
C
i
A
P
A
B
V
DD
V
DD
C
i
C
i
C
o
S
C
i
P
P
P
P
P
Sum Generation
Carry Generation
Setup
(2) NMOS Only Logic: Level Restoring
Transistor
M
2
M
1
M
n
M
r
Out
A
B
V
DD
V
DD
Level Restorer
X
Advantage: Full Swing
Disadvantage: More Complex, Larger Capacitance
Other approaches: reduced threshold NMOS
Level Restoring Transistor
(a) Output node
(b) Intermediate node X
0 2 4 6
t (nsec)
-1.0
1.0
3.0
5.0
V
o
u
t

(
V
)
0 2 4
t (nsec)
-1.0
1.0
3.0
5.0
V
X
with
without
V
B
with
without
6
Solution 3: Single Transistor Pass Gate with
V
T
=0
Out
V
DD
V
DD
5V
V
DD
0V
5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
Complimentary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=AB
F=AB
OR/NOR
EXOR/NEXOR AND/NAND
F
F
Pass-Transistor
Network
Pass-Transistor
Network
A
A
B
B
A
A
B
B
Inverse
(a)
(b)
4 Input NAND in CPL
Dynamic Logic
M
p
M
e
V
DD
PDN
|
I n
1
I n
2
I n
3
Out
M
e
M
p
V
DD
PUN
|
I n
1
I n
2
I n
3
|
|
Out
C
L
C
L
|
p network
|
n network
2 phase operation:
Evaluation
Precharge
Example
M
p
M
e
V
DD
|
Out
|
A
B
C
N + 1 Transistors
Ratioless
No Static Power Consumption
Noise Margins small (NM
L
)
Requires Clock
Transient Response
0.00e+00 2.00e-09 4.00e-09 6.00e-09
t (nsec)
0.0
2.0
4.0
6.0
V
o
u
t

(
V
o
l
t
)
|
V
out
PRECHARGE
EVALUATION
Dynamic 4 Input NAND Gate
In
1

In
2

In
3

In
4

Out
V
DD

GND
|
Reliability Problems
Charge Leakage
M
p
M
e
V
DD
|
Out
|
A
C
L
(1)
(2)
|
t
t
V
out
(b) Effect on waveforms (a) Leakage sources
precharge
evaluate
Minimum Clock Frequency: > 1 MHz
Charge Sharing (redistribution)
M
p
M
e
V
DD
|
Out
|
A
B = 0
C
L
C
a
C
b
M
a
M
b
X
C
L
V
DD
C
L
V
out
t
( )
C
a
V
DD
V
Tn
V
X
( )
( )
+ =
or
AV
out
V
out
t
( )
V
DD
C
a
C
L
-------- V
DD
V
Tn
V
X
( )
( )
= =
AV
out
V
DD
C
a
C
a
C
L
+
----------------------
\ .
|
| |
=
case 1) if AV
out
< V
Tn
case 2) if AV
out
> V
Tn
Charge Redistribution - Solutions
M
p
M
e
V
DD
|
Out
|
A
B
M
a
M
b
M
bl
M
p
M
e
V
DD
|
Out
|
A
B
M
a
M
b
M
bl
(b) Precharge of internal nodes
|
(a) Static bleeder
Clock Feedthrough
M
p
M
e
V
DD
|
Out
|
A
B
C
L
C
a
C
b
M
a
M
b
X
|
5V
overshoot
out
could potentially forward
bias the diode
Clock Feedthrough and Charge Sharing
0 1 2 3
t (nsec)
0
2
4
6
V

(
V
o
l
t
) |
out
internal node in PDN
output without redistribution (M
a
off)
f
e
e
d
t
h
r
o
u
g
h
Cascading Dynamic Gates
M
p
M
e
V
DD
|
|
M
p
M
e
V
DD
|
|
In
Out1 Out2
|
Out2
Out1
In
V
t
A
V
V
Tn
(a)
(b)
Only 0
1 Transitions allowed at inputs!

Domino Logic
M
p
M
e
V
DD
PDN
|
I n
1
I n
2
I n
3
Out1
|
M
p
M
e
V
DD
PDN
|
I n
4
|
Out2
M
r
V
DD
Static Inverter
with Level Restorer
Domino Logic - Characteristics
Only non-inverting logic
Very fast - Only 1->0 transitions at input of inverter
move V
M
upwards by increasing PMOS
Adding level restorer reduces leakage and
charge redistribution problems
Optimize inverter for fan-out
np-CMOS
M
p
M
e
V
DD
PDN
|
In
1
In
2
In
3
|
M
e
M
p
V
DD
PUN
|
In
4
|
Out1
Out2
Only 1
0 transitions allowed at inputs of PUN

np CMOS Adder
V
DD
|
|
C
i0
A
0
B
0
B
0
|
A
0
V
DD
|
B
1
|
A
1
V
DD
|
|
A
1
B
1
C
i1
C
i2
C
i0
C
i0
B
0
A
0
B
0
S
0
A
0
V
DD
|
|
V
DD
|
V
DD
|
|
B
1
C
i1
B
1
|
A
1
A
1
V
DD
|
S
1
C
i1
Carry Path
Manchester Carry Chain Adder
P
0
C
i,0
P
1
G
0
P
2
G
1
P
3
G
2
P
4
G
3
G
4
|
|
V
DD
M0
M1 M2 M3 M4
C
o,4
1 1.5 2 2.5 3
3.5 3 2.5 2
1.5
1
1.5
2 2.5 3 3.5 4
0.5
Total Area:
225 m 48.6 m
CMOS Circuit Styles - Summary

Combinational Logic: Digital Integrated Circuits © Prentice Hall 1995

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Digital Integrated Circuits Prentice Hall 1995 Combinational Logic

1 Transitions allowed at inputs!

0 transitions allowed at inputs of PUN

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