LOGIC GATES

module logic_gates(a,b,y1,y2,y3,y4,y5,y6,y7,y8);
input a,b;
output y1,y2,y3,y4,y5,y6,y7,y8;
buf (y1,a);
not (y2,a);
o (y3,a,b);
no (y4,a,b);
and (y5,a,b);
nand (y6,a,b);
!o (y7,a,b);
!no (y8,a,b);
endmodule
HALF ADDER & FULL ADDER
module "alf_adde(a,b,sum,cay);
input a,b;
output sum,cay;
!o (sum,a,b);
and (cay,a,b);
endmodule
module full_adde(a,b,c,sum,cay);
input a,b,c;
output sum,cay;
assign sum # a$b$c;
assign cay # (a%b)&(b%c)&(c%a);
endmodule
HALF SUBTRACTOR & FULL SUBTRACTOR
module "alf_subtacto (!,y,diffeence,boo');
input !,y;
output diffeence,boo' ;
assign diffeence # (!$y),
boo' #((!%y);
endmodule
module full_subtacto (!,y,bin,d,bout);
input !,y,bin;
output d,bout;
assign d # (!$y$bin),
bout #((!%y)&((!%bin)&(y%bin);
endmodule
PARALLEL ADDER
module paallel_adde(a,b,cin,sum,cout);
input )3*+, a,b;
input cin;
output )3*+, sum;
output cout;
assign -cout,sum.# a / b / cin;
endmodule
PARALLEL SUBTRACTOR
module paallel_subtacto(!,y,bin,diffeence,bout);
input )3*+, !,y;
input bin;
output )3*+, diffeence;
output bout;
assign -bout,diffeence.# ! 0 y 0 bin;
endmodule
CARRY LOOK AHEAD ADDER
module 123_adde (a,b,cin,sum,cout);
input )3*+,a,b;
input cin;
output)3*+,sum;
output cout;
'ie po,p1,p2,p3,g+,g1,g2,g3;
'ie c1,c2,c3,c4;
assign p+ # (a)+, $ b)+,),
p1 # (a)1, $ b)1,),
p2 # (a)2, $ b)2,),
p3 # (a)3, $ b)3,);
assign g+ # (a)+, % b)+,),
g1 # (a)1, % b)1,),
g2 # (a)2, % b)2,),
g3 # (a)3, % b)3,);
assign c+#cin,
c1#g+ & (p+ % cin),
c2 # g1 & (p+ % g+) & (p1 % p+ % cin),
c3 # g2 & (p2 % g1) & (p2 % p1 % g+) & (p2 % p1 % p+ % cin),
c4 # g3 & (p3 % g2) & (p3 % p2 % g1) & (p3 % p2 % p1 % g+) & (p3 % p2 % p1 % p+
% cin);
assign sum)+,#p+ $ c+,
sum)1,#p1 $ c1,
sum)2,#p2 $ c2,
sum)3,#p3 $ c3;
assign cout # c4;
endmodule
PARALLEL ADDER & SUBTRACTOR
module paallel_add_sub( a3,a2,a1,a+,b3,b2,b1,b+,m,sum3,sum2,sum1,sum+,cout);
input a3,a2,a1,a+;
input b3,b2,b1,b+;
input m;
output sum3,sum2,sum1,sum+;
output cout;
'ie cin,c+,c1,c2,d+,d1,d2,d3;
assign cin # m;
assign d+ # a+$m,
d1#a1$m,
d2#a2$m,
d3#a3$m;
full_add ff+(b+,d+,cin,sum+,c+);
full_add ff1(b1,d1,c+,sum1,c1);
full_add ff2(b2,d2,c1,sum2,c2);
full_add ff3(b3,d3,c2,sum3,cout);
endmodule
module full_add(a,b,c,sum,cay);
input a,b,c;
output sum,cay;
assign sum # a$b$c;
assign cay # (a%b)&(b%c)&(c%a);
endmodule
8 :3 ENCODER & 3:8 DECODER
module encode8_to_3(d+,d1,d2,d3,d4,d5,d6,d7,a,b,c);
input d+,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
o (a,d4,d5,d6,d7);
o(b,d2,d3,d6,d7);
o (c,d1,d3,d5,d7);
endmodule
module decode3_to_8(a,b,c,d+,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d+,d1,d2,d3,d4,d5,d6,d7 ;
assign d+ # ((a % (b%(c),
d1 # ((a % (b%c ),
d2 # ((a % b%(c ),
d3 # ((a % b%c ),
d4 # (a % (b%(c ),
d5 # (a % (b%c ),
d6 # (a % b%(c ),
d7 # (a %b%c );
endmodule
1 :8 DEMULTIPLEXER & 4:1 MULTIPLEXER
module demu!1_to_8(i,s+,s1,s2,d+,d1,d2,d3,d4,d5,d6,d7);
input i,s+,s1,s2;
output d+,d1,d2,d3,d4,d5,d6,d7;
assign d+ # (i % (s2 % (s1 % (s+),
d1 # (i % (s2 % (s1 % s+),
d2 # (i % (s2 % s1 % (s+),
d3 # (i % (s2 % s1 % s+),
d4 # (i % s2 % (s1 % (s+),
d5 # (i % s2 % (s1 % s+),
d6 # (i % s2 % s1 % (s+),
d7 # (i % s2 % s1 % s+);
endmodule
module mu!4_to_1(i+,i1,i2,i3,s+,s1,out);
input i+,i1,i2,i3,s+,s1;
output out;
assign out # (i+ % (s1 % (s+)&(i1 % (s1 % s+)&(i2 % s1 % (s+)&(i3 % s1 % s+);
endmodule
8 BIT MULTIPLIER
module multiplie_8_bit (a,b,c);
input )7*+,a;
input )7*+,b;
output )15*+,c;
assign c)15*+, # a)7*+,4b)7*+,;
endmodule
D FLIPFLOP
module 5_66 (5,cl7,eset,8);
input 5,cl7,eset;
output 8;
eg 8;
al'ays 9 (posedge eset o negedge cl7)
if (eset)
8 # 1:b+;
else
8 # 5;
endmodule
T FLIPFLOP
module ;_66 (;,cl7,eset,8);
input ;,cl7,eset;
output 8;
'ie ';
assign ' # ;$8;
5_66 dff1(',cl7,eset,8);
endmodule
module 5_66 (5,cl7,eset,8);
input 5,cl7,eset;
output 8;
eg 8;
al'ays 9 (posedge eset o negedge cl7)
if (eset)
8 # 1:b+;
else
8 # 5;
endmodule
JK FLIPFLOP
module <=_66 (<,=,cl7,eset,8);
input <,=,cl7,eset;
output 8;
'ie ';
assign ' # (<%(8)&((=%8);
5_66 dff1(',cl7,eset,8);
endmodule
module 5_66 (5,cl7,eset,8);
input 5,cl7,eset;
output 8;
eg 8;
al'ays 9 (posedge eset o negedge cl7)
if (eset)
8 # 1:b+;
else
8 # 5;
endmodule
SYNCHRONOUS UP-DOWN COUNTER
module updo'n_counte(up_do'n,cl7,eset,count);
input )1*+,up_do'n;
input cl7,eset;
output )2*+,count;
eg)2*+,count;
al'ays 9(posedge cl7 o posedge eset)
if (eset##1)count>#3:b+++;
else
if(up_do'n##2:b++ &&up_do'n ##2:b11)
count>#count;
else
if(up_do'n##2:b+1)
count>#count/1;
else
if(up_do'n##2:b1+)
count>#count01;
endmodule
UNIERSAL SHIFT REGISTER
module unis"ft_eg(s1,s+,?@in,26in,A;in,cl7,eset,B3,B2,B1,B+);
input s1,s+; CC select inputs
input 26in,A;in; CC seial inputs
input cl7,eset;
input)3*+,?@in; CC paallel input
output B3,B2,B1,B+; CC egiste output
eg B3,B2,B1,B+;
al'ays 9 (posedge cl7 o posedge eset)
if (eset)
-B3,B2,B1,B+.#4:b++++;
else
case (-s1,s+.)
2:b++*-B3,B2,B1,B+.#-B3,B2,B1,B+.; CC Do c"ange
2:b+1*-B3,B2,B1,B+.#-A;in,B3,B2,B1.; CC E"ift ig"t
2:b1+*-B3,B2,B1,B+.#-B2,B1,B+,26in.; CC E"ift left
2:b11*-B3,B2,B1,B+.#?@in; CC ?aallel load input
endcase
endmodule
CMOS INERTER
module my_inF(in,out);
input in;
output out;
supply1 p';
supply+ gnd;
pmos ( out,p',in);
nmos (out,gnd,in);
endmodule
CMOS NOR GATE
module my_no(a,b,out);
input a,b;
output out;
'ie c;
supply1 p';
supply+ gnd;
pmos ( c,p',b);
pmos (out,c,a);
nmos(out,gnd,a);
nmos(out,gnd,b);
endmodule
CMOS NAND GATE
module my_nand(a,b,out);
input a,b;
output out;
'ie c;
supply1 p';
supply+ gnd;
pmos ( out,p',a);
pmos (out,p',b);
nmos(out,c,a);
nmos(c,gnd,b);
endmodule
SR FLIPFLOP
module s_flipflop(s,,cl7,B,Bba);
input s,,cl7;
output B,Bba;
eg B,Bba;
al'ays9(posedge cl7)
begin
case (-s,.)
2:b++*B#B;
2:b+1*B#1:b+;
2:b1+*B#1:b1;
2:b11*B#1:b!;
endcase
Bba#(B;
end
endmodule
CMOS XOR GATE
module my_!o(a,b,out);
input a,b;
output out;
'ie e,f,g;
supply1 p';
supply+ gnd;
assign c#(a;
assign d#(b;
pmos (e,p',c);
pmos (e,p',d);
pmos (out,e,a);
pmos (out,e,b);
nmos(out,f,a);
nmos(f,gnd,b);
nmos(out,g,c);
nmos(g,gnd,d);
endmodule
SERIAL ADDER
module seial_adde(count2,count1,count+,cl7,a+,a1,a2,a3,a4,a5,a6,a7,a8,esult,add);
input count2,count1,count+;
input cl7;
input a+,a1,a2,a3,a4,a5,a6,a7,a8;
output )3*+,add ,esult;
eg )3*+,esult,add;
al'ays 9 (posedge cl7 )
case (-count2,count1,count+.)
3:b+++ *begin
add#a+/a1;
end
3:b++1 *begin
add#add/a2;
end
3:b+1+ *begin
add#add/a3;
end
3:b+11 *begin
add#add/a4;
end
3:b1++ *begin
add#add/a5;
end
3:b1+1 *begin
add#add/a6;
end
3:b11+ *begin
add#add/a7;
end
3:b111 *begin
esult#add/a8;
end
endcase
endmodule
TRAFFIC LIGHT CONTROLLER
module tlc(state2,state1,state+,cl7,+,y+,g+,p+,1,y1,g1,p1);
input state2,state1,state+;
input cl7;
output +,y+,g+,p+,1,y1,g1,p1 ;
eg +,y+,g+,p+,1,y1,g1,p1;
al'ays 9 (posedge cl7 )
case (-state2,state1,state+.)
3:b+++ *begin
+#1;
y+#+;
g+#+;
p+#1;
1#1;
y1#+;
g1#+;
p1#1;
end
3:b++1 *begin
+#+;
y+#1;
g+#+;
p+#1;
1#1;
y1#+;
g1#+;
p1#1;
end
3:b+1+ *begin
+#+;
y+#+;
g+#1;
p+#+;
1#1;
y1#+;
g1#+;
p1#+;
end
3:b+11 *begin
+#+;
y+#1;
g+#+;
p+#+;
1#+;
y1#1;
g1#+;
p1#+;
end
3:b1++ *begin
+#1;
y+#+;
g+#+;
p+#+;
1#+;
y1#+;
g1#1;
p1#+;
end
3:b1+1 *begin
+#1;
y+#+;
g+#+;
p+#+;
1#+;
y1#1;
g1#+;
p1#+;
end
default *begin
+#+;
y+#+;
g+#+;
p+#+;
1#+;
y1#+;
g1#+;
p1#+;
end
endcase
endmodule