1

Contents
LI M U ......................................................................................................... 2
Chng 1: Tng quan v FPGA .............................................................................. 4
1.1 Khi nim FPGA ............................................................................................ 4
1.2 ng dng ca FPGA trong x l tn hiu s ................................................... 5
1.3 Cng ngh ti cu trc FPGA ......................................................................... 6
1.4 Kin trc tng quan ca FPGA ....................................................................... 8
Chng 2: Kin trc chi tit Xilinx FPGA Spartan-3E ............................................ 9
2.1 Khi logic kh trnh ...................................................................................... 11
2.1.1 Slides...................................................................................................... 11
2.1.2 Bng tham chiu LUT ........................................................................... 15
2.1.3 Phn t nh ............................................................................................ 16
2.1.4 B chn knh m rng ........................................................................... 16
2.1.5 Chui bit nh v chui s hc ................................................................ 19
2.1.6 Ram phn tn ......................................................................................... 20
2.1.7 Thanh ghi dch........................................................................................ 20
2.2 Khi iu khin vo ra ................................................................................ 22
2.3 H thng kt ni kh trnh ............................................................................ 24
2.3.1 Ma trn chuyn ....................................................................................... 25
2.3.2 Cc dng kt ni ..................................................................................... 25
2.4 Khi RAM ................................................................................................... 27
2.5 Khi nhn chuyn dng 18x18 ..................................................................... 28
2.6 Khi iu chnh xung nhp ng b .............................................................. 30
Chng 3: Quy trnh thit k bng ISE.................................................................. 32
3.1 Idea Design .................................................................................................. 33
3.2 Specifications S ch nh r ..................................................................... 33
3.3 RTL .............................................................................................................. 33
2

3.4 Synthesis ...................................................................................................... 34
3.5 Physical Implementation Hin thc ha thit k ....................................... 37
3.6 FPGA test ..................................................................................................... 38
3.6.1 Kim tra bng m phng ........................................................................ 38
3.6.2 Phn tch tham s thi gian tnh ............................................................. 38
3.6.3 Kim tra trc tip trn mch ................................................................... 38
Chng 4:Thit k mt s ng dng c bn .......................................................... 40
4.1 VGA ............................................................................................................. 41
4.1.1 Nhng thng s k thut ca VGA.......................................................... 42
4.1.2 S dng cng VGA ca FPGA Spartan 3E ............................................. 42
4.1.3 nh thi tn hiu cho ch hin th VGA 60Hz, 640x480 .................. 44
4.1.4 S khi .............................................................................................. 46
4.1.5 Khi ng b VGA ................................................................................ 47
4.1.6 Khi m ha a ch cho RAM (encoder_add_ram) ................................ 47
4.1.7 Khi Ram (rom_add) .............................................................................. 48
4.1.8 Khi Character_rom ............................................................................... 49
4.1.9 Khi MUX ............................................................................................. 49
4.1.10 Khi VGA_gen .................................................................................... 50
Kt lun ................................................................................................................. 51

LI M U
FPGA l cng ngh mang li s thay i ln lao trong k thut in t s hin i.
Nu nh cc IC tch hp s trc kia c sn xut bng cng ngh phc tp, s hu
bi s t cc quc gia c nn tng khoa hc k thut pht trin, khi thit k cc h thng
s ngi thit k khng c c s ty bin linh ng cng nh nhng gii php ti u
m phi l thuc vo cc phn t c sn. HDL v FPGA ra i cho php ngi thit k
c kh nng t thit k IC chc nng theo mc ch s dng mt cch nhanh chng
d dng. Bn cnh s tip cn trc tip v n gin FPGA cn em li hiu qu thit k
cao v tnh ng dng thc tin cho nhng bi ton s c xem rt phc tp i vi cc
cng ngh c hn. Nhn thc c tm quan trong ca ngh s cng nh ng dng ca
3

FPGA, cng vi s hng dn ca thy gio Phm Xun Minh, em la chn ti
Tm hiu v xy dng ng dng trn kit FPGA trong mn ti thc tp tt nghip.
Theo , ti c t chc v trnh by trong 4 phn:
1. Gii thiu v FPGA
2. Cu trc chi tit ca FPGA
3. Quy trnh thit k trn ISE
4. Thit k mt s ng dng c th
Vi s hng dn tn tnh ca thy gio Th.s Phm Xun Minh cng vi s c gng ca
bn thn, ti hon thnh vi yu cu t ra trong phm vi nht nh. Tuy nhin do
trnh c hn v thi gian thc hin ti khng cho php, chc chn ti khng th
trnh khi nhng sai st, knh mong c thy v cc bn ng gp kin em tip thu
v hon thin ti mt cch tt nht.
Trn trng
4

Chng 1: Tng quan v FPGA
1.1 Khi nim FPGA
FPGA l cng ngh vi mch tch hp kh trnh (PLD - Programmable Logic
Device) trnh mi nht v tin tin nht hin nay. Thut ng Field-
Programmable ch qu trnh ti cu trc IC c th c thc hin bi ngi dng
cui, trong iu kin thng thng, hay ni mt cch khc l ngi k s lp trnh
IC c th d dng hin thc ha thit k ca mnh s dng FPGA m khng l
thuc vo mt quy trnh sn xut hay cu trc phn cng phc tp no trong nh
my bn dn. y chnh l mt trong nhng c im lm FPGA tr thnh mt
cng ngh IC kh trnh c nghin v cu pht trin nhiu nht hin nay.

c c kh nng , FPGA ra i hon ton l mt cng ngh mi ch
khng phi l mt dng m rng ca cc chip kh trnh kiu nh PAL, PLA... S
khc bit h nht nm c ch ti cu trc FPGA, ton b cu hnh ca FPGA
thng c lu trong mt b nh truy cp ngu nhin (thng thng SRAM),
qu trnh ti cu trc c thc hin bng cch c thng tin t RAM lp trnh
li cc kt ni v chc nng logic trong IC. C th so snh c ch lm vic
ging nh phn mm my tnh cng c lu tr trong RAM v khi thc thi s
c np ln lt vi x l, ni cch khc vic lp trnh li cho FPGA cng d
dng nh lp trnh li phn mm trn my tnh.

Nh vy v mt nguyn tc th qu trnh khi ng ca FPGA khng din ra tc
th m cu hnh t SRAM phi c c trc sau mi din ra qu trnh ti cu
trc theo ni dung thng tin cha trong SRAM. D liu cha trong b nh RAM
ph thuc vo ngun cp, chnh v vy lu gi cu hnh cho FPGA thng phi
dng thm mt ROM ngoi vi. n nhng dng sn phm FPGA gn y th
FPGA c thit k c th giao tip vi rt nhiu dng ROM khc nhau hoc
FPGA thng c thit k km CPLD np nhng thnh phn c nh, vic
tch hp ny lm FPGA np cu hnh nhanh hn nhng c ch np v lu tr cu
hnh vn khng thay i.

Ngoi kh nng im th hai lm FPGA khc bit vi cc PLD th h trc
l FPGA c kh nng tch hp logic vi mt cao vi s cng logic tng ng
ln ti hng trm nghn, hng triu cng. Kh nng c c nh s t ph
trong kin trc ca FPGA. Nu hng m rng ca CPLD tch hp nhiu mng
PAL, PLA ln mt chip n, trong khi bn thn cc mng ny c kch thc ln
5

v cu trc khng n gin nn s lng mng tch hp nhanh chng b hn ch,
dung lng ca CPLD nhiu nht cng ch t c con s trm nghn cng tng
ng. i vi FPGA th phn t logic c bn khng cn l mng PAL, PLA m
thng l cc khi logic lp trnh c cho 4-6 bit u vo v 1 u ra ( thng
c gi l LUT). Vic chia nh n v logic cho php to mt cu trc kh trnh
linh hot hn v tch hp c nhiu hn s lng cng logic trn mt khi bn
dn. Bn cnh hiu qu lm vic v tc lm vic ca FPGA cng vt tri so
vi cc IC kh trnh trc . V c mt tch hp ln v tc lm vic cao nn
FPGA c th c ng dng cho lp nhng bi ton x l s phc tp i hi hiu
sut lm vic ln m cc cng ngh trc khng p ng c.

Thit k trn FPGA thng c thc hin bi cc ngn ng HDL v hu ht
cc dng FPGA hin ti h tr thit k theo hai ngn ng chnh l Verilog v
VHDL, tt c nhng thit k n gin u c th hin thc ha trn FPGA bng
mt quy trnh n gin. Ngoi HDL, thit k trn FPGA cn c th c thc hin
thng qua h nhng ngha l bng ngn ng phn mm (thng l C/C++). Mt
phng php na thng dng trong cc bi ton x l s tn hiu l s dng
System Generator, mt chng trnh kt hp ca Matlab vi phn mm thit k
FPGA ca Xilinx.

Hin nay cng ngh FPGA ang c pht trin rng ri bi nhiu cng ty bn
dn khc nhau. Dn u l Xilinx vi cc dng sn phm nh Virtex 3, 4, 5, 6 v
Spartan3, 6, Altera vi Stratix, Cyclone, Arria. Bn cnh cn c sn phm ca
Lattice Semiconductor Company, Actel, Achronix, Blue Silicon Technology

Khi nim FPGA board, hay FPGA KIT l khi nim ch mt bo mch in trn
c gn chp FPGA v cc phn t khc nh cng giao tip, mn hnh, led, nt
bm v bao gi cng c phn giao tip vi my tnh np cu hnh cho FPGA.
Ngoi ra board cn cha cc thit b ngoi vi c lin kt vi cc cng vo ra ca
FPGA nhm mc ch th nghim.

1.2 ng dng ca FPGA trong x l tn hiu s

Do kh nng ti cu trc n gin v s hu mt khi ti nguyn logic ln
FPGA c th uc ng dng cho nhiu cc lp bi ton x l tn hiu s c ln m
cc cng ngh truc khng lm uc hoc lm uc nhung vi tc v hiu
sut thp. Cc lp ng dng l:
6

- Cc ng dng chung v x l s nh lc tn hiu, tm kim, phn tch, gii
m, iu ch tn hiu, trn tn hiu
- Cc ng dng v m ha, gii m ging ni, nhn dng ging ni, tng hp
ging ni. X l tn hiu m thanh bao gm lc nhiu , trn, m ha,
gii m, nn, tng hp m thanh
- ng dng trong x l nh s, nn v gii nn, cc thao tc bin i,
chnh sa, nhn dng nh s
- ng dng trong cc h thng bo mt thng tin, cung cp cc khi gii m v
m ha c th thc thi vi tc rt cao v d dng tham s ha hoc iu
chnh.
- ng dng trong cc h thng thng tin nh cc h thng Voice IP, Voice mail.
Modem, in thoi di ng, m ha v gii m truyn thng trong mng
LAN, WIFI trong truyn hnh KTS, radio KTS
- ng dng trong iu khin cc thit b in t: cng, my in, my
cng nghip , dn ng, nh v, robots.
Cc sn phm ng dng FPGA hin ti vn nm con s khim tn nu so snh
vi cc gii php truyn thng. Tuy vy vi cc th mnh k trn, FPGA chc
chn s l mt cng ngh quan trng ca tng lai. Mt s nhng kin trc thch
nghi Vi x l FPGA vi nn tng chp vi x l v FPGA c t trong mt chip
n mang li hiu qu x l mnh m do kt hp c tnh linh ng ca phn
mm v hiu sut, tc ca phn cng ang l nhng hng nghin cu mi v
c th to nn s thay i ln vi cc thit k s truyn thng.
1.3 Cng ngh ti cu trc FPGA
Trong lnh vc cng ngh ti cu trc IC hin nay c tt c 5 cng ngh: fuse,
EPROM, EEPROM, SRAM based, Antifuse trong SRAM-based l cng ngh
ph bin c s dng cho FPGA.

SRAM-based
Cu hnh ca FPGA bn cht l m t cc im kt ni gia cc thnh phn c
cha trong IC, c hai dng kt ni c bn l kt ni gia cc ng kt ni dn
bng ma trn chuyn mch (switch matrix), v kt ni ni b trong cc khi logic.
Kt ni trong ma trn chuyn l kt ni gia hai knh dn c thc hin thng
qua cc pass-transitor, hay gi l transitor dn. 1 bit thng tin t b nh SRAM
c s dng ng hoc m pass-transitor ny, tng ng s ngt hay kt ni
gia hai knh dn.

7

Kiu cu trc th hai ph bin trong cc khi logic l lp trnh thng qua khi
chn knh (Multiplexer). Thng tin iu khin t SRAM cho php khi chn knh
chn mt trong s cc u vo a ra. Nu khi lng u vo l 2
n
, th yu
cu s bit iu khin t SRAM l n-bit.

Kiu cu trc th 3 c gi l Look-Up Table (LUT), mi mt LUT c th
c lp trnh thc hin bt k mt hm logic bt k no ca u ra ph thuc
cc u vo. C ch lm vic ca LUT c th tm tt nh sau, gi s cn thc hin
mt hm m u vo v n u ra th cn mt b nh 2
m
x(n), cha thng tin v n
u ra i vi tt c cc kh nng u vo. Khi lm vic th m-bit u vo ng
vai tr nh a ch truy cp (Look-up) ln b nh (Table). V bn cht cu
trc ny cng ging nh khi chn knh c ln. Trong FPGA ph bin s dng
cc LUT c 4-6 bit u vo v 1 bit u ra.


Hnh 1. SRAM-base FPGA
Nh vy tnh kh trnh ca FPGA c thc hin nh tnh kh trnh ca
cc khi logic v tnh kh trnh ca h thng knh kt ni, ngoi ra l
tnh kh trnh ca cc khi iu khin cng vo ra.

8

1.4 Kin trc tng quan ca FPGA
Hnh 1.2 trnh by cu trc tng quan nht cho cc loi FPGA hin
nay. Cu trc chi tit v tn gi ca cc thnh phn c th thay i ty theo cc
hng sn xut khc nhau nhng v c bn FPGA c cu thnh t cc khi
logic (Logic Block) s lng ca cc khi khi ny thay i t vi trm
(Xilinx Spartan) n vi chc nghn (Xilinx Virtex 6, 7) c b tr di dng
ma trn, chng c ni vi nhau thng qua h thng cc knh kt ni kh
trnh. H thng ny cn c nhim v kt ni vi cc cng giao tip vo ra
(IO_PAD) ca FPGA. S lng cc chn vo ra thay i t vi trm n c hn
mt nghn.
Bn cnh cc thnh phn chnh , nhng FPGA c ln cn c tch hp
cng nhng khi thit k sn m thut ng gi l Hard IP cores, cc IP cores ny
c th l cc b nh RAM, ROM, khi thc hin php nhn, khi thc hin php
nhn cng (DSP)... b vi x l c va v nh nh PowerPC hay ARM.


Hnh 1.2. Kin trc tng quan ca FPGA
9

Chng 2: Kin trc chi tit Xilinx FPGA Spartan-3E

Spartan 3E FPGA c nhiu loi khc nhau khc nhau v kch thc, ti
nguyn logic, cch thc ng gi, tc , s lng chn vo ra bng sau lit k cc
tham s ca cc dng FPGA Spartan 3E.


Hnh 2.1

V d theo bng trn XC3S500 c s Slices l 4656, tng ng 1164 CLBs
(10,476 cng tung ung) c b tr trn 46 hng v 24 ct. Cc ti nguyn
khc bao gm 4 khi iu chnh/to xung nhp h thng Digital Clock Manager
(DCM) c b tr 2 trn v 2 dui. Cc khi nh bao gm 360K Block RAM v ti
a 73K RAM phn tn. Tch hp 20 khi nhn 18x18 bt c b tr st cc Block Ram.
V ti nguyn cng vo ra XC3S500E vi gi PQ208 h tr 208 chn vo ra trong
c 8 cng cho xung nhp h thng, ti a 232 cng vo ra s dng t do, trong c
158 chn Input/Output, s cn li l chn Input. XC3S500E c thit k trn cng
ngh 90nm v cho php lm vic xung nhp ti a n 300Mhz, vi tc nh vy
XC3S500 c th p ng hu ht nhng bi ton x l s c va v nh.
10



Hnh 2.2. Kin trc Spartan 3E FPGA

FPGA Spartan 3E c cu trc t cc thnh phn c bn sau:
CLBs: (Configurable Logic Blocks) l cc khi logic lp trnh c
cha cc LUTs v cc phn t nh flip-flop c th c cu trc
thc hin cc hm khc nhau.
IOBs: (Input/Output Blocks) l cc khi iu khin giao tip gia cc chn
vo ca FPGA vi cc khi logic bn trong, h tr c nhiu dng tn hiu
khc nhau. Cc khi IO c phn b xung quanh mng cc CLB.
Block RAM: cc khi RAM 18Kbit h tr cc cng c ghi c lp, vi
cc FPGA h Spartan 3 block RAM thng phn b hai ct, mi ct cha
mt vi khi RAM 18Kbit, mi khi RAM c ni trc tip vi mt khi
nhn 18 bit.
Dedicated Multiplier: cc khi thc hin php nhn vi u vo l cc s
nh phn khng du 18 bit.
DCM (Digital Clock Manager) Cc khi lm nhim v iu chnh,
phn phi tn hiu ng b ti tt cc cc khi khc. DCM thng
c phn b gia, vi hai khi trn v hai khi di. mt
s i FPGA Spartan 3E DCM cn c b tr gia.
Interconnect: Cc kt ni kh trnh v ma trn chuyn dng lin kt cc
phn t chc nng ca FPGA vi nhau.
11


2.1 Khi logic kh trnh

Khi logic kh trnh ca FPGA Xilinx c tn gi y l Configurable Logic
Blocks (CLBs). CLBs l phn t c bn cu thnh FPGA, l ngun ti nguyn
logic chnh to nn cc mch logic ng b ln khng ng b.
Mi CLB c cu thnh t 4 Slices, mi Slice li c cu thnh t 2 LUTs
(Look Up Tables).


Hnh 2.3. Phn b ca cc CLBs trong FPGA

Cc CLB c phn b theo hng v theo ct, mi mt CLB c xc nh
bng mt ta X v Y trong ma trn, i vi Spartan 3E s lng hng thay
i t 22 n 76, s lng ct t 16 n 56 ty thuc vo cc gi c th.

2.1.1 Slides
Mi CLB c cu to thnh t 4 slices v cc slices ny chia lm hai nhm
tri v phi. Nhm 2 slices bn tri c kh nng thc hin cc chc nng logic v lm
12

vic nh phn t nh nn c gi l SLICEM (SLICE Memory). Nhm 2 silces
bn phi ch thc hin c cc chc nng logic nn c gi l SLICEL (SLICE
Logic). Thit k nh vy xut pht t thc t l nhu cu thc hin chc nng logic
thng ln hn so vi nhu cu lu tr d liu, do vic h tr ch mt na lm vic
nh phn t nh lm gim kch thc v chi ph cho FPGA, mt khc lm tng tc lm
vic cho ton khi.

Hnh 2.4. B tr Slice trong CLBs

SLICEL ch thc hin chc nng logic nn ch cha cc thnh phn gm LUT, chui
bt nh (Carry Chain), chui s hc (Arithmetic chain), cc b chn knh m rng
(wide-multiplexer) F5MUX v FiMUX, 2 Flip-flop. Cn i vi SLICEM th ngoi
cc thnh phn trn LUT cn c th c cu hnh lm vic nh mt thanh ghi
dch 16 bit Shift-Register (SRL16), hoc RAM phn tn 16x1bit (Distributed RAM).

13


Hnh 2.5. Phn b ti nguyn trong SLICEM v SLICEL

Cu trc chi tit ca 1 slice:


Hnh 2.6. Cu trc chi tit ca 1 Silce
14

Nhng ng gch t th hin nhng kt ni ti cc ti nguyn m ch SLICEM
mi c, nhng ng gch lin ch nhng kt ni m c hai dng SLICEs u c.
Mi mt slice chia lm hai phn vi cu trc gn nh nhau phn trn v phn di,
mi phn cha cc khi chc nng ging nhau nhng c k hiu khc nhau, v d
G-LUT ch LUT phn trn, F-LUT ch LUT phn di . Tn hiu ng b CLK, tn
hiu cho php ca xung nhp CE (Clock Enable), tn hiu cho php ghi d liu vo
SLICEM SLICEWE1 v tn hiu RS (Reset/Set) l cc tn hiu dng chung cho c phn
trn v phn di ca SLICE.
Cc ng d liu c bn trong Slices l cc ng bt u t cc u vo F[4:1] v
G[4:1] thng ti F-LUT v G-LUT tng ng, ti y s thc hin hm logic t hp theo
yu cu v gi ra cc u ra D. T y u ra D c gi ra cc cng ra ca SLICE
thng qua cc ng sau:
Kt thc trc tip ti cc u ra X, Y v ni ra ngoi vi ma trn kt ni.
Thng qua FMUX (GMUX) ri DMUX lm u vo cho phn t nh
FFX (FFY) sau gi ra thng qua cc u ra QX (QY) tng ng ca cc
phn t nh.
iu khin CYMUXF (CYMUXG) ca chui bit nh.
Gi ti cng XORF (XORF) tnh tng hoc tch ring trong chui nh.
Lm u vo cho F5MUX (FIMUX) trong trng hp thit k cc khi
logic, cc chui nh, thanh ghi dch, RAM m rng.
Bn cnh cc ng d liu c bn trn th trong Slice tn ti cc ng d liu "tt" bt
u t cc u vo BX, BY v kt thc qua mt trong nhng ng sau:
B qua c LUT ln phn t nh v kt thc cc u ra BXOUT,
BYOUT ri ra ma trn kt ni.
B qua LUT nhng lm u vo cho cc phn t nh v kt thc cc
u ra QX, QY.
iu khin F5MUX hoc FiMUX.
Thng qua cc b chn knh, tham gia nh mt u vo ca chui bit nh.
Lm vic nh u vo DI ca LUT (khi LUT lm vic ch
Distributed RAM hay Shift Register).
BY c th ng vai tr ca tn hiu REV cho phn t nh (xem chi tit v REV ti
m t v phn t nh).

15

2.1.2 Bng tham chiu LUT

Hnh 2.7. Phn b cc LUT trn mt Slice

Bng tham chiu (Look-Up Table) gi tt l cc LUT c phn b gc trn tri v
gc di phi ca Slice v c gi tn tng ng l F-LUT v G-LUT. Phn t nh
ng vai tr l u ra ca cc LUT c gi tng ng l Flip-Flop X (FFX) v
Flip-Flop Y FFY. LUT l n v logic v l ti nguyn logic c bn ca FPGA, LUT
c kh nng c cu trc thc hin mt hm logic bt k vi 4 u vo. Cu trc ca
LUT c th hin hnh sau:

Hnh 2.8. Cu trc ca LUT

LUT bn cht l mt b chn knh 16 u vo, cc u vo ca LUT A[3:0]
ng vai tr tn hiu chn knh, u ra ca LUT l u ra ca b chn knh. Khi cn
thc hin mt hm logic bt k no , mt bng nh SRAM 16 bit c to lu tr
16

kt qu bng chn l ca hm, t hp 16 gi tr ca hm tng ng s l cc knh chn
ca khi chn knh. Khi lm vic ty vo gi tr ca A[3:0] u ra D s nhn mt
trong s 16 gi tr lu tr tng ng trong SRAM. Bng cch mt hm logic bt
k vi 4 u vo 1 u ra c th thc hin c trn LUT.
2 LUTs c trong SLICEM c th c cu trc lm vic nh 16x1 RAM gi
l Ram phn tn (Distributed RAM) hoc c cu trc lm vic nh mt thanh
ghi dch 16-bit SHL16. Cu trc ca cc phn t ny s c nghin cu k hn
phn sau.
Cc LUT c th c kt hp vi nhau thc hin cc hm logic ty bin c
s lng u vo ln hn 4 thng qua cc b chn knh m rng. cc th h FPGA v
sau ny, nguyn l lm vic ca LUT vn khng thay i nhng s lng u vo c th
nhiu hn, v d trong Virtex-5, s lng u vo l 6.

2.1.3 Phn t nh
Phn t nh (Storage elements) c trong CLBs l Flip-Flop FFX, FFY c th c cu
hnh lm vic nh D-flip-flop hoc Latch, lm vic vi cc tn hiu iu khin ng
b hoc khng ng b v vy cu trc ca phn t nh trong FPGA phc tp hn
so vi cu trc ca D-flip-flop thng thng. Cc u ra QX, QY ca phn t nh
cng l cc u ra ca Slices. Trong phn ln cc ng dng thng gp phn t nh
c cu trc lm vic nh D-flipflop ng b.
Cc cng giao tip ca mt phn t nh bao gm:
D, Q l cc cng d liu vo v ra tng ng.
C l cng vo xung nhp ng b.
GE (Gate Enable) cng cho php xung nhp C khi lm vic ch latch.
CE (Clock Enable) cng cho php xung nhp C khi lm vic ch flip-flop
S, R l cc cng Set v Reset ng b cho Flip-flop.
PRE, CLR Cng Set v Clear khng ng b.
RS Cng vo ca CLB cho S, R, PRE, hay CLR..
REV Cng vo pha nghch so vi RS, thng c u vo t BY, c tc
dng ngc vi RS. Khi c hai cng ny kch hot th gi tr u ra
ca phn t nh bng 0.
2.1.4 B chn knh m rng
Trong cu trc ca Slice c cha hai b chn knh c bit gi l B chn knh m
rng - Wide-multipexer F5MUX v FiMUX.
17


Hnh 2.9. FiMUX v F5MUX
Mi mt LUT c thit k c th thc hin c mi hm logic 4 u vo. Mc
ch ca cc b chn knh ny l tng tnh linh ng ca FPGA bng cch kt hp cc
phn t logic chc nng nh LUT, chui bit nh, Thanh ghi dch, RAM phn tn
cc Slices, CLBs khc nhau to ra cc hm ty bin vi nhiu u vo hn. V d
bng sau th hin cch s dng 2 LUT 4 u vo v 1 F5MUX to ra mt hm logic
ty bin 5 u vo.
18


Hnh 2.10. Nguyn l lm vic ca F5MUX

u tin i vi hm 5 bin OUT = F(X1, X2, X3, X4, X5) bt k ta thnh lp bng
chn l tng ng, bng ny c chia lm hai phn, phn trn vi tt c cc gi tr
ca X5 bng 0, ta gi hm ny c tn l:
OUT0 = F(X1, X2, X3,X4,0) = F0(X1, X2, X3, X4)
Phn di vi tt c cc gi tr ca X5 bng 1, ta gi hm ny c tn l:
OUT1 = F(X1, X2, X3, X4,1). = F1(X1, X2, X3, X4)
Hai hm F1, F2 l cc hm 4 u vo c thc hin tng ng bi LUT1, LUT2.
Tn hiu X5 c s dng lm tn hiu chn knh cho F5MUX chn 1 trong hai gi
tr u ra ca LUT1, LUT2, u ra ca F5MUX chnh l kt qu ca hm 5 bin cn
thc hin.
OUT = F0(X1, X2, X3, X4) nu X5 = 0
= F1(X1, X2, X3, X4) nu X5 = 1
19


Hnh 2.11. cu to ca F5MUX
F5MUX c thit k da trn nguyn l trn nhng trn FPGA thc t ngoi cng
ra thng thng O theo kt qu gi ra phn t nh ca CLB, th kt qu cn c gi
ra tn hiu tr v LO (Local Output) theo kt qu c th c gi ngc li cc
FiMUX tip tc thc hin cc hm logic c nhiu cng vo hn.
Tng t nh vy c th thnh lp cc hm vi s lng u vo ln hn bng 6, 7, 8
tng ng FiMUX s c gi l F6MUX, F7MUX, F8MUX V d 1 hm 6 bin
th phi thc hin bng cch ghp ni 2 CLB lin tip thng qua F6MUX.
Ngoi thc hin cc hm y vi s kt hp hai LUT to ra hm logic
ty bin 5 u vo th c th kt hp to ra cc hm logic khng y vi 6, 7, 8, 9
u vo.
2.1.5 Chui bit nh v chui s hc
Trong Spartan-3E cng nh trong cc FPGA th h sau ny u c tch hp cc
chui bit nh (carry chain) v cc chui s hc (arithmetic chain) c bit, cc
chui ny kt hp vi cc LUT c s dng t ng hu ht trong cc php ton s hc
thng gp nh cng, nhn, gp phn rt ln vo vic tng tc cho cc php ton ny,
ng thi tit kim ti nguyn logic (LUTs). Cc chui ny c to thnh bng
cc khi chn knh v cc cng logic ring bit, cc phn t cng c th c
s dng c lp thc hin cc hm logic n gin khc.
Chui bit nh thng gp trong php ton cng, vi mi SLICE chui bit nh c
bt u t tn hiu CIN v kt thc COUT. Cc chui n l trong c th c ni
trc tip gia cc CLB vi nhau to thnh cc chui di hn theo yu cu. Mi
mt chui bit nh ny c th c bt u ti bt k mt u vo BY hoc BY no ca
cc Slices.
Cc chui s hc logic bao gm chui thc hin hm XOR vi cc cng XORG,
XORF phn b phn trn v phn dui ca Slice, chui AND vi cc cng GAND,
FAND. Cc chui ny kt hp vi cc LUT thc hin php nhn hoc to thnh cc b
m nh phn.
20

2.1.6 Ram phn tn
Trong mi CLB ca Xilinx FPGA c cha 4 x 16 = 64 bit RAM tng ng vi 4
LUT nm trong 2 SLICEM ca CLB. Phn RAM c th s dng nh mt khi 64-bit
RAM mt cng (Single-port RAM) hoc khi 32-bit RAM hai cng(Dual-port
RAM), khi khi RAM c to thnh t hai mng nh 32-bit v lu tr d liu y ht
nh nhau. V cc RAM ny phn b ri rc theo CLB bn trong cu trc ca FPGA nn
chng uc gi l cc RAM phn tn (Distributed RAM) phn bit vi cc khi
RAM nm tp trung v c kch thc ln hn khc l Block RAM.

Hinh 2.12. RAM phn tn trong FPGA
RAM phn tn trong FPGA c th s dng mt trong hai dng nh hnh v
trn. i vi kiu single-port RAM th c mt ghi d liu 1 cng c d liu. i vi
dual-port RAM th c 1 cng c ghi d liu v mt cng ch thc hin c d liu t
RAM.
i vi thao tc ghi d liu cho c hai kiu RAM c thc hin ng b trong 1
xung nhp WCLK, tn hiu cho php ghi l WE (Write Enable, theo ngm nh tch
cc nu WE = 1). i vi Dual-port RAM th mi ng tc ghi s thc hin
ghi d liu t cng D vo hai phn nh ca RAM.
Ti nguyn RAM phn tn trong FPGA c s dng ht sc linh ng, mt khi
CLB n l c th c cu hnh to thnh cc khi 64x1, 32x2, 16x4
Distributed RAM, cc u vo G[4:1] v F[4:1] c dng nh cc u vo a ch.
Cc khi RAM ln hn c th cu to bng cch ghp ti nguyn trong cc CLB khc
nhau li s dng cc b chn knh m rng, khi cc cng BX, BY c s dng
nh cc bit a ch b xung.
2.1.7 Thanh ghi dch
Mt dng s dng khc ca cc LUTG, v LUTF trong SLICEM l dng nh
mt thanh ghi dch (Shift Register) 16 bit k hiu l SRL16.
21


Hnh 2.13. S dng LUT nh thanh ghi dch 16-bit
Khi s dng LUT nh mt thanh ghi dch, cu trc ca LUT v c bn gi nguyn,
cc knh chn c ni vi chui cc D flip-flop lm vic ng b. u ra D vn nhn
gi tr ti u ra Q ca D-flip-flop quy nh bi gi tr a ch A[3:0], chnh v vy
SRL16 cn c gi l thanh ghi dch c a ch. Ngoi u ra D thanh ghi dch c u ra
cui cng c tn l Q15 hoc MC15 quy nh trong th vin cc phn t chun ca
FPGA. u vo DI c th c bt u t cng BY. BX hoc u vo SHIFTIN t ngoi
CLB. Tn hiu xung nhp ng b CLK v CE c ly t tn hiu ng b chung ca
Slices.
u ra ca MC15 ca SRL16 c th c ni tip vi cng SHIFTOUT ca Slice hoc
YB. u ra a ch D c th c gi trc tip ra ngoi Slice hoc thng qua FFX hoc
FFY, khi chui dch tnh thm mt n v, trn thc t tr ca FFX, FFY thng
nh hn so vi tr ca cc D-flip-flop trong thanh ghi dch.
22


Hnh 2.14. Cu trc ca thanh ghi dch trong FPGA
2.2 Khi iu khin vo ra
S nguyn l ca khi iu khin vo ra (Input/Output Block) trong Spartan 3E
c trnh by nh hnh di y:
23


Hnh 2.14. S nguyn l ca khi vo ra IOB
Cc khi Input/Output Blocks (IOB) trong FPGA cung cp cc cng vo ra lp trnh
c mt chiu hoc hai chiu gia cc chn vo ra ca FPGA vi cc khi logic bn
trong. Cc khi mt chiu l cc khi Input-only ngha l ch ng vai tr cng vo, s
lng ca cc cng ny thng chim khng nhiu khong 25% trn tng s ti nguyn
IOB ca FPGA.
Hnh 2.14 m t s tng quan ca mt IOB, i vi cc khi Input-only th khng c
nhng phn t lin quan n Output. Mt IOB in hnh c ba ng d liu chnh,
ng input, ng output, ng cng 3 trng thi (Three state path), mi ng ny
u cha cc khi lm tr lp trnh c v cp phn t nh c kh nng lm vic nh
Latch hoc D-flipflop.
24

ng Input dn d liu t cc chn vo ra ca FPGA c th qua hoc khng qua
khi lm tr kh trnh vo gi ti thng chn d liu I. ng Input th hai i qua
cp phn t nh ti cc chn IQ1, IQ2. Cc chn I, IQ1, IQ2 dn trc tip ti phn
logic bn trong ca FPGA. Khi s dng cc khi lm tr kh trnh th thng c
cu hnh m bo ti u cho yu cu v gi tr hold time ca phn t nh.
ng Output bt u ti cc chn O1, O2 c nhim v dn lung d liu t cc
khi logic bn trong ti cc chn vo ra ca FPGA. ng dn trc tip l ng
dn t O1, O2 qua khi chn knh ti khi dn 3 trng thi ti cc chn vo ra.
ng dn th hai ngoi cc phn t trn cn i qua hai phn t nh. u ra cn
c ni vi h thng pull-up, pull-down resisters t cc gi tr cng ra l
logic 1 hoc 0.
ng 3 trng thi xc nh khi no ng dn ra l trng thi tr khng cao.
ng trc tip t cc chn T1, T2 ti khi iu khin 3 trng thi. ng gin
tip i qua hai phn t nh trc khi ti khi iu khin 3 trng thi.
Mt trong nhng ng dng ca khi lm tr l m bo khng vi phm iu
kin ca Thold khi phn t nh hot ng (Thold l thi gian ti thiu cn gi n nh d
liu sau thi im kch hot ca xung nhp ng b), v d nh hnh v sau:

Hnh 2.15. iu chnh u vo bng khi lm tr kh trnh
2.3 H thng kt ni kh trnh
H thng kt ni kh trnh (Progammable Interconnects) ca FPGA dng lin kt
cc phn t chc nng khc nhau bao gm IOB, CLB, Block RAM, khi nhn chuyn
dng, DCM vi nhau. H thng kt ni ca FPGA c thit k cn bng gia yu t linh
ng v tc lm vic (gim thiu tr do ng truyn gy ra). i vi cc FPGA h
Spartan 3E c 4 loi kt ni sau: kt ni xa (long lines), kt ni kp (double lines), kt
25

ni ba (hex lines), kt ni trc tip (direct line). Cc dng kt ni ny lin h vi nhau
thng qua cu trc ma trn chuyn (switch matrix).
2.3.1 Ma trn chuyn
Ma trn chuyn (Switch matrix) l cc khi thc hin kt ni gia cc dng ti
nguyn kt ni ca FPGA bao gm kt ni xa, kt ni kp, kt ni ba, kt ni trc tip.
lin kt (interconnect tiles) c nh ngha l mt khi bao gm ma trn chuyn v cc
phn t chc nng ca FPGA nh IOB, CLB, Block RAM, Dedicated Multipliers, DCM.

Hinh 2.16. Cc thnh phn ni khc nhau trong Xilinx FPGA
Vi CLB, IOB, DCM ch cn 1 ma trn chuyn to thnh mt kt ni nhng vi
cc phn t ln hn nh Block RAM hay MULT18 th cn nhiu ma trn kt ni tng
ng c s kt ni ln hn.
2.3.2 Cc dng kt ni
Kt ni xa - Long line

Hnh 2.17. ng kt ni di
ng kt ni di gm t hp 24 ng ni 1 trong 4 CLB lin tip theo
phng ngang hoc phng dc. T mi kt ni c 4 ng kt ni thng qua
26

ma trn chuyn ni vi cc cn li. ng kt ni xa c tr khng thp do
vy thch hp cho nhng tn hiu ton cc nh CLK hay Reset.
Kt ni 3- Hex lines
hf
Hnh 2.18. ng kt ni 3

Kt ni 3 l knh kt ni gm 8 ng ni ti 1 trong 3 CLB lin tip, i vi
kt ni dng ny tn hiu ch c th truyn t mt u xc nh ti cc u khc
theo hng mi tn nh hnh 2.18.
Kt ni kp Double lines

Hnh 2.18. ng kt ni kp
Kt ni kp l knh kt ni gm 8 ng ni ti 1 trong 2 CLB lin tip, i
vi kt ni dng ny tn hiu ch c th truyn t mt u xc nh ti cc im
khc nh hex lines. S lng ca double lines trong FPGA ln hn nhiu so vi
hai dng Long lines v Hex lines do kh nng kt ni linh ng.
Kt ni trc tip - Direct lines

Hnh 2.19. ng kt ni trc tip
Kt ni trc tip kt ni cc CLB cnh nhau theo phng ngang, dc v cho
m khng cn thng qua ma trn kt ni.
Vic phn cp cc ti nguyn kt ni trong FPGA tuy lm cho vic thit k bn thn
FPGA phc tp hn cng nh tng phc tp cho thut ton kt ni ng truyn
nhng gp phn rt ln vo vic tit kim din tch v ti u ha thit k trn FPGA. Trn
27

thc t vic s dng ti nguyn kt ni trong FPGA c thc hin t ng, bn thn
ngi thit k t tham gia vo qu trnh ny hoc nu c ch l to cc tn hiu ton cc
kiu nh CLK, RS, TST s dng phn b c ti u ha ca cc tn hiu ny.
2.4 Khi RAM
Bn cnh ngun ti nguyn lu tr d liu nh trnh by trn l RAM phn tn
(Distributed RAM) vi bn cht l mt hnh thc s dng khc ca LUT th trong Xilinx
FPGA cn c tch hp cc RAM (Block RAM) ring bit c cu hnh nh mt khi
RAM hai cng, s lng ny trong Spartan 3E thay i t 4 n 36 ty theo tng IC c
th. Tt c Block RAM hot ng ng b v c kh nng lu tr tp trung mt khi
lng ln thng tin. Giao din ca mt Khi RAM nh sau:

Hnh 2.20. Giao din khi RAM
Khi RAM c hai cng A v B vo ra cho php thc hin cc thao tc c ghi c lp
vi nhau, mi mt cng c cc tn hiu xung nhp ng b, knh d liu v cc tn hiu
iu khin ring. C 4 ng d liu c bn nh sau:
1) c ghi cng A
2) c ghi cng B
3) Truyn d liu t A sang B
4) Truyn d liu t B sang A
V tr ca cc Block RAM ny trong FPGA thng c b tr nh hnh sau:
28


Hnh 2.21. Phn b ca cc khi RAM trong Spartan 3E FPGA
Ty theo tng FPGA c th m c th c t mt n 5 ct b tr Block RAM, cc ct ny
thng c b tr bn cnh cng cc khi nhn 18-bit. 16-bit cng A phn thuc khi
nh bn trn dng chung vi 16 bit cng A, tng t nh vy vi 16 bit cng B ca
Block RAM c chia s vi 16 bit cng B ca khi nhn.
2.5 Khi nhn chuyn dng 18x18
Cc khi nhn chuyn dng 18bitx18bit (Dedicated Multiplier) c thit k
ring, thng c ng dng trong cc bi ton x l tn hiu s, k hiu l
MULT18X18SIO trong th vin chun ca Xilinx.
Cc khi nhn c t ti cc v tr st vi cc Block RAM nhm kt hp hai khi
ny cho nhng tnh ton ln vi tc cao. S lng ca cc khi ny bng vi s
lng ca cc khi RAM trong FPGA, ngoi ra hai thnh phn ny cn chia s vi nhau
cc cng A, B 16 bit dng chung..
Khi nhn trong Spartan 3E thc hin php nhn hai s 18 bit c du, kt qu
l mt s 36 bit c du. Php nhn khng du c thc hin bng cch gii hn min
ca s nhn v s b nhn (bit du lun bng 0). M t cc cng vo ra ca phn t
nhn MULT18X18SIO th hin hnh sau:
29


Hnh 2.21. Cng vo ra ca khi nhn 18 bit
Khi nhn c tt c 13 cng vo ra vi cc chc nng nh sau:
A, B[17:0] l cng vo 18 bit s nhn v s b nhn.
P[35:0] l 36 bit kt qu nhn (Product).
CEA, CEB l tn hiu cho php xung nhp cc u vo A, B.
RSTA, RSTB, RSTP l cc cng Set/Reset ng b tng ng cho cc gi tr A, B,
P.
CLK l tn hiu xung nhp ng b cho cc Flip-flop trong khi nhn.
BCIN, BCOUT[17:0] l cc cng vo ra tng ng nhm chia s gi tr s b nhn
gia cc khi nhn vi nhau nhm mc ch to thnh cc khi nhn nhiu
bit hn. BCOUT = BCIN.
Pipelined option: Khi nhn c th c thc hin nh mt khi t hp thun
ty hoc c th chia nh bi cc thanh ghi t hiu sut lm vic cao hn. Cu trc
pipelined ca khi nhn th hin hnh sau:
30


Hnh 2.21. Cu trc pipelined ca khi nhn
Cc nhn t A, B v kt qu P c th c lu trong cc thanh ghi trung gian gm
AREG, BREG, PREG, mi thanh ghi l mt chui cc Flip-flop. Trong cu trc
pipelined th REGA, REGB c cng mc.
2.6 Khi iu chnh xung nhp ng b
Digital Clock Manager (DCM) l mt khi c bit trong FPGA c nhim v iu
chnh v to ra xung nhp ng b (Clock) theo nhng yu cu c th ca bi ton. DCM
c cu to khng n gin v c s lng hn ch (2-4 DCM trong Spartan 3E). 3
thao tc chnh m khi DCM c th thc hin l:
- Loi b tr gia cc xung Clock cc v tr khc nhau (Clock
Skew Elimination). Xung ng b gi ti cc thnh phn khc nhau trong
FPGA c th khng n ng thi do s khc bit v ti ng truyn. DCM
c kh nng tng cc gi tr Thold, Tsetup ca xung ng b v thi gian t
im kch hot cho ti khi u ra n nh Tclk_q ng nht cc xung
ng b. Trong cc bi ton i hi lm vic vi tn s cao th y l mt trong
nhng thao tc khng th b qua.
- Tng hp tn s (Frequency Synthesis): Tng hp tn s y bao gm
nhn v chia tn s, vi tn s c nh u vo DCM c th thc hin thao tc
nhn tn s vi 1 s M, chia cho mt s D hoc ng thi nhn v chia M/D.
y l mt kh nng c bit quan trng cho nhng bi ton yu cu tn s lm
vic l c nh nh iu khin VGA, DAC, ADC, LCD
31

- Dch pha (Phase shifting) Dch pha ca xung nhp ng b i 0, 90, 180, hoc
270 .

Hnh 2.22. S khi DCM
Khi DCM c cu to t 4 khi chnh, khi dch pha PhS (Phase
shifter), khi lp kha pha DLL (Delay Locked Loop), khi tng hp tn s DFS
(digital Frequency Synthesis) v khi Trng thi logic ca DCM.

32

Chng 3: Quy trnh thit k bng ISE
Mt trong nhng yu t gp phn vo s thnh cng ca FPGA phi
k n l c mt quy trnh thit k n gin, hon thin c thc hin bng cc
b phn mm chuyn dng. Cc phn mm ny c tch hp nhiu cc thut ton
x l ti u khc nhau nhm tng tnh t ng ha cho quy trnh thit k. Trong
ti ny tp trung tm hiu phn mm thit k FPGA bng Xilinx ISE (Integrated
Software Enviroments).
C mt s im khc nhau cho tng loi FPGA hay cho FPGA ca tng hng
nhng quy trnh thit k IC s s dng FPGA chung u c th chia thnh nm
bc th hin s di y:

Hnh 3.1. FPGA Design Flow

33

3.1 Idea Design
thit k mt con chip, ngi thit k cn c tng mt cch chnh xc
nhng g con chip s hot ng. Tt c cc bc thit k tip theo lun phi
m bo tng thit k ng nh ban u.
3.2 Specifications S ch nh r
y l bc u tin bin tng vo trong mt con chip. Specifications ch ra
nhng mc ch c th ca thit k:
Mc ch v nhng rng buc ca thit k.
Chc nng ca chip.
Hiu sut ca chip nh tc v nng lng tiu th.
Nhng rng buc v cng ngh nh kch thc (ASIC)
Cng ngh sn xut v k thut thit k (ASIC)
Trong bc ny cng ch r kiu kin trc m ngi thit k mong mun nh
RISC/CISC, ALU, pipelining d dng cho vic thit k mt h thng phc tp,
ngi ta thng chia nh thit k thnh nhiu khi nh. Chc nng ca cc khi ny cng
c ch nh r. ng thi, mi quan h gia cc khi vi nhau v vi ton b h thng
cng c xc nh c th.
3.3 RTL
Khi ton b h thng c ch nh r, thit k cn phi c thc thi. Thit k
c thc thi bng din t logic (Boolean Expressions), my bin trng thi (Finite State
Machines), mch t hp (Combinational), mch tun t ( Sequencial), Schematic Bc
ny c gi l Logic Design/RTL Design (Register Transfer Level). RTL v c bn m
t cc khi nh trong h thng. RTL thng c miu t bng Verilog hoc VHDL,
c gi l ngn ng m t phn cng (Hardware Description Languages). HDL c
dng m t h thng s nh mt vi x l, b nh hay mt flip flop n gin. iu ny
c ngha l, bng cch s dng ngn ng m t phn cng, ta c th m t mt phn cng
(digital) bt k, ti bt k mc no. Funtional/ Logical Verification l cng on dm
bo rng RTL design ng vi mc ch thit k ban u.
Bn cnh dng m t HDL ca ngi dng th c dng m t HDL th hai s
dng cc khi thit k c sn. Loi m t ny c hai dng, th nht l cc khi thit k
c nh ngha trong th vin UNISIM ca Xilinx. Khi mun ci t cc khi ny th
phi khai bo thm th vin Unisim u thit k:
library UNISIM;
use UNISIM.VCOMPONENTS.all;
34

Mt s khi thit k in hnh l cc LUT, thanh ghi dch, Block RAM,
ROM, DCMc th tm thy trong Language template ca ISE, cc khi ny gi
chung l cc phn t c bn ca FPGA (FPGA primitives), c im ca cc khi ny l
ph thuc vo i tng FPGA c th.

Hnh 3.2. Cc dng m t thit k trn FPGA
Ngoi FPGA primitives th ISE cho php ngi dng s dng mt s khi thit k sn
dng IPCore (Intellectual Property core). IP core l cc khi thit k sn c ng k s
hu tr tu v thng l cc thit k kh phc tp v d nh cc khi FIFO, khi lm
vic vi s thc (Floating Point Unit), khi chia, cc khi CORDIC, cc khi giao
tip Ethernet, PCI EXPRESS, SPI, cc khi x l s tn hiu Trong khun kh
chng trnh hc th vic s dng ny l c php tuy vy nu mun s dng cc khi
ny vi mc ch to ra sn phm ng dng th cn xem xt k vn bn quyn. Vi s
h tr phong ph ca cc IP Cores ny cho php thc hin nhng thit k ln v hu
dng trn FPGA. Lu l khi s dng cc khi ny th phn thit k HDL thc s cng
b giu i m chng trnh ch cung cp cc m bin dch v m t giao din
(wrapper file) ca IPCore c s dng.
3.4 Synthesis
Cng c Synthesis ly file RTL cng vi th vin chun to ra mt file neslist.
Qu trnh tng hp FPGA (FPGA Synthesis) bng chng trnh ISE bao
gm cc bc nh sau.
35


Hnh 3.3. Tng hp thit k FPGA trn Xilinx ISE

Check Syntax & Synthesis: Trc khi thit k c tng hp th m ngun VHDL
c bin dch v kim tra trc. Nu xut hin li c php m ngun th qua trnh
tng hp s dng li. Nu m t VHDL khng c li th chuyn sang bc th
hai l tng hp (synthesis). Tng hp thit k l chuyn m t t mc tru tng cao (con
ngi c th c hiu) xung mc tru tng thp hn (my tnh mi c kh nng c
hiu). i vi FPGA qu trnh tng hp logic l qu trnh bin dch t m t chc nng
sang m t cng (netlist). M t cng bn cht vn l cc m t VHDL nhng s
dng cc phn t ca FPGA, hiu mt cch khc nu m t chc nng l s
nguyn l th m t netlist l s chi tit ha s nguyn l. C th so snh m di dng
Netlist nh m Assembly ca chng trnh gc m t bng cc ngn ng lp trnh
bc cao C/C++, Pascal, Basic...
Cc m ngun VHDL c chia thnh hai dng l tng hp c
(Synthesizable code) v khng tng hp c (Simulation-only code), vic phn bit hai
dng m ngun ny c ISE lm t ng. Khi c tnh tng hp mt cu trc ch dng
cho m phng th s gy ra li. Ngi thit k v vy ngoi vic m bo chc
nng lm vic ng cho mch cn lun phi m bo rng nhng cu trc vit ra l
nhng cu trc c th to thnh mch tht ngha l tng hp c.
Kt xut m t netlist: m t netlist l m t VHDL ca thit k nhng c
nh x ln th vin phn t logic ca FPGA. M t netlist l dng m t mc cng v
vy khng m t trc quan c chc nng ca vi mch m ch th hin c cu trc
ca mch, trong cc khi con (components) l cc phn t c bn c m t trong
th vin UNISIM ca FPGA.
Netlist c th khng phn nh ng bn cht thc t ca mch m m t ny ny ch
s dng kim tra li chc nng ca vi mch sau khi nh x ln th vin phn t FPGA.
Vic kim tra ny c thc hin ging nh kim tra m t VHDL ban u, tc l c th
dng bt k chng trnh m phng logic no m h tr th vin UNISIM.
36

Create Technology schematic (S cng ngh chi tit) Sau khi tng hp chng
trnh cng cho php kt xut s cng ngh chi tit ca thit k m bn cht l m t
trc quan bng hnh nh ca netlist, v d mt s cng ngh chi tit hnh sau:

Hnh 3.4. Schematic tng hp c trn ISE

Vic so snh s ny vi s nguyn l bc ban u cho php kim tra
trc quan s b vic thc hin ng s nguyn l ca m t VHDL.
Create RTL schematic (S logic chi tit) S logic chi tit l s th
hin chc nng ca thit k s dng cc cng logic chun nh AND, OR, NOT,
FFD thay v s dng cc phn t chun ca FPGA, s ny v th khng ph thuc vo
i tng cng ngh c th.


Hnh 3.5. S logic chi tit
37

3.5 Physical Implementation Hin thc ha thit k
File neslist c chuyn thnh dng m t hnh hc. Physical Implementation gm c 3
bc: Floor planning->Placement->Routing.
Place and Routing
Placing & Routing (PAR) l qu trnh nh x nhng khi logic c phn
chia phn Maping sang nhng khi logic (LUT, IOBUF) c v tr c c th trn
FPGA v kt ni chng li vi nhau thng qua khi ti nguyn kt ni. Ngi thit k c
th can thip vo qu trnh ny bng FPGA editor, mt cng c giao din ha tch hp
trong ISE, nhng trn thc t th qu trnh ny thng thc hin hon ton t ng bng
cng c PAR (Place and Route).

Hnh 3.6. Phn b v kt ni
Placing: bc ny PAR la chn cc khi logic chc nng c th phn b trn
FPGA gn cho cc khi chc nng trn m t thit k, vic la chn da trn cc tiu
ch nh ngun ti nguyn, di kt ni, iu kin rng buc trong PCF file Qu trnh
ny thc hin thng qua mt s pha, kt thc mi pha th thit k c ti u thm mt
mc, kt thc Placing mt kt qu NCD mi c to ra.
Routing: l qu trnh tin hnh s dng cc ti nguyn kt ni (interconnects),
cc kt ni c thc hin nhm t thi gian tr thp nht c th, khi kt ni PAR
s phi quan tm ti thng tin trong PCF file. Qu trnh ny cng c thc hin thnh
38

nhiu pha, mi pha mt file NCD mi s c lu li nu nh c c s ti u v thi
gian so vi phng n trc .
Floorplaning: L qu trnh cho php ngi thit k s dng FPGA editor can thip
vo qu trnh Placing v Routing, bc ny c th lm trc hoc sau cc bc ca
PAR.
3.6 FPGA test
Thit k trn FPGA c th c kim tra nhiu mc khc nhau v c chc
nng ln v cc yu cu khc v mt ti nguyn hay hiu sut lm vic.

Hnh 3.7. Kim tra thit k FPGA
3.6.1 Kim tra bng m phng
Cc cng c m phng c th dng m phng chc nng (Functional Simulation) ca
mch thit k v m phng v mt thi gian (Timing simulation). Kim tra c th c
thc hin t bc u tin ca qu trnh thit k (m t VHDL) cho ti bc cui
cng (PAR).
3.6.2 Phn tch tham s thi gian tnh
Phn tch thi gian tnh (Static timing analysis) cho php nhanh chng xc nh cc
tham s v mch thi gian sau qu trnh Place & Routing, kt qu ca bc kim tra ny
cho php xc nh c hay khng cc ng truyn vi phm cc iu kin rng buc
v mt thi gian, ch ra cc ng gy tr vi phm ngi thit k tin hnh nhng
thay i ti u mch nu cn thit.
3.6.3 Kim tra trc tip trn mch
Kim tra trc tip trn mch (On-circuit Testing) l qu trnh thc hin sau khi
cu hnh FPGA c np vo IC, i vi nhng thit k n gin th mch c np
c th c kim tra mt cch trc quan bng cc i tng nh mn hnh, LED, switch,
cng COM.
Vi nhng thit k phc tp Xilinx cung cp cc cng c phn mm kim tra ring.
ChipScope l mt phn mm cho php kim tra trc tip thit k bng cch nhng thm
39

vo trong khi thit k nhng khi c bit c kh nng theo di gi tr cc tn hiu
vo ra hoc bn trong khi cu hnh c np v lm vic. ChipScope s dng chnh giao
thc JTAG giao tip vi FPGA. Vic thm cc khi g ri vo trong thit k lm tng
kch thc v thi gian tng hp thit k ln ng k. Chi tit hn v cch s dng
Chipscope Pro c th xem trong ti liu hng dn ca Xilinx.

40

Chng 4:Thit k mt s ng dng c bn
S mt khi thit k chun trn FPGA c th chia thnh cc khi chnh nhuw hnh v
sau:

Hnh 4.1. S khi thit k y trn FPGA

41

Hnh 4.2. S mch th nghim FPGA
Trong mch s dng IC FPGA Spartan 3E XCS500K, Flash ROM XFC04 vi 4M
cho lu tr c nh cu hnh. Mch c np thng qua giao thc chun JTAG. Cc ngoi
vi h tr bao gm: Khi to xung nhp tn s 48Mhz, H thng cc 7 phm n a chc
nng, 2 khi Switch 8-bit, 2 khi Led 8-bit, Led 7 on vi c kh nng hin th 4 k t
s, 2 cng giao tip PS/2, cng giao tip RS232, cng giao tip USB-RS232, cng giao
tip VGA, mn hnh LCD1602A hin th cc k t vn bn, cng giao tip CAN, cng
giao tip Ethernet, khi AD/DA s dng IC PCF8591. Mch dng mt ngun ngoi duy
nht 5V vi dng ti thiu 1A.

Khi nim v VGA
VGA (hay Video Graphics Array) l mt chun hin th trn mn hnh my tnh c
gii thiu nm 1987 t pha IBM cng vi dng my tnh PS/2. N c th hiu l thit b
xut ha di dng Video thnh tng dy ra mn hnh v c th hin th 256 mu bin
i lin tc cng mt lc, vi phn gii 640 dng chiu ngang v 480 dng chiu dc.
Chun VGA tng thch li vi tt c cc chun hin th trc , nh CGA, MDA v
EGA.
Chun VGA cao EGA hn khng nhng ch v phn gii cao, m cn v cng
ngh VGA cho php gi vng t l co gin ca cc hnh ha trn mn hnh my tnh.
Chun VGA cng dng cng ngh tn hiu u vo dng tng t to ra mt s lng
khng hn ch cc mu sc bin i theo mt di lin tc, trong khi EGA dng cng
ngh mn hnh s nn b gii hn v s lng cc mc cng mu.
4.1 VGA
Chun VGA ca IBM c cc hng sn xut thit b nng ln cao hn khi a ra
cc b iu hp VGA (Video Graphics Adapter Card mn hnh) c kh nng hin
th thm cc ch ha b sung. l ch Super VGA c phn gii 800
pixel dng chiu ngang v 600 dng chiu dc, v cc b iu hp cao cp hn cho
php hin th phn gii 1024 x 768 hoc cao hn, mc ti thiu 256 mu (8
bit).
42

4.1.1 Nhng thng s k thut ca VGA
Vi kh nng hin th hnh nh ng trn mn hnh Analog CRT, chun VGA c
cc thng s tiu chun sau :
256 KB Video RAM
Cc ch 16-mu v 256-mu
262144-gi tr trong bng mu (su bit cho mi mu Red, Green v Blue
C th la chn gia tn s 25.2 MHz hoc 28.3 MHz
S im nh ngang ln nht : 720 im
S hng 480 hng
Tn s lm ti ln n 70 Hz
Vi kh nng hin th hnh nh ng trn mn hnh Analog CRT, chun VGA c
cc thng s tiu chun sau :
256 KB Video RAM
Cc ch 16-mu v 256-mu
262144-gi tr trong bng mu (su bit cho mi mu Red, Green v Blue
C th la chn gia tn s 25.2 MHz hoc 28.3 MHz
S im nh ngang ln nht : 720 im
S hng 480 hng
Tn s lm ti ln n 70 Hz
in p tn hiu 0.7 V peak-peak
4.1.2 S dng cng VGA ca FPGA Spartan 3E
Bo mch Spartan-3E kit c mt cng ra VGA thng qua u ni DB15. Cng kt
ni ny c th kt ni trc tip vo hu ht mn hnh my tnh hoc LCD dng loi cp
chun thng thng.
43


Hnh 4.2. u ni VGA trong Spartan-3E Starter Kit Board
Bo Spartan-3E FPGA trc tip iu khin nm tn hiu VGA nh cc in tr. Dy
cable tn hiu c gi tr tr khng l 75 m bo rng cc tn hiu mu c ln
trong phm vi 0V 0,7V.
Tn hiu VGA_HSYNC v VGA_VSYNC s dng chun I/O LVTTL hoc
LVCMOS33 iu khin cc trng thi khc nhau.Cc tn hiu VGA_RED,
VGA_GREEN v VGA_BLUE khi thay i s to ra 8 mu c bn c trnh by trong
bng sau.
VGA_Red VGA_Green VGA_Blue Mu tng ng
0 0 0 en
0 0 1 Xanh dng
0 1 0 Xanh l
0 1 1 Lc lam
1 0 0
1 0 1 Hng
44

1 1 0 Vng
1 1 1 Trng

4.1.3 nh thi tn hiu cho ch hin th VGA 60Hz, 640x480
Vic hin th ln mn hnh c tin hnh da trn cc ng qut ngang t phi qua
tri v qut dc t trn xung di. hin th ln trn mn hnh di dng cc im nh
(cc pixel). S pixel qut ht mt ng ngang v s pixel qut ht mt ng dc
gi l phn gii. d dng hnh dung cch to nh trn mn hnh chng ta xt hnh
v.

Hnh 4.3. V d v CRT Display Timing
45

Hnh v trn l mt v d minh ho cho vic hin th trn mn hnh CRT vi
phn gii l 640*480. Nh vy, to ra in p rng ca thc hin vic qut cn phi
cung cp mt tn hiu sao cho ng vi in p qut ngc khi s l tn hiu xo cho
mt dng qut. Di y l biu thi gian tn hiu VGA :

Hnh 4.4. Biu thi gian tn hiu VGA
Trong :T
pw
: thi gian ng b (synctime);
T
fp
: thi gian sn trc (frontporch);
T
bp
: thi gian sn sau (backporch);
T
disp
:thi gian hin th (display);
T
s
:tng thi gian qut
C hai phn gii ta thng s dng hn c l 640*480 v 800*600. Di y l
bng tham s T
PW
, T
S
,T
disp
, T
fp
, T
bp
ng vi phn gii 640*480 l phn gii m ta
hay s dng trong qu trnh thit k. Thc ra cc gi tr ny chng ta c th thay i
trong mt vi gi tr vn m bo vic ng b qut v to nh trn mn hnh theo ng
thit k vic hin th.

46

Hnh 4.5. Bng tham s cho ch 640 * 480
Nh vy to ra tn hiu qut nh trn n gin ta to ra mt b m vi s m ti
a ln n 800 s reset v khng. B m thc hin m n cc gi tr tng ng cho
trn bng trn th xut tn hiu ln mc 1. Mt iu lu l tn s ng vi mi Pixel
l 25 Mhz. Chnh v vy ta phi to ra xung clock 25Mhz to s kin m i vi
mi gi tr Pixel.
4.1.4 S khi

Hnh 4.6. S khi c bn iu khin VGA
47

4.1.5 Khi ng b VGA

Hnh 4.7. khi ng b VGA
Bao gm:
Chia xung: y l khi c tc dng iu chnh tn s mch ngoi ph hp vi tn s
hot ng ca VGA tng ng ang s dng.L khi c sn trong FPGA c kh nng
iu chnh v pha tn s, v dng ca xung nhp ng b.
Qut ngang dc: l khi ht nhn ca VGA, nhim v to ra cc xung HS v VS bng
hai b m ghp ni tip, b m c s l b m xung qut ngang vi u vo l
xung nhp DCM_CLK=40Mhz ly t DCM, b m th hai to xung qut dc, tng
ln 1 khi qut ht mt hng.
4.1.6 Khi m ha a ch cho RAM (encoder_add_ram)

48

Hnh 4.8. Khi m ha a ch cho RAM
Gi tr m ha ny s c a ti u vo a ch ca RAM cho bit rng, b m
ang tr n no trn ca mn hnh.
Ng ra add_ram s c 40 a ch hin th 40 k t 16x16bit.

4.1.7 Khi Ram (rom_add)

Hnh 4.9. Khi RAM
Rom_add c u vo v u ra nh sau:
Add_RAM (in) : bus a ch 11 bit c ni vi u ra ca b m ha a
ch RAM (encode_add_RAM) cho bit, b m ang tr ti no trn
mn hnh.
Btn(in): iu khin chn nhm thanh ghi trong character_Rom.
Character_address: u ra ca RAM c rng 8 bit. Tn hiu t y
s c ni vi u vo seg_sel ca khi character_ROM quyt nh xem ti m b
m ang tr ti s hin th k t g.
49

4.1.8 Khi Character_rom
Khi ny cha cc k t c nh dng sn xut ra theo pixel v c chn bi khi
ROM_add, khi c tn hiu seg_sel v Sh_sel vo th khi ny s x l tn hiu v xut
ra k t tng ng vi a ch m khi ROM_add a n khi ny.
Ng ra Char_out gm 16 bit s xut k t tng ng n b MUX
4.1.9 Khi MUX

Hnh 4.10. Khi MUX
Khi c chc nng quyt nh mu ca im nh.u vo ly t m qut lu trong ROM.

Hinh 4.11. u ra VGA


50

4.1.10 Khi VGA_gen
Khi to im nh c u vo l cc gi tr ta
hcount v vcount ca im nh v u ra l mu
sc tng ng ca im nh .


51

Kt lun

Vi FPGA, chng ta khng nhng c th rt ngn thi gian thc hin ASIC m
cn gim chi ph nghin cu ti a do qu trnh kim tra thit k khng nhng
c kim tra bng cc phn mm m phng m gi y cn c th chy trn cc
Chip thc trong mi trng c th ni l gn vi mi trng ASIC thc nht. Kh
nng ti cu hnh cho php bn sa i sa li thit k cho n khi t yu cu m
khng tn mt xu no ngoi tin in m bn phi tr. Do , cng ngh FPGA s
l cng ngh ph hp nht i vi nn cng nghip ang pht trin nh Vit Nam.