LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
ENTITY SIM2 IS
END SIM2;
ARCHITECTURE behavior OF SIM2 IS
COMPONENT Datapath_1
PORT(
out_s1 : OUT std_logic_vector(3 downto 0);
out_s2 : OUT std_logic_vector(3 downto 0);
clk : IN std_logic;
R : IN std_logic;
LOAD : IN std_logic_vector(3 downto 0)
);
END COMPONENT;
signal clk : std_logic := '0';
signal R : std_logic := '0';
signal LOAD : std_logic_vector(3 downto 0) := (others => '0');
signal out_s1 : std_logic_vector(3 downto 0);
signal out_s2 : std_logic_vector(3 downto 0);
BEGIN
Instantiate the Unit Under Test (UUT)
uut: Datapath_1 PORT MAP (
out_s1 => out_s1,
out_s2 => out_s2,
clk => clk,
R => R,
LOAD => LOAD
);
clk <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns,
'1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns,
'0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns,
'1' after 150 ns, '0' after 160 ns, '1' after 170 ns, '0' after 180 ns, '1' after 190 ns,
'0' after 200 ns;
LOAD <= "1010", "0101" after 20 ns, "0001" after 40 ns, "0011" after 60 ns, "0110" after 80 ns;
R <= '0', '1' after 80 ns;
END;