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Advanced UVM
Architecting a UVM Testbench

Tom Fitzpatrick
Verification Evangelist

What does it do?
What are the use cases?
Which test cases are required?
What type of stimulus scenarios are required?
What represents correct behavior?
What kind of functional coverage do I need?
For the Design:
UVM Testbench - Architectural Design

DUT



SPI
I/F

APB
IRQ
How does the interface work?
What information is transferred?
Transaction variants?
Uni/bidirectional? Pipelined?
For Each Interface:
UVC Structural Building Block

DUT
One per
interface
UVC(agent)
Sequencer
Driver
Monitor
Configuration
Object
Stimulus Converts seq_item
to pin wiggles
Sends stimulus
to Driver
Detects transactions
on the interface
Analysis port: Send
transactions for checking
- Contains virtual
interface handle
- Pass information
on how agent
should behave
seq_item
UVCs are Protocol-Specific

DUT
UVC(agent)
Sequencer
Driver
Monitor
Configuration
Object
UVC(agent)
Sequencer
Driver
Monitor
Configuration
Object
cl ass dut _agent ext ends uvm_component ;
`uvm_component _ut i l s( dut _agent )
dut _agent _cf g m_cf g;
uvm_anal ysi s_por t #( dut _t xn) ap;
dut _moni t or m_moni t or ;
dut _dr i ver m_dr i ver ;
uvm_sequencer #( dut _t xn) m_seqr ;

f unct i on voi d build_phase(uvm_phase phase);
super . bui l d_phase( phase) ;
i f ( ! uvm_conf i g_db #( dut _agent _cf g) : : get ( t hi s, , conf i g, m_cf g) )
`uvm_f at al ( Conf i g f at al , Can t get conf i g) ;
i f ( m_cf g. act i ve == UVM_ACTI VE) begi n
m_seqr = uvm_sequencer #( dut _t xn) : : t ype_i d: : cr eat e( seqr , t hi s) ;
m_dr i ver = dut _dr i ver : : t ype_i d: : cr eat e( dr i ver , t hi s) ;
end

endf unct i on

f unct i on voi d connect_phase(uvm_phase phase);
m_moni t or . dut _i f = m_cf g. bus_i f ;
ap = m_moni t or . ap;
i f ( m_cf g. act i ve == UVM_ACTI VE) begi n
m_dr i ver . seq_i t em_por t . connect ( m_seqr . seq_i t em_expor t ) ;
m_dr i ver . dut _i f = m_cf g. bus_i f ;
end

endf unct i on
endcl ass
UVCs are Protocol-Specific: The Agent

DUT
UVC(agent)
Sequencer
Driver
Monitor
Configuration
Object
The Environment

DUT
UVC(agent)
Sequencer
Driver
Monitor
Configuration
Object
cl ass my_env ext ends uvm_env;
`uvm_component _ut i l s( my_env)

agent 1 m_agent 1;
agent 2 m_agent 2;
my_scor eboar d m_scor eboar d;
my_env_conf i g m_cf g;

f unct i on new( st r i ng name = my_env, uvm_component par ent = nul l ) ;
super . new( name, par ent ) ;
endf unct i on

f unct i on voi d bui l d_phase( uvm_phase phase) ;
i f ( ! uvm_conf i g_db #( my_env_conf i g ) : : get ( t hi s , " " ,
my_env_conf i g" , m_cf g ) begi n
`uvm_er r or ( " bui l d_phase" , " unabl e t o get my_env_conf i g" )
end
i f ( m_cf g. has_agent 1) begi n
uvm_conf i g_db #( agent 1_conf i g) : : set ( t hi s , " m_agent 1*" ,
" agent 1_conf i g" , m_cf g. m_agent 1_cf g ) ;
m_agent 1 = agent 1: : t ype_i d: : cr eat e( " m_agent 1" , t hi s) ;
end
i f ( m_cf g. has_agent 2) begi n
uvm_conf i g_db #( agent 2_conf i g) : : set ( t hi s , " m_agent 2*" ,
" agent 2_conf i g" , m_cf g. m_agent 2_cf g ) ;
m_agent 2 = agent 2: : t ype_i d: : cr eat e( " m_agent 2" , t hi s) ;
end
i f ( m_cf g. has_my_scor eboar d) begi n
m_scor eboar d = my_scor eboar d: : t ype_i d: : cr eat e( " m_scor eboar d" , t hi s) ;
end
endf unct i on: bui l d_phase
The Environment

DUT
cl ass my_env ext ends uvm_env;
`uvm_component _ut i l s( my_env)

agent 1 m_agent 1;
agent 2 m_agent 2;
my_scor eboar d m_scor eboar d;
my_env_conf i g m_cf g;

f unct i on new( st r i ng name = my_env, uvm_component par ent = nul l ) ;
super . new( name, par ent ) ;
endf unct i on

f unct i on voi d connect _phase( uvm_phase phase ) ;
i f ( m_cf g. has_spi _scor eboar d) begi n
m_agent 1. ap. connect ( m_scor eboar d. apb. anal ysi s_expor t ) ;
m_agent 2. ap. connect ( m_scor eboar d. spi . anal ysi s_expor t ) ;
end
endf unct i on: connect _phase
endcl ass
The Environment

DUT
cl ass my_t est _base ext ends uvm_t est ;
`uvm_component _ut i l s( my_t est _base)

my_env m_env;
my_env_conf i g m_cf g;
my_agent 1_conf i g m_a1_cf g;
my_agent 2_conf i g m_a2_cf g;

f unct i on new( st r i ng name = my_t est _base, uvm_component par ent = nul l ) ;
super . new( name, par ent ) ;
endf unct i on

f unct i on voi d bui l d_phase( uvm_phase phase ) ;
m_cf g = my_env_conf i g: : t ype_i d: : cr eat e( m_env_cf g) ;
/ / set up conf i gur at i on f or env and agent s
uvm_conf i g_db#( my_env_conf i g) : : set ( t hi s, " *" , my_env_conf i g" ,
m_cf g) ;
m_env = my_env: : t ype_i d: : cr eat e( " m_env" , t hi s) ;
endf unct i on

endcl ass
The Base Test

DUT
cl ass my_t est ext ends uvm_t est _base;
`uvm_component _ut i l s( my_t est )

my_vi r t _seq m_vseq;

f unct i on new( st r i ng name = my_t est , uvm_component par ent = nul l ) ;
super . new( name, par ent ) ;
endf unct i on

f unct i on voi d bui l d_phase( uvm_phase phase ) ;
super . bui l d_phase( phase) ;
endf unct i on

t ask r un_phase( uvm_phase phase) ;
m_vseq = my_vi r t _seq: : t ype_i d: : cr eat e( my vi r t ual sequence) ;
phase. r ai se_obj ect i on( t hi s, St ar t i ng vi r t ual sequence) ;
m_vseq. st ar t ( ) ;
phase. dr op_obj ect i on( t hi s, Fi ni shed vi r t ual sequence) ;
endt ask

endcl ass
The Actual Test

DUT
A Word About Phasing
UVM adds 12 new phases in parallel
with run_phase
Consensus is to use the new phases
to control stimulus




Drivers and monitors should just
use run_phase
Dont use phase domains or
jumping
uvm
shutdown
post_shutdown
main
pre_main
post_config
config
pre_config
post_reset
reset
pre_reset
pre_shutdown
post_main
common
build
end_of_elab
connect
start_of_sim
run
extract
check
report
final
cl ass my_phase_t est ext ends uvm_t est _base;
`uvm_component _ut i l s( my_phase_t est )

t ask XXX_phase( uvm_phase phase) ;
phase. r ai se_obj ect i on( t hi s, St ar t i ng Phase) ;
/ / St ar t sequence( s)
/ / begi n- end / f or k- j oi n
phase. dr op_obj ect i on( t hi s, Fi ni shed Phase) ;
endt ask

endcl ass
Architecture Summary
Agents are protocol-specific
Environments define the testbench topology
Which agents and how many
Other components
Base Test instantiates env and handles
default configuration
Extend the base test to define your test
Tweek configuration and/or factory settings
Start (virtual) sequence(s)
Test handles phase objections
Keep to basic phasing