Crownhill PIC BASIC Plus compiler - for the 14-bit range of PIC micros www.letbasic.com PICBASIC PLUS Compiler Copyright Crownhill 2001 93
5.50. PRINT
Syntax : PRINT Item { , Item... }
Overview : Send Text to an LCD module using the Hitachi 44780 controller or a graphic LCD based on the Samsung S6B0108 chipset.
Operators : Item may be a constant, variable, expression, modifier, or string list. There are no operators as such, instead there are modifiers. For ex- ample, if an at sign @ precedes an Item, the ASCII representation for each digit is sent to the LCD.
The modifiers are listed below: -
Modifier Operation
AT ypos (1 to n),xpos(1 to n) Position the cursor on the LCD BIN{1..16} Send binary digits CLS Clear the LCD (also creates a 30ms delay) DEC{1..5} Send decimal digits HEX{1..4} Send hexadecimal digits REP c\n Send character c repeated n times
The numbers after the BIN, DEC, and HEX modifiers are optional. If they are omitted, then the default is all the digits that make up the value will be displayed.
The Xpos and Ypos values in the AT modifier both start at 1. For ex- ample, to place the text HELLO WORLD on line 1, position 1, the code would be: -
PRINT AT 1 , 1 , HELLO WORLD
Example : DIM Var as BYTE DIM Wrd as WORD
PRINT Hello World Display the text Hello World PRINT Var= , DEC Var Display the decimal value of VAR PRINT Var= , HEX Var Display the hexadecimal value of VAR PRINT Var= , BIN Var Display the binary value of VAR PRINT Var= , @Var Display the decimal value of VAR
Declares : There are six DECLARES for use with an alphanumeric LCD and PRINT: -
DECLARE LCD_TYPE 1 or 0 , GRAPHIC or ALPHA Inform the compiler as to the type of LCD that the PRINT command will output to. If GRAPHIC or 1 is chosen then any output by the PRINT command will be directed to a graphic LCD based on the PICBASIC PLUS Compiler Copyright Crownhill 2001 94
Samsung S6B0108 chipset. A value of 0 or ALPHA, or if the DE- CLARE is not issued will target the standard alphanumeric LCD type
Targeting the graphic LCD will also enable commands such as PLOT, UNPLOT, LCDGET, and LCDPUT.
DECLARE LCD_DTPIN PORT . PIN Assigns the Port and Pins that the LCDs DT (data) lines will attach to.
The LCD may be connected to the PICmicro using either a 4-bit bus or an 8-bit bus. If an 8-bit bus is used, all 8 bits must be on one port. If a 4-bit bus is used, it must be connected to either the bottom 4 or top 4 bits of one port. For example: -
DECLARE LCD_DTPIN PORTB.4 Used for 4-line interface.
DECLARE LCD_DTPIN PORTB.0 Used for 8-line interface.
In the examples above, PortB is only a personal preference. The LCDs DT lines may be attached to any valid port on the PIC. If the DECLARE is not used in the program, then the default Port and Pin is PortB.4, which assumes a 4-line interface. . DECLARE LCD_ENPIN PORT . PIN Assigns the Port and Pin that the LCDs EN line will attach to.
If the DECLARE is not used in the program, then the default Port and Pin is PortB.2.
DECLARE LCD_RSPIN PORT . PIN Assigns the Port and Pins that the LCDs RS line will attach to.
If the DECLARE is not used in the program, then the default Port and Pin is PortB.3.
DECLARE LCD_INTERFACE 4 or 8 Inform the compiler as to whether a 4-line or 8-line interface is re- quired by the LCD.
If the DECLARE is not used in the program, then the default interface is a 4-line type.
DECLARE LCD_LINES 1 , 2 , or 4 Inform the compiler as to how many lines the LCD has.
LCDs come in a range of sizes, the most popular being the 2 line by 16 character types. However, there are 4-line types as well. Simply place the number of lines that the particular LCD has, into the declare. PICBASIC PLUS Compiler Copyright Crownhill 2001 95
If the DECLARE is not used in the program, then the default number of lines is 2.
Notes : If no modifier precedes an item in a PRINT command, then the char- acters value is sent to the LCD. This is useful for sending control codes to the LCD. For example: -
PRINT $FE , 128
Will move the cursor to line 1, position 1 (HOME).
Below is a list of useful control commands: -
Control Command Operation
$FE, 1 Clear display $FE, 2 Return home (beginning of first line) $FE, $0C Cursor off $FE, $0E Underline cursor on $FE, $0F Blinking cursor on $FE, $10 Move cursor left one position $FE, $14 Move cursor right one position $FE, $C0 Move cursor to beginning of second line $FE, $94 Move cursor to beginning of third line $FE, $D4 Move cursor to beginning of fourth line
Note that if the command for clearing the LCD is used, then a small delay should follow it: -
PRINT $FE , 1 : DELAYMS 30
The above diagram shows the default connections for an alphanu- meric LCD module. In this instance, connected to the 16F84 PICmicro. RB7 VDD RB6 RB5 RB4 RB3 RB2 RB1 RB0 13 RA4 RA3 RA2 RA1 RA0 MCLR OSC1 OSC2 VSS 14 PIC16F84 C4 22pF C1 10uF C2 0.1uF R1 4.7k 5 Volts C3 22pF 4MHz Crystal 12 11 10 9 8 7 6 3 2 1 18 17 5 4 16 15 0V I NTELLI GENT LCD MODULE D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0 E N R / W R S V o V d d V s s Contrast 47K linear +5V PICBASIC PLUS Compiler Copyright Crownhill 2001 96
Using a Graphic LCD
Once a graphic LCD has been chosen using the DECLARE LCD_TYPE directive, all PRINT outputs will be directed to that LCD.
The standard modifiers may also be used with the graphics LCD: -
AT ypos (0 to 7),xpos (0 to 20) Position the cursor on the LCD BIN{1..16} Send binary digits CLS Clear the LCD DEC{1..5} Send decimal digits HEX{1..4} Send hexadecimal digits REP c\n Send character c repeated n times
Most of the above modifiers still work in the expected manner, how- ever, the AT modifier now starts at Ypos 0 and Xpos 0, where values 0,0 will be the top left corner of the LCD.
There are also four new modifiers. These are: -
FONT 0 to n Choose the n th font, if available INVERSE 0-1 Invert the characters sent to the LCD OR 0-1 OR the new character with the original XOR 0-1 XOR the new character with the original
Once one of the four new modifiers has been enabled, all future PRINT commands will use that particular feature until the modifier is disabled. For example: -
Enable inverted characters from this point PRINT AT 0 , 0 , INVERSE 1 , HELLO WORLD PRINT AT 1 , 0 , STILL INVERTED Now use normal characters PRINT AT 2 , 0 , INVERSE 0 , NORMAL CHARACTERS
If no modifiers are present, then the characters ASCII representation will be displayed: -
Print characters A and B PRINT AT 0 , 0 , 65 , 66
Declares : There are six declares associated with a graphic LCD.
DECLARE LCD_DTPORT PORT Assign the port that will output the 8-bit data to the graphic LCD.
If the DECLARE is not used, then the default port is PORTD. PICBASIC PLUS Compiler Copyright Crownhill 2001 97
DECLARE LCD_RWPIN PORT . PIN Assigns the Port and Pin that the graphic LCDs RW line will attach to.
If the DECLARE is not used in the program, then the default Port and Pin is PortE.0.
DECLARE LCD_CS1PIN PORT . PIN Assigns the Port and Pin that the graphic LCDs CS1 line will attach to.
If the DECLARE is not used in the program, then the default Port and Pin is PortC.0.
DECLARE LCD_CS2PIN PORT . PIN Assigns the Port and Pin that the graphic LCDs CS2 line will attach to.
If the DECLARE is not used in the program, then the default Port and Pin is PortC.2.
Note : Along with the new declares, two of the existing LCD declares must also be used. Namely, RS_PIN and EN_PIN.
DECLARE INTERNAL_FONT ON - OFF, 1 or 0 The graphic LCDs that are compatible with PICBASIC PLUS are non- intelligent types, therefore, a separate character set is required. This may be in one of two places, either externally, in an I 2 C eeprom, or in- ternally in a CDATA table.
If the DECLARE is omitted from the program, then an external font is the default setting.
If an external font is chosen, the I 2 C eeprom must be connected to the specified SDA and SCL pins (as dictated by DECLARE SDA and DE- CLARE SCL).
If an internal font is chosen, it must be on a PIC device that has self modifying code features, such as the 16F87X range.
The CDATA table that contains the font must have a label, named FONT: preceding it. For example: -
FONT:- { data for characters 0 to 64 } CDATA $7E , $11 , $11 , $11 , $7E , $0 Chr 65 A CDATA $7F , $49 , $49 , $49 , $36 , $0 Chr 66 B { rest of font table } PICBASIC PLUS Compiler Copyright Crownhill 2001 98
Notice the dash after the fonts label, this disables any bank switching code that may otherwise disturb the location in memory of the CDATA table.
The font table may be anywhere in memory, however, it is best placed after the main program code.
The font is built up of an 8x6 cell, with only 5 of the 6 rows, and 7 of the 8 columns being used for alphanumeric characters. See the dia- gram below.
However, if a graphic character is chosen (chr 0 to 31), the whole of the 8x6 cell is used. In this way, large fonts and graphics may be eas- ily constructed.
A list of the graphic characters is shown at the end of the PRINT de- scription.
The character set itself is 128 characters long (0 -127). Which means that all the ASCII characters are present, including $, %, &, # etc.
There are two programs on the compilers CDROM, that are for use with internal and external fonts. INT_FONT.BAS, contains a CDATA table that may be cut and pasted into your own program if an internal font is chosen. EXT_FONT.BAS, writes the character set to a 24C32 I 2 C eeprom for use with an external font. Both programs are fully com- mented. $ 7 E $ 0 0 $ 1 1 $ 1 1 $ 1 1 $ 7 E PICBASIC PLUS Compiler Copyright Crownhill 2001 99
DECLARE FONT_ADDR 0 to 7 Set the slave address for the I 2 C eeprom that contains the font.
When an external source for the font is used, it may be on any one of 8 eeproms attached to the I 2 C bus. So as not to interfere with any other eeproms attached, the slave address of the eeprom carrying the font code may be chosen.
If the DECLARE is omitted from the program, then address 0 is the default slave address of the font eeprom.
Important : Because of the complexity involved with interfacing to the graphic LCD, five of the eight stack levels available are used when the PRINT command is issued with an external font. Therefore, be aware that if PRINT is used within a subroutine, you must limit the amount of sub- routine nesting that may take place.
If an internal font is implemented, then only four stack levels are used.
If the default setting of PORTE is used for the LCDs CS1, CS2, and RW pin connections, then these pins should be set to digital by issu- ing the following line of code near the beginning of the program: -
ADCON1 = 7 Set PORTA and PORTE to all digital
You will need to refer to the PICs datasheet for ADCON1 settings if PORTA is to be used for analogue inputs.
The diagram shows the connections required for an external font. The eeprom has a slave address of 0. If an internal font is used, then the eeprom may be omitted. RB7 VDD RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA4 RA3 RA2 RA1 RA0 MCLR OSC1 OSC2 VSS 32 PIC16F877 C4 15pF C2 0.1uF C1 10uF C3 15pF 5 Volts 26 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 VSS RA5 20MHz Crystal 0V R1 4.7k 25 24 23 18 17 16 15 40 39 38 37 36 35 34 33 7 6 5 4 3 2 31 12 14 13 1 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 VDD 11 10 9 8 30 29 28 27 22 21 20 19 5 Volts Contrast 47k VCC WP SCL A1 A2 VSS 24C32 7 8 A0 SDA 1 2 3 4 6 5 2x 4.7k 5 Volts 64x128 DOT MATRI X GRAPHI C LCD D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0 E N R / W R S V o V c c G n d C S 1 C S 2 R S T - V o u t 1 20 L E D A L E D K PICBASIC PLUS Compiler Copyright Crownhill 2001 100
The below diagram lists the graphic characters available. For exam- ple, to display a single horizontal bar, the BASIC code would be: -
Any of the character set may be altered to suit your personal needs, however, characters 26 to 31 are left blank to be used for user de- fined characters.
Symbol Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Symbol Code 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Date : 2000/10/27 AMPIRE CO., LTD. 3 1 FEATURES (1) Display format : 128 64 dot-matrix ; 1/ 64 duty. (2) Construction : STN / FSTN LCD, Bezel, Zebra, Heat Seal and PCB. (3) Optional Edge LED or EL backlight. (4) Controller : KS0108B. (5) 5V single power input. Built-in DC/DC converter for LCD driving. (6) Normal / Extended temperature type. 2 NUMBERING SYSTEM AG-12864C _ _ _ _ - _ 1 2 3 4 5 No Code Value Description Remark G STN gray type LCD Y STN yellow green type LCD S STN negative type LCD 1 F FSTN type LCD LCD Type A Reflective type / 6:00 view B Reflective type / 12:00 view I Transflective type / 6:00 view J Transflective type / 12:00 view T Negative type / 6:00 view 2 U Negative type / 12:00 view Polarizer / Viewing Angel None Without backlight Q 5V Edge type LED 3 E EL Backlight type None Without backlight Y Yellow-green (LED) B Blue (EL) 4 W White (EL, LED) Backlight color None Normal temperature type 5 H Extended temperature type LCM temperature type Date : 2000/10/27 WWW.LETBASIC.COM 4 2 MECHANICAL DATA Parameter Stand Value Unit Dot size 0.40(W) 0.56(H) mm Dot pitch 0.44(W) 0.60(H) mm Viewing area 62.0(W) 44.0(H) mm Module size 78.0(W) 70.0(H) 10.5 max (T) mm Module size (w/ LED back-light) 78.0(W) 70.0(H) 13.0 max (T) mm 3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit Logic Circuit Supply Voltage VDD-VSS 0 7.0 V LCD Driving Voltage VDD-VO 0 20 V Input Voltage VI VSS VDD V Operating Temp. TOP 0 50 C Normal temp. type Storage Temp. TSTG -20 70 C Operating Temp. TOP -20 70 C Extended temp. type Storage Temp. TSTG -30 80 C Date : 2000/10/27 WWW.LETBASIC.COM 5 4 ELECTRO-OPTICAL CHARACTERISTICS Parameter Symbol Condition Min Typ Max Unit Note ----- Electronic Characteristics ----- Logic Circuit Supply Voltage VDD-VSS -- 4.5 5.0 5.5 V -20 C 8.4 9.2 10.0 0C 8.4 9.2 10.0 25C 8.4 9.2 10.0 50C 8.4 9.2 10.0 LCD Driving Voltage VDD-VO 70 C 8.4 9.2 10.0 V 0 ~50 C for Normal Temp. type -20 ~70 C for Extended Temp. type VIH -- 0.7 VDD -- VDD V Input Voltage VIL -- VSS -- 0.3 VDD V Logic Supply Current IDD VDD =5V -- 3 4 mA ----- Optical Characteristics ----- STN type -- 4.2 -- Contrast CR FSTN type 7 Note 1 Rise Time tr 25C -- 140 -- ms Fall Time tf 25C -- 240 -- ms Note 2 f -- 40 -- b -- 35 -- l -- 35 -- Viewing Angle Range r 25C & CR2 -- 35 -- Deg. Note 3 Frame Frequency fF 25C -- 70 -- Hz ----- Yellow-green LED Back-light Characteristics ----- Forward Voltage VF -- -- 4.05 4.3 V Supply Voltage between A&K Forward Current IF VF=4.05V -- 100 -- mA Bare LED Luminous intensity VF=4.05V -- 20 -- cd/m 2 LCM Luminous intensity VF=4.05V -- 7 -- cd/m 2 A K A K Active Area Date : 2000/10/27 WWW.LETBASIC.COM 6 ----- White Edge LED Back-light Characteristics ----- Forward Voltage VF -- 7.2 7.6 8.0 V Supply Voltage between A&K Forward Current IF VF=7.6V -- 100 -- mA Bare LED Luminous intensity VF=7.6V -- 30 -- cd/m 2 LCM Luminous intensity VF=7.6V -- 10 -- cd/m 2 A K A K Parameter Min Typ Max Unit Note ----- EL Back-light Characteristics ----- Driving Voltage -- 110 -- Vrms Frequency -- 400 -- Hz Bare EL Luminous intensity -- 50 -- cd/m 2 LCM Luminous intensity -- 15 -- cd/m 2 (NOTE 1) Contrast ratio : CR =(Brightness in OFF state) / (Brightness in ON state) ( NOTE 2 ) Response time : Date : 2000/10/27 WWW.LETBASIC.COM 7 (NOTE 3) Viewing angle Date : 2000/10/27 WWW.LETBASIC.COM 8 5 BLOCK DIAGRAM & POWER SUPPLY 64 COM Driver KS0107 LCD Panel 128 x 64 Dots SEG Driver KS0108B 64 RS, R/W, E, /RES, DB0 - DB7 SEG Driver KS0108B 64 LCD Bias Circuit DC/DC Converter CS1 CS2 V0,V2,V3, V5,VEE V0,V1,V4, V5,VEE M,FRM, CLK1,CLK2, CL2 LCM VEE (-10V) VO VDD VSS VDD EL Back-light EL1 EL2 AC110V(400Hz) LCM LED Back-light LED_A LED_K 5V 4.05V LCM Using LED Back-light Using EL Back-light Date : 2000/10/27 WWW.LETBASIC.COM 9 6 PIN CONNECTIONS No. Symbol Function 1 /CSA Chip Selection For ICA 2 /CSB Chip Selection For ICB 3 VSS Ground (0V) 4 VDD Supply Voltage for Logic (+5V) 5 VO Contrast adjustment 6 D/I Data or Instruction 7 R/W Read or Write 8 E Enable signal 9-16 DB0-DB7 Data Bus Line 17 /RST Reset 18 VEE Negative Power Supply Output ( -5V ) 19 LEDA LED Back-light Power Supply +(5V) 20 LEDK LED Back-light Power Supply - (5V) Date : 2000/10/27 WWW.LETBASIC.COM 10 7 TIMING CHARACTERISTICS Item Symbol Min Typ Max Unit Enable Cycle Time tCYCLE 1000 - - ns High Level PWEH 450 - - ns Enable Pulse Width Low Level PWEL 450 - - ns Enable Rise & Fall Time tER,tEF - - 25 ns Address Set-Up Time tAs 140 - - ns Address Hold Time tAH 10 - - ns Data Set-Up Time tDSW 200 - - ns Data Delay Time tDDR -- - 320 ns Data Hold Time(Write) tDHW 10 - - ns Data Hold Time(Read) tDHW 20 - - ns Write Timing Chart tCYCLE PWEL PWEH tAS tAS tAH tDHW tDSW tER tEF E R/W CS,D/I DB0 DB7 Date : 2000/10/27 WWW.LETBASIC.COM 11 Read Timing Chart tCYCLE PWEL PWEH tAS tAS tAH TDHR tER tEF E R/W CS,D/I DB0 DB7 TDDR Date : 2000/10/27 WWW.LETBASIC.COM 12 7.1 Power ON/OFF Sequence VDD VO Signal POWER ON SEQUENCE 0~50 ms VSS VSS VSS T!20 ms T!0 ms POWER OFF SEQUENCE 0 ~50 ms VDD VO Signal VSS VSS VSS T!20 ms Date : 2000/10/27 WWW.LETBASIC.COM 13 8 INSTRUNTION SET Date : 2000/10/27 WWW.LETBASIC.COM 14 9 QUALITY AND RELIABILITY 9.1 TEST CONDITIONS Tests should be conducted under the following conditions : Ambient temperature : 25 5C Humidity : 60 25% RH. 9.2 SAMPLING PLAN Sampling method shall be in accordance with MIL-STD-105E , level II, normal single sampling plan . 9.3 ACCEPTABLE QUALITY LEVEL A major defect is defined as one that could cause failure to or materially reduce the usability of the unit for its intended purpose. A minor defect is one that does not materially reduce the usability of the unit for its intended purpose or is an infringement from established standards and has no significant bearing on its effective use or operation. 9.4 APPEARANCE An appearance test should be conducted by human sight at approximately 30 cm distance from the LCD module under flourescent light. The inspection area of LCD panel shall be within the range of following limits. Date : 2000/10/27 WWW.LETBASIC.COM 15 9.5 INSPECTION QUALITY CRITERIA Item Description of defects Class of Defects Acceptable level (%) Function Short circuit or Pattern cut Major 0.65 Dimension Deviation from drawings Major 1.5 Ave . dia . D area A area B D0.2 Disregard 0.2<D0.3 3 4 0.3<D0.4 2 3 Black spots 0.4<D 0 1 Minor 2.5 Width W, Length L A B W0.03 disregard 0.03<W0.05 3 4 0.05<W0.07 , L3.0 1 1 Black lines See line criteria Minor 2.5 Bubbles in polarizer Average diameter D 0.2 <D <0.5 mm for N =4 , D >0.5 for N =1 Minor 2.5 Color uniformity Rainbow color or newton ring. Minor 2.5 Glass Scratches Obvious visible damage. Minor 2.5 Contrast ratio See note 1 Minor 2.5 Response time See note 2 Minor 2.5 Viewing angle See note 3 Minor 2.5 ZONE A active area ZONE B viewing area Date : 2000/10/27 WWW.LETBASIC.COM 16 9.6 RELIABILITY Test Conditions Test Item Normal Temp. type Extended Temp. type Note High Temperature Operation 503C , t=96 hrs 703C , t=96 hrs Low Temperature Operation 03C , t=96 hrs -203C , t=96 hrs High Temperature Storage 703C , t=96 hrs 803C , t=96 hrs 1,2 Low Temperature Storage -203C , t=96 hrs -303C , t=96 hrs 1,2 Temperature Cycle -20C ~ 25C ~ 70C 30 m in. 5 min. 30 min. ( 1 cycle ) Total 5 cycle -30C ~ 25C ~ 80C 30 min. 5 min. 30 min. ( 1 cycle ) Total 5 cycle 1,2 Humidity Test 40 C, Humidity 90%, 96 hrs 1,2 Vibration Test (Packing) Sweep frequency : 10 ~55 ~10 Hz/1min Amplitude : 0.75mm Test direction : X.Y.Z/3 axis Duration : 30min/each axis 2 Note 1 : Condensation of water is not permitted on the module. Note 2 : The module should be inspected after 1 hour storage in normal conditions (15-35C , 45-65%RH). Definitions of life end point : ! Current drain should be smaller than the specific value. ! Function of the module should be maintained. ! Appearance and display quality should not have degraded noticeably. ! Contrast ratio should be greater than 50% of the initial value. Date : 2000/10/27 WWW.LETBASIC.COM 17 10 HANDLING PRECAUTIONS (1) A LCD module is a fragile item and should not be subjected to strong mechanical shocks. (2) Avoid applying pressure to the module surface. This will distort the glass and cause a change in color. (3) Under no circumstances should the position of the bezel tabs or their shape be modified. (4) Do not modify the display PCB in either shape or positioning of components. (5) Do not modify or move location of the zebra or heat seal connectors. (6) The device should only be soldered to during interfacing. Modification to other areas of the board should not be carried out. (7) In the event of LCD breakage and resultant leakage of fluid do not inhale, ingest or make contact with the skin. If contact is made rinse immediately. (8) When cleaning the module use a soft damp cloth with a mild solvent, such as Isopropyl or Ethyl alcohol. The use of water, ketone or aromatic is not permitted. (9) Prior to initial power up input signals should not be applied. (10) Protect the module against static electricity and observe appropriate anti-static precautions. Date : 2000/10/27 WWW.LETBASIC.COM 18 11 OUTLINE DIMENSION 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 1 INTRODUCTION The S6B0107 (TQFP type: S6B2107) is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the S6B0108 (64 channel segment driver TQFP type: S6B2108). The S6B0107 is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the S6B0108 (64 channel segment driver). FEATURES Dot matrix LCD common driver with 64 channel output 64-bit shift register at internal LCD driver circuit Internal timing generator circuit for dynamic display Selection of master/ slave mode Applicable LCD duty: 1/ 48, 1/ 64, 1/ 96, 1/ 128 Power supply voltage: + 5V 10% LCD driving voltage: 8V - 17V (V DD -V EE ) Interface Driver COMMON SEGMENT Controller Other S6B0107 S6B0108 MPU
High voltage CMOS process 100QFP / 100TQFP or bare chip available
64 CH SEGMENT DRIVER FOR DOT MATRIX LCD June. 2000. Ver. 0.0 S6B0108 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 2 INTRODUCTION The S6B0108 is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch, 64 bit drivers and decoder logic. It has the internal dis- play RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid crystal driving signals corresponding to stored data. The S6B0108 composed of the liquid crystal display system in combination with the S6B0107 (64 channel common driver). FEATURES Dot matrix LCD segment driver with 64 channel output Input and output signal - Input: 8 bit parallel display data control signal from MPU divided bias voltage (V0R, V0L, V2R, V2L, V3R, V3L, V5R, V5L) - Output: 64 channel for LCD driving. Display data is stored in display data RAM from MPU. Interface RAM - Capacity: 512 bytes (4096 bits) - RAM bit data: RAM bit data = 1: On RAM bit data = 0: Off Applicable LCD duty: 1/32-1/64 LCD driving voltage: 8V-17V (V DD -V EE ) Power supply voltage: + 5V 10% Interface Drivers Common Segment Controller S6B0107 Other S6B0108 MPU High voltage CMOS process. Bare chip available 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 3 BLOCK DIAGRAM Instruction Decoder LCD Driver Data Latch Display Data RAM 512 8 = 4096bits Display On/Off D i s p l a y
S t a r t
L i n e
R e g i s t e r I / O
B u f f e r 8 8 6 3 6 S 6 4 S 6 3 S 2 S 1 V5R V3R V2R V0R M V5L V3L V2L V0L FRM CL ADC RSTB E RS R/W CS3 CS2B CS1B C L K 2 C L K 1 DB<0:7> Input Register Output Register Busy Y-Counter Y-Counter X-Decoder Z - D e c o d e r P a g e
S e l e c t o r 6 64 1 6 64 64 64 8 8 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 4 PAD DIAGRAM 3211 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 V D D MA D C F R M EC L K 1 C L K 2 C L R S R / W R S T B C S 1 B C S 2 B C S 3 N C N C N C D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0 V S S 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 Chip size: 4090 4020 PAD size: 100 100 Unit : m (0, 0) X Y 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 S 4 3 S 4 2 S 4 1 S 4 0 S 3 9 S 3 8 S 3 7 S 3 6 S 3 5 S 3 4 S 3 3 S 3 2 S 3 1 S 3 0 S 2 9 S 2 8 S 2 7 S 2 6 S 2 5 S 2 4 S 2 3 S 2 2 There is mark of S6B0108 on the bottom left in the chip. 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 5 PAD CENTER COORDINATES Coordinate Coordinate Coordinate PAD Number PAD Name X Y Pad Number Pad Name X Y Pad Number Pad Name X Y 1 ADC -1140 1845 35 S38 -687 -1845 69 S4 1882 791 2 M -1275 1845 36 S37 -562 -1845 70 S3 1882 916 3 VDD -1410 1845 37 S36 -437 -1845 71 S2 1882 1041 4 V3R -1882 1809 38 S35 -312 -1845 72 S1 1882 1166 5 V2R -1882 1684 39 S34 -187 -1845 73 VEE1 1882 1310 6 V5R -1882 1559 40 S33 -62 -1845 74 V0L 1882 1435 7 V0R -1882 1434 41 S32 62 -1845 75 V5L 1882 1559 8 VEE2 -1882 1309 42 S31 187 -1845 76 V2L 1882 1684 9 S64 -1882 1165 43 S30 312 -1845 77 V3L 1882 1809 10 S63 -1882 1040 44 S29 437 -1845 78 VSS 1412 1845 11 S62 -1882 915 45 S28 562 -1845 79 DB0 1277 1845 12 S61 -1882 790 46 S27 687 -1845 80 DB1 1142 1845 13 S60 -1882 665 47 S26 812 -1845 81 DB2 1007 1845 14 S59 -1882 540 48 S25 937 -1845 82 DB3 882 1845 15 S58 -1882 415 49 S24 1062 -1845 83 DB4 757 1845 16 S57 -1882 290 50 S23 1187 -1845 84 DB5 632 1845 17 S56 -1882 165 51 S22 1487 -1845 85 DB6 507 1845 18 S55 -1882 40 52 S21 1882 -1379 86 DB7 382 1845 19 S54 -1882 -84 53 S20 1882 -1239 87 NC 20 S53 -1882 -209 54 S19 1882 -1099 88 NC 21 S52 -1882 -334 55 S18 1882 -959 89 NC 22 S51 -1882 -459 56 S17 1882 -834 90 CS3 245 1845 23 S50 -1882 -584 57 S16 1882 -709 91 SC2B 120 1845 24 S49 -1882 -709 58 S15 1882 -584 92 SC1B -5 1845 25 S48 -1882 -834 59 S14 1882 -459 93 RSTB -130 1845 26 S47 -1882 -959 60 S13 1882 -334 94 R/W -255 1845 27 S46 -1882 -1099 61 S12 1882 -209 95 RS -380 1845 28 S45 -1882 -1239 62 S11 1882 -84 96 CL -505 1845 29 S44 -1882 -1379 63 S10 1882 41 97 P2 -630 1845 30 S43 -1487 -1845 64 S9 1882 166 98 P1 -755 1845 31 S42 -1187 -1845 65 S8 1882 291 99 E -880 1845 32 S41 -1062 -1845 66 S7 1882 416 100 FRM -1005 1845 33 S40 -937 -1845 67 S6 1882 541 34 S39 -812 -1845 68 S5 1882 666 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 6 PIN DESCRIPTION Table 1. Pin Description Pin Number QFP(TQFP) Symbol Input / Output Description 3(1) 78(76) 73(71), 8(6) V DD V SS V EE1.2 Power For internal logic circuit (+5V 10%) GND (0V) For LCD driver circuit VSS = 0V, VDD = +5V 10%, VDD-VEE = 8V - 17V VEE1 and VEE2 is connected by the same voltage. 74(72), 7(5) 76(74), 5(3) 77(75), 4(2) 75(73), 6(4) V0L, V0R V2L, V2R V3L, V3R V5L, V5R Power Bias supply voltage terminals to drive the LCD. Select Level V0L(R), V5L(R) Non-Select Level V2L(R), V3L(R) V0L and V0R (V2L & V2R, V3L & V3R, V5L & V5R) should be connected by the same voltage. 92(89) 91(87) 90(86) CS1B CS2B CS3 Input Chip selection In order to interface data for input or output, the terminals have to be CS1B = L, CS2B = L, and CS3 = H. 2(100) M Input Alternating signal input for LCD driving. 1(99) ADC Input Address control signal to determine the relation between Y address of display RAM and terminals from which the data is output. ADC = H Y0: S1 - Y63: S64 ADC = L Y0: S64 - Y63: S1 100(98) FRM Input Synchronous control signal. Presets the 6-bit Z counter and synchronizes the common signal with the frame signal when the frame signal becomes high. 99(97) E Input Enable signal. Write mode (R/W = L) data of DB<0:7> is latched at the falling edge of E. Read mode (R/W = H) DB<0:7> appears the reading data while E is at high level. 98(96) 97(95) CLK1 CLK2 Input 2 phase clock signal for internal operation. Used to execute operations for input/output of display RAM data and others. 96(94) CL Input Display synchronous signal. Display data is latched at rising time of the CL signal and increments the Z-address counter at the CL falling time. 95(93) RS Input Data or Instruction. RS = H DB<0:7>: Display RAM data RS = L DB<0:7>: Instruction data 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 7 Table 1. Pin Description (Continued) Pin Number QFP(TQFP) Symbol Input / Output Description 94(92) R/W Input Read or Write. R/W = H Data appears at DB<0:7> and can be read by the CPU while E = H, CS1B = L, CS2B = L and CS3 = H . R/W = L Display data DB<0:7> can be written at falling of E when CS1B = L, CS2B = L and CS3 = H. 79-86 (77-84) DB0-DB7 Input/Output Data bus. Three state I/O common terminal. 72-9 (70-7) S1-S64 Output LCD segment driver output. Display RAM data 1: On Display RAM data 0: Off (relation of display RAM data & M) M L Data L H Output Level L H H V 2 V 0 V 3 V 5 93(91) RSTB Input Reset signal. When RSTB=L, - ON / OFF register becomes set by 0. (display off) Display start line register becomes set by 0 (Z-address 0 set, display from line 0) After releasing reset, this condition can be changed only by instruction. 87(85), 88(88) 89(90) NC No connection. (open) S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 8 MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Note Operating voltage V DD -0.3 to +7.0 V (1) Supply voltage V EE V DD -19.0 to V DD +0.3 V (4) V B -0.3 to V DD +0.3 V (1), (3) Driver supply voltage V LCD V EE -0.3 to V DD +0.3 V (2) Operating temperature T OPR -30 to +85 C Storage temperature T STG -55 to +125 C NOTES: 1. Based on V SS = 0V. 2. Applies the same supply voltage to V EE1 and V EE2 . V LCD =V DD -V EE . 3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0 - DB7. 4. Applies to V0L(R), V2L(R), V3L(R) and V5L(R). Voltage level: V DD V0L = V0R V2L = V2R V3L = V3R V5L = V5R V EE . 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 9 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (V DD = +5V 10%, V SS = 0V, V DD -V EE = 8 to 17V, Ta =-30 to +85 C) Characteristic Symbol Condition Min Typ Max Unit Note V IH1 - 0.7V DD - V DD V (1) Input high voltage V IH2 - 2.0 - V DD V (2) V IL1 - 0 - 0.3V DD V (1) Input low voltage V IL2 - 0 - 0.8 V (2) Output high voltage V OH I OH = -200A 2.4 - - V (3) Output low voltage V OL I OL = 1.6mA - - 0.4 V (3) Input leakage current I LKG V IN = V SS - V DD -1.0 - 1.0 A (4) Three-state(off) input current I TSL V IN = V SS - V DD -5.0 - 5.0 A (5) Driver input leakage current I DIL V IN = V EE - V DD -2.0 - 2.0 A (6) I DD1 During display - - 100 A (7) Operating current I DD2 During access Access cycle = 1MHz - - 500 A (7) On resistance R ON V DD -V EE = 15V I LOAD = 0.1mA - - 7.5 K (8) NOTES: 1. CL, FRM, M RSTB, CLK1, CLK2 2. CS1B, CS2B, CS3, E, R/W, RS, DB0 - DB7 3. DB0 - DB7 4. Except DB0 - DB7 5. DB0 - DB7 at high impedance 6. V0L(R), V2L(R), V3L(R), V5L(R) 7. 1/64 duty, FCLK = 250kHz, frame frequency = 70HZ, output: no load 8. V DD - V EE = 15.5V V0L(R) > V2L(R) = V DD - 2/7 (V DD -V EE ) > V3L(R) = V EE + 2/7 (V DD -V EE ) > V5L(R) S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 10 AC CHARACTERISTICS (V DD = +5V 10%, V SS = 0V, Ta =-30 to +85 C) Clock Timing Characteristic Symbol Min Typ Max Unit CLK1, CLK2 cycle time t CY 2.5 - 20 s CLK1 "low" level width t WL1 625 - - CLK2 "low" level width t WL2 625 - - CLK1 "high" level width t WH1 1875 - - CLK2 "high" level width t WH2 1875 - - CLK1-CLK2 phase difference t D12 625 - - CLK2-CLK1 phase difference t D21 625 - - CLK1, CLK2 rise time t R - - 150 CLK1, CLK2 fall time t F - - 150 ns CLK1 CLK2 t CY t WH1 t F t R t WL1 t D12 t D21 t WL2 t F t R t WH2 t CY 0.7V DD 0.3V DD 0.7V DD 0.3V DD Figure 1. External Clock Waveform 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 11 Display Control Timing Characteristic Symbol Min Typ Max Unit FRM delay time t DF -2 - +2 us M delay time t DM -2 - +2 us CL "low" level width t WL 35 - - us CL "high" level width t WH 35 - - us 0.7V DD 0.3V DD t WL 0.7V DD 0.3V DD t DF t DF t WH t DM 0.7V DD 0.3V DD Figure 2. Display Control Waveform S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 12 MPU Interface Characteristic Symbol Min Typ Max Unit E cycle t C 1000 - - ns E high level width t WH 450 - - ns E low level width t WL 450 - - ns E rise time t R - - 25 ns E fall time t F - - 25 ns Address set-up time t ASU 140 - - ns Address hold time t AH 10 - - ns Data set-up time t DSU 200 - - ns Data delay time t D - - 320 ns Data hold time (write) t DHW 10 - - ns Data hold time (read) t DHR 20 - - ns E R/W CS1B, CS2B, CS3, RS DB0 - 7 t C t WL t WH t R t F t AH t ASU t ASU t AH 0.8V 2.0V t DSU t DHW 2.0V 0.8V Figure 3. MPU Write Timing 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 13 E R/W CS1B, CS2B, CS3, RS DB0 - 7 t C t WL t WH t R t F t AH t ASU t ASU t AH t D t DHR Figure 4. MPU Read Timing S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 14 OPERATING PRINCIPLES AND METHODS I/O BUFFER Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS1B-CS3. INPUT REGISTER Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then Writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. OUTPUT REGISTER Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode and R/W and RS = H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W = H, RS = L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read. RS R/W Function L Instruction L H Status read (busy check) L Data write (from input register to display data RAM) H H Data read (from display data RAM to output register) 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 15 RESET The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. Display off Display start line register become set by 0. (Z-address 0) While RSTB is low, No instruction except status read can be accepted. Therefore, execute other instructions after making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read instruction. The Conditions of power supply at initial power up are shown in table 1. Table 2. Power Supply Initial Conditions Item Symbol Min Typ Max Unit Reset time t RS 1.0 - - us Rise time t R - - 200 ns t R t RS 4.5V VDD RSTB 0.7V DD 0.3V DD S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 16 Busy Flag Busy Flag indicates that S6B0108 is operating or no operating. When busy flag is high, S6B0108 is in internal operating. When busy flag is low, S6B0108 can accept the data or instruction. DB7 indicates busy flag of the S6B0108. N + 2 N + 1 N RS R/W E Address Data at address N Data at address N+1 Output register DB0-DB7 Busy check Write address N Busy check Read data (dummy) Busy check Read data at address N Busy check Data read address N + 1 Busy Check
E Busy Flag T Busy 1/f CLK < T Busy < 3/f CLK f CLK is CLK1, CLK2 frequency Busy Flag 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 17 Display ON / OFF Flip - Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flip- flop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal. X Page Register X page register designates pages of the internal display data RAM. Count function is not available. An address is set by instruction. Y Address Counter Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data. Display Data RAM Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of liquid crystal display, write data 1. The other way, off state, writes 0. Display data RAM address and segment output can be controlled by ADC signal. ADC = H Y-address 0:S1 - Y address 63:S64 ADC = L Y-address 0:S64 - Y address 63:S1 ADC terminal connect the V DD or V SS . Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen. S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 18 DISPLAY CONTROL INSTRUCTION The display control instructions control the internal state of the S6B0108. Instruction is received from MPU to S6B0108 for the display control. The following table shows various instructions. Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Display on/off L L L L H H H H H L/H Controls the display on or off. Internal status and display RAM data is not affected. L: OFF, H: ON Set address (Y address) L L L H Y address (0 - 63) Sets the Y address in the Y address counter. Set page (X address) L L H L H H H Page (0 - 7) Sets the X address at the X address register. Display start line (Z address) L L H H Display start line (0 - 63) Indicates the display data RAM displayed at the top of the screen. Status read L H Busy L On / Off Reset L L L L Read status. BUSY L: Ready H: In operation ON/OFF L: Display ON H: Display OFF RESET L: Normal H: Reset Write display data H L Write data Writes data (DB0:7) into display data RAM. After writing instruction, Y address is increased by 1 automatically. Read display data H H Read data Reads data (DB0: 7) from display data RAM to the data bus. 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 19 DISPLAY ON / OFF RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 1 1 D The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1. SET ADDRESS (Y ADDRESS) S R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Y address (AC0 - AC5) of the display data RAM is set in the Y address counter. An address is set by instruction and increased by 1 automatically by read or write operations of display data. SET PAGE (X ADDRESS) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 1 AC2 AC1 AC0 X address(AC0 - AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is executed in this specified page until the next page is set. DISPLAY START LINE (Z ADDRESS) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 Z address (AC0 - AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others(1/32 - 1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 20 STATUS READ RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY 0 ON/OFF RESET 0 0 0 0 BUSY When BUSY is 1, the Chip is executing internal operation and no instructions are accepted. When BUSY is 0, the Chip is ready to accept any instructions. ON/OFF When ON/OFF is 1, the display is OFF. When ON/OFF is 0, the display is ON. RESET When RESET is 1, the system is being initialized. In this condition, no instructions except status read can be accepted. When RESET is 0, initializing has finished and the system is in the usual operation condition. WRITE DISPLAY DATA RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Writes data (D0 - D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically. READ DISPLAY DATA RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Reads data (D0 - D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically. 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 21 APPLICATION CIRCUIT 1/64 DUTY COMMON DRIVER (S6B0107) INTERFACE CIRCUIT DIO1 DIO2 M FRM CLK1 CLK2 CL2 C1 C64 R C RC R S T B D B 7 - D B 0 E R S R / W C S 3 C S 2 B C S 1 B V DD ADC Open Open S1 S64 SEG1 SEG64 LCD COM1 COM64 From MPU V 0R , V 0L V 5R , V 5L V 2R , V 2L V 3R , V 3L V EE1 , V EE2 V SS V DD V 0 V 5 V 2 V 3 V SS M FRM CLK1 CLK2 CL2 S6B0108 S6B0107 V 0R , V 0L V 5R , V 5L V 1R , V 1L V 4R , V 4L V EE V 0 V 5 V 1 V 4 V EE V SS DS1 SD2 PCLK2 MS FS SHL V DD V DD V DD R 1 R 1 R 2 R 1 R 1 V EE V 5 V 4 V 3 V 2 V 1 V 0 - V EE R 1 R 2 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 22 TIMING DIAGRAM (1/64 DUTY) CLK1 1 2 3 48 49 64 1 2 3 64 1 2 3 64 1 1 Frame 1 Frame V4 V5 V1 V4 V1 V5 V1 V0 V4 V4 V0 V4 V5 V1 V4 V0 V1 V5 V4 V0 V1 V2 V2 V5 V3 V5 V3 V3 V0 V2 V0 V2 V3 CLK2 CL FRM M C1 C2 C64 S1 S64 Input Common Segment 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 23 LCD PANEL INTERFACE APPLICATION CIRCUIT LCD Panel (128 512dots) S6B0108 No. 1 S1 ..... S64 S6B0108 No. 2 S1 ..... S64 S6B0108 No. 8 S1 ..... S64 . . . . . C1 C2 C3 C64 CR R COM1 COM2 COM3 COM64 S6B0107 (master) C1 C2 C3 C64 S6B0107 (slave) COM65 COM66 COM67 COM128 . . . . . . . . . . . . . . . S1 ..... S64 No. 9 S6B0108 S1 ..... S64 No. 10 S6B0108 S1 ..... S64 No. 16 S6B0108 . . . . . . . . . . . . . . . . . . . . C f R f S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 2 BLOCK DIAGRAM 64 bit 4- Level Driver 64 bit Bi-Directional Shift Register Data Shift Direction & Phase Selection Control Circuit OSC C 1 C 2 C 3 C 6 2 C 6 3 C 6 4 V0L V1L V4L V5L DIO1 PCLK2 SHL C R M CL2 DIO2 V5R Timing Generator Circuit CR FRM CLK1 CLK2 V D D V S S V E E D S 1 D S 2 M S F S V4R V1R V0R
64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 3 PIN CONFIGURATION 100 QFP S 6 B 0 1 0 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS C 2 3 C 2 4 C 2 5 C 2 6 C 2 7 C 2 8 C 2 9 C 3 0 C 3 1 C 3 2 C 3 3 C 3 4 C 3 5 C 3 6 C 3 7 C 3 8 C 3 9 C 4 0 C 4 1 C 4 2 D S 1 D S 2C N CR N C C R N C S H L V S S N C M S C L K 2 C L K 1 N C F R M M N C P C L K 2 D I O 2 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R NC CL2 NC
S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 4 PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP) 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 11 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 C 2 2 C 2 3 C 2 4 C 2 5 C 2 6 C 2 7 C 2 8 C 2 9 C 3 0 C 3 1 C 3 2 C 3 3 C 3 4 C 3 5 C 3 6 C 3 7 C 3 8 C 3 9 C 4 0 C 4 1 C 4 2 C 4 3 V D D D I O 1 F S D S 1 D S 2C N CR N C C R N C S H L V S S N C M S C L K 2 C L K 1 N C F R M M N C P C L K 2 D I O 2 N C C L 2 N C 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L Chip size: 3450 4000 PAD size: 100 100 Unit : m (0, 0) X Y 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R
There is the mark S6B0107 on the center of the chip. 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 5 PAD CENTER COORDINATES (100QFP) Pad Number Pad Name Coordinate Pad Number Pad Name Coordinate Pad Number Pad Name Coordinate X Y X Y X Y 1 C22 -1314.5 1775.4 32 DS2 -677.6 -1775 71 C52 1500.9 630 2 C21 -1499.9 1630 34 C -527.6 -1775 72 C51 1500.9 755 3 C20 -1499.9 1505 35 R -377.6 -1775 73 C50 1500.9 880 4 C19 -1499.9 1380 37 CR -227.6 -1775 74 C49 1500.9 1005 5 C18 -1499.9 1255 39 SHL -77.6 -1775 75 C48 1500.9 1130 6 C17 -1499.9 1130 40 VSS 113.8 -1775 76 C47 1500.9 1255 7 C16 -1499.9 1005 42 MS 308.7 -1775 77 C46 1500.9 1380 8 C15 -1499.9 880 43 CLK2 458.7 -1775 78 C45 1500.9 1505 9 C14 -1499.9 755 44 CLK1 608.7 -1775 79 C44 1500.9 1630 10 C13 -1499.9 630 46 FRM 758.7 -1775 80 C43 1310.5 1775.4 11 C12 -1499.9 505 47 M 908.7 -1775 81 C42 1185.5 1775.4 12 C11 -1499.9 380 49 PCLK2 1058.7 -1775 82 C41 1060.5 1775.4 13 C10 -1499.9 255 50 DI02 1208.7 -1775 83 C40 935.5 1775.4 14 C9 -1499.9 130 52 CL2 1358.7 -1775 84 C39 810.5 1775.4 15 C8 -1499.9 5 54 V0R 1500.9 -1495 85 C38 685.5 1775.4 16 C7 -1499.9 -120 55 V5R 1500.9 -1370 86 C37 560.5 1775.4 17 C6 -1499.9 -245 56 V4R 1500.9 -1245 87 C36 435.5 1775.4 18 C5 -1499.9 -370 57 V1R 1500.9 -1120 88 C35 310.5 1775.4 19 C4 -1499.9 -495 58 VEE 1500.9 -995 89 C34 185.5 1775.4 20 C3 -1499.9 -620 59 C64 1500.9 -870 90 C33 60.5 1775.4 21 C2 -1499.9 -745 60 C63 1500.9 -745 91 C32 -64.5 1775.4 22 C1 -1499.9 -870 61 C62 1500.9 -620 92 C31 -189.5 1775.4 23 VEE -1499.9 -995 62 C61 1500.9 -495 93 C30 -314.5 1775.4 24 V1L -1499.9 -1120 63 C60 1500.9 -370 94 C29 -439.5 1775.4 25 V4L -1499.9 -1245 64 C59 1500.9 -245 95 C28 -564.5 1775.4 26 V5L -1499.9 -1370 65 C58 1500.9 -120 96 C27 -689.5 1775.4 27 V0L -1499.9 -1495 66 C57 1500.9 5 97 C26 -814.5 1775.4 28 VDD -1345.6 -1775 67 C56 1500.9 130 98 C25 -939.5 1775.4 29 DI01 -1127.6 -1775 68 C55 1500.9 255 99 C24 -1064.5 1775.4 30 FS -977.6 -1775 69 C54 1500.9 380 100 C23 -1189.5 1775.4 31 DS1 -827.6 -1775 70 C53 1500.9 505 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 6 100 TQFP (S6B2107) C 1 9 C 1 8 C 1 7 C 1 6 C 1 5 C 1 4 C 1 3 C 1 2 C 1 1 C 1 0 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 V E E V 1 L V 4 L V 5 L V 0 L V D D S6B2107 (100 TQFP) 1234567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 NC CL2 NC DIO2 PCLK2 NC M FRM NC CLK1 CLK2 MS NC VSS SHL NC CR NC R NC C DS2 DS1 FS DIO1 C 4 5 C 4 6 C 4 7 C 4 8 C 4 9 C 5 0 C 5 1 C 5 2 C 5 3 C 5 4 C 5 5 C 5 6 C 5 7 C 5 8 C 5 9 C 6 0 C 6 1 C 6 2 C 6 3 C 6 4 V E E V 1 R V 4 R V 5 R V 0 R
64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 7 PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 C 2 0 C 2 1 C 2 2 C 2 3 C 2 4 C 2 5 C 2 6 C 2 7 C 2 8 C 2 9 C 3 0 C 3 1 C 3 2 C 3 3 C 3 4 C 3 5 C 3 6 C 3 7 C 3 8 C 3 9 C 4 0 C 4 1 C 4 2 C 4 3 C 4 4 D I O 1 F S D S 1 D S 2C N CR N C C R N C S H L V S S N C M S C L K 2 C L K 1 N C F R M M N C P C L K 2 D I O 2 N C C L 2 N C C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD Chip size: 3850 X 100 PAD size: 100 X 100 Unit : m (0, 0) X Y
There is the mark S6B2107 on the center of the chip. S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 8 PAD CENTER COORDINATES (100-TQFP) Pad Number Pad Name Coordinate Pad Number Pad Name Coordinate Pad Number Pad Name Coordinate X Y X Y X Y 1 C19 -1697 1534 35 NC 69 C51 1697 784 2 C18 -1697 1409 36 SHL -195 -1821 70 C50 1697 909 3 C17 -1697 1284 37 VSS 0 -1821 71 C49 1697 1034 4 C16 -1697 1159 38 NC 72 C48 1697 1159 5 C15 -1697 1034 39 MS 195 -1821 73 C47 1697 1284 6 C14 -1697 909 40 CLK2 345 -1821 74 C46 1697 1409 7 C13 -1697 784 41 CLK1 495 -1821 75 C45 1697 1534 8 C12 -1697 659 42 NC 76 C44 1500 1822 9 C11 -1697 534 43 FRM 645 -1821 77 C43 1375 1822 10 C10 -1697 409 44 M 795 -1821 78 C42 1250 1822 11 C9 -1697 284 45 NC 79 C41 1125 1822 12 C8 -1697 159 46 PCLK2 945 -1821 80 C40 1000 1822 13 C7 -1697 34 47 DIO2 1095 -1821 81 C39 875 1822 14 C6 -1697 -91 48 NC 82 C38 750 1822 15 C5 -1697 -216 49 CL2 1245 -1821 83 C37 625 1822 16 C4 -1697 -341 50 NC 84 C36 500 1822 17 C3 -1697 -466 51 V0R 1697 -1466 85 C35 375 1822 18 C2 -1697 -591 52 V5R 1697 -1341 86 C34 250 1822 19 C1 -1697 -716 53 V4R 1697 -1216 87 C33 125 1822 20 VEE -1697 -841 54 V1R 1697 -1091 88 C32 0 1822 21 V1L -1697 -966 55 VEE 1697 -966 89 C31 -125 1822 22 V4L -1697 -1091 56 C64 1697 -841 90 C30 -250 1822 23 V5L -1697 -1216 57 C63 1697 -716 91 C29 -375 1822 24 V0L -1697 -1341 58 C62 1697 -591 92 C28 -500 1822 25 VDD -1697 -1466 59 C61 1697 466 93 C27 -625 1822 26 DIO1 -1245 -1821 60 C60 1697 -341 94 C26 -750 1822 27 FS -1095 -1821 61 C59 1697 -216 95 C25 -875 1822 28 DS1 -945 -1821 62 C58 1697 -91 96 C24 -1000 1822 29 DS2 -795 -1821 63 C57 1697 34 97 C23 -1125 1822 30 C -645 -1821 64 C56 1697 159 98 C22 -1250 1822 31 NC 65 C55 1697 284 99 C21 -1375 1822 32 R -495 -1821 66 C54 1697 409 100 C20 -1500 1822 33 NC 67 C53 1697 534 34 CR -345 -1821 68 C52 1697 659 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 9 PIN DESCRIPTION Table 1. Pin Description Pin Number QFP (TQFP) Symbol I/ O Description 28(25) 40(37) 23(20), 58(55) V DD V SS V EE
Power For internal logic circuit (+5V 10%) GND ( = 0 V) For LCD driver circuit 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) V0L, V0R V1L, V1R V4L, V4R V5L, V5R Power Bias supply voltage terminals to drive LCD. Slelect Level V0L (R), V5L (R) Non-Select Level V1L (R), V4L (R)
V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should be connected by the same voltage. 42(39) MS Input Selection of master/ slave mode - Master mode (MS = 1) DIO1, DIO2, CL2 and M is output state. - Slave mode (MS = 0) SHL = 1 DIO1 is input state (DIO2 is output state) SHL = 0 DIO2 is input state (DIO1 is output state) CL2 and M are input state. 39(36) SHL Input Selection of data shift direction. SHL H L Data Shift Direction DIO1 C1 ...... C64 DIO2 DIO2 C64 ...... C1 DIO1
49(46) PCLK2 Input Selection of shift clock (CL2) phase. PCLK2 H L Shift Clock (CL2) Phase Data shift at the rising edge of CL2 Data shift at the falling edge of CL2
30(27) FS Input Selection of oscillation frequency. - Master mode When the frame frequency is 70 Hz, the oscillation frequency should be fosc = 430kHz at FS = 1(V DD ) fosc = 215kHz at FS = 0(V SS ) - Slave mode Connect to V DD . S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 10 Table 1. Pin Description (Continued) Pin Number QFP (TQFP) Symbol I/ O Description 31(28) 32(29)
DS1 DS2
Input Selection of display duty. - Master mode DS1 L DS2 L L H H L Duty 1/ 48 1/ 64 1/ 96 H H 1/ 128
- Slave mode Connect to V DD
33(30) 35(32) 37(34) C R CR RC Oscillator - Master mode: Use these terminals as shown below. S6B0107 R C R f CR C f S6B0107 R C CR Open Open External - Slave mode: Stop the oscillator as shown below. R C CR Open Open V DD
44(41) 43(40) CLK1 CLK2 Output Operating clock output for the S6B0108 - Master mode: connection to CLK1 and CLK2 of the S6B0108 - Slave mode: open 46(43) FRM Output Synchronous frame signal. - Master mode: connection to FRM of the S6B0108 - Slave mode: open 47(44) M Input/ Output Alternating signal input for LCD driving. - Master mode: output state Connection to M of the S6B0108 - Slave mode: input state Connection to the controller 52(49) CL2 Input / Output Data shift clock - Master mode: output state Connection to CL of the S6B0108 - Slave mode: input state Connection to shift clock terminal of the controller. 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 11 29(26) 50(47) DIO1 DIO2 Input/ Output Data input/ output pin of internal shift register. MS H DS2 H L L L DIO1 Output Output Input H Output DIO2 Output Output Output Input
S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 12 Table 1. Pin Description (Continued) Pin Number QFP (TQFP) Symbol I/ O Description 22-1(19-1) 100-59(100- 56) C1-C64 Output Common signal output for LCD driving. Data L L H H M Out L H L H V 1 V 4 V 5 V 0
34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50) NC No connection MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Note Operating voltage V DD -0.3 to +7.0 V (1)
Supply voltage V EE V DD -19.0 to V DD +0.3 V (4)
Driver supply voltage V B -0.3 to V DD +0.3 V (1),
(2)
V LCD V EE -0.3 to V DD +0.3 V (3), (4)
Operating temperature T OPR -30 to +85 C - Storage temperature T STG -55 to +125 C -
NOTES: 1. Based on V SS = 0V 2. Applies to input terminals and I/ O terminals at high impedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R)) 3. Applies to V0L(R), V1L(R), V4L(R) and V5L(R). 4. Voltage level: V DD V0L = V0R V1L = V1R V4L = V4R V5L = V5R V EE .
64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 13 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (V DD = +5V 10%, V SS = 0V, | V DD -V EE | =8 - 17V, TA = -30 - +85C) Characteristic Symbol Condition Min Typ Max Unit Note High V IH
- 0.7V DD
- V DD
V (1)
Input Voltage Low V IL
V SS
- 0.3V DD
High V OH I OH = -0.4mA V DD -0.4 - - V (2)
Output voltage Low V OL I OL = 0.4mA - - 0.4
Input leakage current I LKG V IN = V DD -V SS
-1.0 - 1.0 A (1)
OSC frequency f OSC
Rf = 47k 2% Cf = 20pf 5% 315 450 585 kHz On resistance (VDIV- Ci) R ON
V DD -V EE = 17V Load current = 150A - - 1.5 K Operating current I DD1
Master mode 1/ 128 Duty - - 1.0 mA (3)
I DD2
Slave mode 1/ 128 Duty - - 200 A (4)
Supply current I EE
Master mode 1/ 128 Duty - - 100 (5)
Operating f op1
Master mode External clock 50 - 600 kHz Frequency f op2
Slave mode 0.5 - 1500
NOTES: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/ O terminals DIO1, DIO2, M and CL2 in the input state. 2. Applies to output terminals CLK1, CLK2 and FRM and I/ O terminals DIO1, DIO2, M and CL2 in the output state. 3. This value is specified at about the current flowing through V SS . Internal oscillation circuit: Rf = 47k, Cf = 20pF. Each terminal of DS1, DS2, FS, SHL and MS is connected to V DD and out is no load. 4. This value is specified at about the current flowing through V SS . Each terminal of DS1, DS2, FS, SHL, PCLK2 and CR is connected to V DD , and MS is connected to V SS . CL2, M, DIO1 is external clock. 5. This value is specified at about the current flowing through V EE . Don t connect to V LCD (V1-V5).
S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 14 AC CHARACTERISTICS (V DD = 5V 10%, TA = -30C - +85C) Master Mode (MS = V DD , PCLK2 = V DD , Cf = 20pF, Rf = 47k) CL2 DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) CLK1 t su t su t D DIO2 (SHL = V DD ) DIO1 (SHL = V SS ) FRM M CLK2 0.7V DD 0.3V DD 0.7V DD 0.3V DD t WLC t WHC t DF t DM t DM t F t R t WH1 t D12 t WL1 t D21 t F t R t WH2 t D t DH t WHC
64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 15 Master Mode Characteristic Symbol Min Typ Max Unit Data setup time t SU 20 - - s Data hold time t DH
40 - - Data delay time t D
5 - - FRM delay time t DF
-2 - 2 M delay time t DM
-2 - 2 CL2 low level width t WLC
35 - - CL2 high level width t WHC
35 - - CLK1 low level width t WL1
700 - - ns CLK2 low level width t WL2
700 - - CLK1 high level width t WH1
2100 - - CLK2 high level width t WH2
2100 - - CLK1-CLK2 phase difference t D12
700 - - CLK2-CLK1 phase difference t D21
700 - - CLK1, CLK2 rise/ fall time t R / t F - - 150
S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 16 Slave Mode (MS = V SS ) t WLC t WHC1 CL2 (PLK2 = V SS ) CL2 (PLK2 = V DD ) DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) Input Data DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) Onput Data t F t R t WLC1 0.7V DD 0.3V DD 0.7V DD 0.3V DD 0.7V DD 0.3V DD t WHC2 t SU t R t F t D t HCL t H
Characteristics Symbol Min Typ Max Unit Note CL2 low level width t WLC1 450 - - ns PCLK2 = V SS
CL2 high level width t WHC1 150 - - ns PCLK2 = V SS
CL2 low level width t WLC2 150 - - ns PCLK2 = V DD
CL2 high level width t WHL 450 - - ns PCLK2 = V DD
Data setup time t SU 100 - - ns Data hold time t DH 100 - - ns Data delay time t D - - 200 ns (NOTE)
Output data hold time t H 10 - - ns CL2 rise/ fall time t R / t F - - 30 ns NOTE: Connect load CL = 30pF
Output 30pF 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 17 FUNCTIONAL DESCRIPTION RC Oscillator The RC Oscillator generates CL2, M, FRM of the S6B0107, and CLK1 and CLK2 of the S6B0108 by the oscillation resister R and capacitor C. When selecting the master/ slave mode, the oscillation circuit is as following: Master Mode: In the master mode, use these terminals as shown below. S6B0107 R C R f CR C f 47K 20pF Internal Oscillation S6B0107 R C CR Open Open External Clock External Clock
Slave Mode: In the slave mode, stop the oscillator as shown below. S6B0107 R C CR Open Open V DD
Timing Generation Circuit It generates CL2, M, FRM, CLK1 and CLK2 by the frequency from the oscillation circuit. Selection of Master/ Slave (M/ S) Mode - When M/ S is H, it generates CL2, M, FRM, CLK1 and CLK2 internally. - When M/ S is L, it operates by receiving M and CL2 from the master device. Frequency Selection (FS) To adjust FRM frequency by 70Hz, the oscillation frequency should be as follows: FS Oscillation Frequency H f OSC
= 430kHz L f OSC
= 215kHz
In the slave mode, it is connected to V DD . S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 18 Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 DS2 DUTY L L 1/ 48 H 1/ 64 H L 1/ 96 H 1/ 128
Data Shift & Phase Select Control Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the CL2 according to PCLK2. PCLK2 Phase Selection H Data shift on rising edge of CL2 L Data shift on falling edge of CL2
Data Shift Direction Selection When M/ S is connected to V DD , DIO1 and DIO2 terminal is only output. When M/ S is connected to V SS , it depends on the SHL. MS SHL DIO1 DIO2 Direction of Data H H Output Output C1 C64 L Output Output C64 C1 L H Input Output DIO1 C1 C64 DIO2 L Output Input DIO2 C64 C1 DIO1
S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 22 POWER DRIVER CIRCUIT To S6B0108 V0 V1 V2 V3 V4 V5 V DD R1 R1 R2 R1 R1 VR V0L/ R V1L/ R V4L/ R V5L/ R V EE S6B0107 V DD V EE
When duty factor is 1/ 48, the value of R1 & R2 should satisfy. R1/ (4R1 + R2) = 1/ 8 R1 + 3k, R2 = 12k 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 23 APPLICATION CIRCUIT 1/ 128 duty Segment driver (S6B0108) interface circuit LCD Panel V 0 R / L V 2 R / L V 3 R / L V 5 R / L CS3 CS2B CS1B DB0 -DB7 RSTB E R/ W RS F R M C L K 1 C L K 2 M V D D C L V S S V 0 R / L V 2 R / L V 3 R / L V 5 R / L V E E CS3 CS2B CS1B DB0 -DB7 RSTB E R/ W RS F R M C L K 1 C L K 2 M V D D C L V S S S6B0108 S6B0108 S 1
-
S 6 4 S 1
-
S 6 4 1 5 1 5 S E G 1 2 8 S E G 1 COM1 COM128 V E E V 2 R / L V 3 R / L CS3 CS2B CS1B DB0 -DB7 RSTB E R/ W RS F R M C L K 1 C L K 2 MV D D C L V SS S6B0108 S 1
-
S 6 4 V E E V 0 R / L V 5 R / L V E E V 2 R / L V 3 R / L CS3 CS2B CS1B DB0 -DB7 RSTB E R/ W RS F R M C L K 1 C L K 2 MV D D C L V SS S6B0108 S 1
-
S 6 4 V 0 R / L V 5 R / L MPU R S R / W E R S T B D B 0
-
D B 7 C S 1 B C S 2 B C S 3 1 5 1 5 1 5 C 1 C 6 4 C CR R DS1 DS2 PCLK2 MS FS SHL V DD V S S V 0 R / L V 1 R / L V 4 R / L V 5 R / L V E E DIO2 DIO1 CL2 M CLK2 CLK1 FRM C 1 C 6 4 V D D V S S V 0 R / L V 1 R / L V 4 R / L V 5 R / L V E E CLK2 CLK1 FRM C P C L K 2 F S D S 1 K S 2 S H L CR R DIO2 M CL2 M S S6B0107 (master) S6B0107 (slave) 2 5 5 C 1 R 1 o p e n o p e n 5 o p e n o p e n o p e n o p e n o p e n V D D V 0 V 1 V 2 V 3 V 4 V 5 V E E V D D