UNIVERSITY OF NEBRASKA AT OMAHA

COURSE SYLLABUS/DESCRIPTION
Department and Course Number CSCI 3710
Course Title Introduction to Computer Organization and
Architecture
Course Coordinator assan !arhat
Total Credits 3
Date o" #ast $e%ision &une 1'( )003
1.0 Course Descr!"o#
1*1 O%er%ie+ o" content and purpose o" the course ,catalog description-
This course is built on the principal o" digital logic co%ered in CSCI )710* Topics
co%ered include. $egister Trans"er #anguages( Non/pipelined C01 detailed design both
hard+ired and micro/programmed( instruction "ormat "ormats "or three architectures
Stac2( AC/based and general purpose based( assembl3 programming( memor3
organization and cache( "loating/point arithmetic( and input/output organization*
1*) !or +hom course is intended
The course is intended "or undergraduate computer science ma4ors*
1*3 0rere5uisites o" the course ,courses-
CSCI )710 and CSCI 33)0 ,could be ta2en concurrentl3-
1*6 0rere5uisites o" the course ,topics-
1*6*1 7no+ledge o" the principals o" digital logic design "or both combinational and
se5uential circuits
1*6*) 7no+ledge o" programming
1*8 1nusual circumstances o" the course
None
$.0 O%&ec"'es
)*1 Stud3 $egister Trans"er #anguage ,$T#-*
)*) Stud3 the details o" a simple AC/based C01 ,hard+ired-*
)*3 Stud3 the details o" a simple AC/based C01 ,microprogrammed-*
)*6 Stud3 assembl3 instruction "ormats "or di""erent architectures ,CISC( $ISC etc*-*
)*8 Con%ert high/le%el constructs to assembl3 constructs*
)*9 Stud3 computer arithmetic including "loating/point arithmetic*
)*7 Stud3 memor3 hierarch3 +ith an emphasis on cache organization*
)*: Stud3 input/output organization and the di""erent "orms o" interrupts*
(.0 Co#"e#" )#* Or+)#,)"o#
Contact hours
3*1 $egister Trans"er and ;icrooperations <*<
3*1*1 $egister Trans"er #anguage
3*1*) $egister Trans"er
3*1*3 =us and ;emor3 Trans"ers
3*1*3*1 Three/State =us =u""ers
3*1*3*) ;emor3 Trans"er
3*1*6 Arithmetic ;icrooperations
3*1*6*1 =inar3 Adder
3*1*6*) =inar3 Adder/Subtractor
3*1*6*3 =inar3 Incrementer
3*1*6*6 Arithmetic Circuit
3*1*8 #ogic ;icrooperations
3*1*8*1 #ist o" #ogic ;icrooperations
3*1*8*) ard+are Implementation
3*1*9 Shi"t ;icrooperations
3*1*9*1 ard+are Implementation
3*1*7 Arithmetic #ogic Shi"t 1nit
3*) AC/=ased Computer Organization and Design <*<
3*)*1 Instruction Codes
3*)*1*1 Stored 0rogram Organization
3*)*1*) Indirect Address
3*)*) Computer $egisters
3*)*)*1 Common =us S3stem
3*)*3 Computer Instructions
3*)*3*1 Instruction Set Completeness
3*)*6 Timing and Control
3*)*8 Instruction C3cle
3*)*8*1 !etch and Decode
3*)*9 $egister/$e"erence Instructions
3*)*7 ;emor3/$e"erence Instructions
3*)*: Input/Output and Interrupts
3*)*:*1 Input/Output Con"iguration
3*)*:*) Input/Output Instructions
3*)*:*3 0rogram Interrupt
3*)*:*6 Interrupt C3cle
3*)*' Complete Computer Description
3*)*10 Design o" =asic Computer
3*)*10*1 Control o" #ogic >ates
3*)*10*) Control o" $egisters and ;emor3
3*)*10*3 Control o" Single !lip/!lops
3*)*10*6 Control o" Common =us
3*)*11 Design o" Accumulator #ogic
3*)*11*1Control o" AC $egister
3*)*11*)Adder and #ogic Circuit
3*3 Assembl3 0rogramming <*<
3*3*1 ;achine #anguage
3*3*) Assembl3 #anguage
3*3*)*1 $ules o" the #anguage
3*3*)*) Translation to =inar3
3*3*3 The Assembler
3*3*3*1 $epresentation o" S3mbolic 0rogram in ;emor3
3*3*3*) !irst 0ass
3*3*3*3 Second 0ass
3*3*6 0rogram #oops
3*3*8 0rogramming Arithmetic and #ogic Operations
3*3*8*1 ;ultiplication 0rogram
3*3*8*) Double/0recision Addition
3*3*8*3 #ogic Operations
3*3*8*6 Shi"t Operations
3*3*9 Subroutines
3*3*9*1 Subroutines 0arameters and Data #in2age
3*3*7 Input/Output 0rogramming
3*3*7*1 Character ;anipulation
3*3*7*) 0rogram Interrupt
3*6 ;icroprogrammed Control design <*<
3*6*1 Control ;emor3
3*6*) Address Se5uencing
3*6*)*1 Conditional =ranching
3*6*)*) ;apping o" Instruction
3*6*)*3 Subroutines
3*6*3 ;icroprogram ?@ample
3*6*3*1 Computer Con"iguration
3*6*3*) ;icroinstruction !ormat
3*6*3*3 S3mbolic ;icroinstructions
3*6*3*6 The !etch $outine
3*6*3*8 S3mbolic ;icroprogram
3*6*3*9 =inar3 ;icroprogram
3*6*6 Design o" Control 1nit
3*6*6*1 ;icroprogram Se5uencer
3*8 Alternati%e 0rocessor Architectures and Instruction t3pes <*<
3*8*1 >eneral $egister Organization
3*8*1*1 Control Aord
3*8*1*) ?@amples o" ;icrooperations
3*8*) Stac2 Organization
3*8*)*1 $egister Stac2
3*8*)*) ;emor3 Stac2
3*8*3 Instruction !ormats
3*8*3*1 Three/Address Instructions
3*8*3*) T+o/Address Instructions
3*8*3*3 One/Address Instructions
3*8*3*6 Bero/Address Instructions
3*8*3*8 $ISC Instructions
3*8*6 Addressing ;odes
3*8*8 Data Trans"er and ;anipulation
3*8*8*1 Data Trans"er Instructions
3*8*8*) Data ;anipulation Instructions
3*8*8*3 Arithmetic Instructions
3*8*8*6 #ogical and =it ;anipulation Instructions
3*8*8*8 Shi"t Instructions
3*8*9 0rogram Control
3*8*9*1 Status =it Conditions
3*8*9*) Conditional =ranch Instructions
3*8*9*3 Subroutine Call and $eturn
3*8*9*6 0rogram Interrupt
3*8*9*8 T3pes o" Interrupts
3*8*7 $educed Instruction Set Computer ,$ISC-
3*8*7*1 CISC Characteristics
3*8*7*) $ISC Characteristics
3*8*7*3 O%erlapped $egister Aindo+s
3*9 0ipeline 0rocessing <*<
3*9*1 0ipelining
3*9*1*1 >eneral Considerations
3*9*) Arithmetic 0ipeline
3*9*3 Instruction 0ipeline
3*9*3*1 ?@ample. !our/Segment Instruction 0ipeline
3*9*3*) Data Dependenc3
3*9*3*3 andling o" =ranch Instructio
3*9*3*6 $ISC 0ipeline
3*9*3*8 ?@ample. Three/Segment Instruction 0ipeline
3*9*3*9 Dela3ed #oad
3*9*3*7 Dela3ed =ranch
3*9*6 Cector 0rocessing
3*9*6*1 Cector Operations
3*9*6*) ;atri@ ;ultiplication
3*9*6*3 ;emor3 Interlea%ing
3*7 Computer Arithmetic <*<
3*7*1 ;ultiplication Algorithms
3*7*1*1 ard+are Implementation "or Signed/;agnitude Data
3*7*1*) ard+are Algorithm
3*7*1*3 =ooth ;ultiplication Algorithm
3*7*1*6 Arra3 ;ultiplier
3*7*) Di%ision Algorithms
3*7*)*1 ard+are Implementation "or Signed/;agnitude Data
3*7*)*) Di%ide O%er"lo+
3*7*)*3 ard+are Algorithm
3*7*)*6 Other Algorithms
3*7*3 !loating/0oint Arithmetic Operations
3*7*3*1 =asic Considerations
3*7*3*) $egister Con"iguration
3*7*3*3 Addition and Subtraction
3*7*3*6 ;ultiplication
3*7*3*8 Di%ision
3*: Input/Output Organization <*<
3*:*1 Input/Output Inter"ace
3*:*1*1 IDO =us and Inter"ace ;odules
3*:*1*) IDO %ersus ;emor3 =us
3*:*1*3 Isolated %ersus ;emor3/;apped IDO
3*:*1*6 ?@ample o" IDO Inter"ace
3*:*) As3nchronous Data Trans"er
3*:*)*1 Strobe Control
3*:*)*) andsha2ing
3*:*)*3 As3nchronous Serial Trans"er
3*:*)*6 As3nchronous Communication Inter"ace
3*:*)*8 !irst/In( !irst/Out =u""er
3*:*3 ;odes o" Trans"er
3*:*3*1 ?@ample o" 0rogrammed IDO
3*:*3*) Interrupt/Initiated IDO
3*:*3*3 So"t+are Considerations
3*:*6 0riorit3 Interrupt
3*:*6*1 Dais3/Chaining 0riorit3
3*:*6*) 0arallel 0riorit3 Interrupt
3*:*6*3 0riorit3 ?ncoder
3*:*6*6 Interrupt C3cle
3*:*6*8 So"t+are $outines
3*:*6*9 Initial and !inal Operations
3*:*8 Direct ;emor3 Access ,D;A-
3*:*8*1 D;A Controller
3*:*8*) D;A Trans"er
3*:*9 Input/Output 0rocessor ,IO0-
3*:*9*1 C01/IO0 Communication
3*:*9*) I=; 370 IDO Channel
3*:*9*3 Intel :0:' IO0
3*:*7 Serial Communication
3*:*7*1 Character/Oriented 0rotocol
3*:*7*) Transmission ?@ample
3*:*7*3 Data Transparenc3
3*:*7*6 =it/Oriented 0rotocol
3*' ;emor3 Organization <*<
3*'*1 ;emor3 ierarch3
3*'*) ;ain ;emor3
3*'*)*1 $A; and $O; Chips
3*'*)*) ;emor3 Address ;ap
3*'*)*3 ;emor3 Connection to C01
3*'*3 Au@iliar3 ;emor3
3*'*3*1 ;agnetic Dis2s
3*'*3*) ;agnetic Tape
3*'*6 Associati%e ;emor3
3*'*6*1 ard+are Organization
3*'*6*) ;atch #ogic
3*'*6*3 $ead Operation
3*'*6*6 Arite Operation
3*'*8 Cache ;emor3
3*'*8*1 Associati%e ;apping
3*'*8*) Direct ;apping
3*'*8*3 Set/Associati%e ;apping
3*'*8*6 Ariting into Cache
3*'*8*8 Cache Initialization
-.0 Te)c.#+ Me".o*o/o+0
6*1 ;ethods to be used
The primar3 teaching methods +ill be lecture( in/class demonstrations( and lab
assignments*
6*) Student role in the course
The student +ill attend lectures and demonstration( participate in discussion on assigned
readings( complete assigned home+or2( and complete re5uired e@aminations
6*3 Contact hours
Three hours per +ee2
1.0 E')/u)"o#
8*1 T3pe o" student pro4ects that +ill be the basis "or e%aluating student per"ormance(
speci"3ing distinction bet+een undergraduate and graduate( i" applicable* !or #aborator3
pro4ects( speci"3 the number o" +ee2s spent on each pro4ect-*
Students +ill complete a se5uence o" "our assembl3 language assignments* Students +ill
participate in the design simulation o" a simple AC/ based C01* This is in addition to
three e@aminations*
8*) =asis "or determining the "inal grade ,Course re5uirements and grading standards-
speci"3ing distinction bet+een undergraduate and graduate( i" applicable*
Component >rading
?@ams :0E
ome+or2D #ab Assignments 18E
0articipation 8E
8*3 >rading scale and criteria*
Points Grade
'7/100E AF
'3/'9E A
'0/')E AG
:7/:'E =F
:3/:9E =
:0/:)E =G
77/7'E CF
73/79E C
70/7)E CG
97/9'E DF
93/99E D
90/9)E DG
0/8'E !
2.0 Resource M)"er)/
9*1 Te@tboo2s andDor other re5uired readings used in course
;* ;ano( Computer System Architecture( 3rd ?dition, 0rentice all( 1''3*
9*) Other suggested reading materials( i" an3
None
9*3 Other sources o" in"ormation
None
9*6 Current bibliograph3 o" resource "or studentHs in"ormation
6.4.1 Ailliam Stallings( Computer Organization and Architecture: Designing or
Perormance, 9th edition( 0rentice all( )003*
6.4.! $andal ?* =r3ant( Da%id $* OIallaron( Computer Systems: A Programmer"s
Perspecti#e( 0rentice all( )003
6.4.$ >* 7aram and &* =r3ant( Princip%es o Computer Systems( 0rentice all( 1'')*
6.4.4 &* Carpinelli( Computer Systems Organization and Architecture( Addison/Aesle3(
)001*
6.4.& C* amacher( B* Cranesic and S* Ba23( Computer Organization( 6th edition(
;c>ra+/ill( 1''9*
6.4.6 C* euring and * &ordan( Computer System Design and Architecture( Addison/
Aesle3( 1''7*
6.4.' 0* Abel( ()* PC Assem+%y ,anguage and Programming( 0rentice all( 1''8*
6.4.- &* a3es( Computer Architecture and Organization 3rd edition( ;c>ra+/ill(
1'':*
6.4.. ;* ;urdocca and C* euring( Princip%es o Computer Architecture( 0rentice all(
)000*
6.4.1/ &* enness3 and D* 0atterson( Computer Architecture: A 0uantitati#e Approach(
)nd edition( ;organ 7au"mann( 1''9*
6.4.11 &* enness3 and D* 0atterson( Computer Organization and Design: 1he
2ard3are4Sot3are (nterace( )nd edition( ;organ 7au"mann( 1'':*
6.4.1! ;* ;ano( Computer System Architecture( 3rd ?dition, 0rentice all( 1''3*
6.4.1$ A* Stallings( Computer Organization and Architecture, &th 5dition( 0rentice all(
)000
6.4.14 Andre+ S* Tanenbaum( Structured Computer Organization( 6th edition( 0rentice
all( 1'''*
6.4.1& &ames ?%ans( (tanium Architecture or Programmers: 6nderstanding 647)it
Processors and 5P(C Princip%es( 0rentice all )003*
3.0 Co4!u"#+ Sce#ce Accre*")"o# Bo)r* C)"e+or0 Co#"e#" 5c/)ss "4e # .ours6
CSA) Category Core Ad#anced
Data Structures
Computer Organization and Architecture 38
Algorithm and So"t+are Design 3
Concepts o" 0rogramming #anguages 3
7.0 Or)/ )#* 8r""e# Co44u#c)"o#s
?%er3 student is re5uired to submit at least JJ0JJJ +ritten reports ,not including e@ams( tests(
5uizzes( or commented programs- to t3picall3 JJJJJ pages and to ma2e JJJ0JJ oral
presentations o" t3picall3 JJJJJ minutes duration* Include onl3 material that is graded "or
grammar( spelling( st3le( and so "orth( as +ell as "or technical content( completeness( and
accurac3*
9.0 Soc)/ )#* E".c)/ Issues
No co%erage
10.0 T.eore"c)/ co#"e#"
The course is considers theoretical aspects o" =oolean algebra( and "inite state machine design
and minimization*
11.0 Pro%/e4 )#)/0ss
The course is an introduction to computer architecture* As a result( design problems "rom
$egister Trans"er #anguages are anal3zed* The designed solutions are considered in the anal3sis
aspect o" the design*
1$.0 So/u"o# *es+#
The solution design includes translating the +ord problem into a "ormal description in the
conte@t o" state machines( AS; charts( and microoperations realization*
CHAN:E HISTORY
Date Change By whom Comments
09D1'D)003 Initial A=?T %ersion !arhat
09D1'D)003 Cleanup Aileman