3 AdvancedAmplifiers&ComparatorsDesign 12 13x2

4/6/13 Analog Integrated Systems jrf@ist.utl.
pt 1
!"#$%& (")*&+#)*, -./)*0/
S. Auvanceu Amplifieis anu Compaiatois Besign (4 sessions)
2-stage OPAMP. Design Perspective

#2
1-stage OPAMPs. Cascode or Telescopic topology. Folded Cascode.
Design Perspective. 2-stage symmetrical OPAMP
#3
Amplifiers and Feedback. OPAMP and OTA amplifiers.
Differential pair with active load. Design perspective.
#1
Ideal Comparator. Specifications. Clocked comparators switched-
capacitors. Comparators using positive feedback stages (latches).
Input test setup.
#4
(,*#$ 12*+#)3%"#$ !02$343*+
15!65
Iueal 0PANP has foi any
voltage:
- Infinite open-loop gain;
- Infinite banuwiuth;
- Infinite input impeuance
(Zeio input cuiient);
- Zeio offset voltage anu cuiient;
- Zeio output impeuance;
- Infinite slew-iate;
- Zeio noise.
4/6/13 Analog Integrated Systems jrf@ist.utl.pt 2
15!65 !"# 17!
+
-
v
2
v
O
v
1
Z
Load
C ?
R
o
v
in
G
m
v
in
R ?
R
o
+
-
v
in
A
v
v
in
!
L0AB
!low ! 0PANP
!
L0AB
! ! 0TA
-)#83$3).9 :#",;3,)<9 5<#/* 6#+&3"
=*/3&" 5*+/2*>)3?*
( ) ( )
( )
( ) 1 ( )
1
( ) 1 ( )
( ) 1 ( ) ( )
f
f
f
Y s A s
A s
X s A s
A s A s
A s A s A s
!
!
!
!
= =
+
"
# $
%
#
&
%
# $
'
!
"
log |gain| [dB]
A(s)
1/!
A
f
(s)
log f
-3dB
-20 dB/dec
-6 dB/oct
BW
0.1BW
10 BW
Phase
-90
GBW
-)#83$3).9 :#",;3,)<9 5<#/* 6#+&3"
=*/3&" 5*+/2*>)3?*
-)#83$3).9 :#",;3,)<9 5<#/* 6#+&3"
=*/3&" 5*+/2*>)3?*
1
PM=5
1
PM=45
1
PM=60
11.5
( )
1.3
( )
1
( )
f
f
f
A j
A j
A j
!
"
!
"
!
"
#
#
=
Bow much phase maigin is
neeueu.
log |A
f
| [dB]
1/!
log f
log |A
f
| [dB]
1/!
log f
y(t)
log f
y(t)
log f
15!65 -)+@>)@+*
K=1 -K
2
+
-
C
g
m
Single-stage
- Simple ciicuit; lowei gain; fast
Two-stage: (most common) 2 gain stages with oi without
buffeis
- Bigh gain pei stage
- Compensation is simple (ieuuce numbei of poles)

Thiee (oi moie) gain stages
- Baiu to uesign: uifficult to compensate
A-3"&$*B/)#&*C =3DD*+*")3#$ 5#3+ ;3)< !>)3?* E%#,
-0#$$ /3&"#$
MM
2
!
v
d
DD
V
M
1
I
SS
-V
SS
V
GS
v
d
2
V
GS
v
d
2
+
I
SS
2
v
d
2
+g
m
I
SS
2
v
d
2
-g
m
v
d
-g
m
M
3
M
4
A-3"&$*B/)#&*C =3DD*+*")3#$ 5#3+ ;3)< !>)3?* E%#,
-0#$$ /3&"#$
1 2 1 2
2
1 2
4
Transconductance
Differential input resist
short circuit output and
ance

Output Resistanc
0
2 2
/ /
can be obtained from small signal an
e
al
d d
o D D m m m d
i
m m m
G
o o
t
d
o
S
v v
i i i g g g v
R
R r
I
g g g
V
r
V
! "
# $
= % = % % =
& '
( )
=
= = =
%
= *
( )
( )
( ) ( )
4 2 4 2
ysis
asymmetric circuit: complete half-mode circuit cannot be
Voltage gain
used
/ /

2 1
2
o
A
GS
d m o o
t GS t
o
V I
V V I V V
r A g r r r
!
=
% %
= = =
v
d
v g
m1 d
r
o2
v
out
//r
o4
A-3"&$*B/)#&*C =3DD*+*")3#$ 5#3+ ;3)< !>)3?* E%#,
=."#03> +*/2%"/*
v
d
v g
m1 d
r
o2
v
out
//r
o4
C
( )
1 Load 1
1
2 4 1
n
each pole depends on all capacitances
output node has high impedance and large capacit
1
dominant pole ;
Voltage gai
( )
( )
( )
ance
/
n
1
1
//
o o
d
o
o m o o
o
C
V s A
A s
V s s
A g r
C C
R C
r
R C
!
!
!
"
= =
+
= =
= = +
MM
2
v
d
DD
V
M
1
M
3
M
4
! I
SS
-V
SS
C
Load
1
2
3
A-3"&$*B/)#&*C =3DD*+*")3#$ 5#3+ ;3)< !>)3?* E%#,
=."#03> +*/2%"/*
1
Gain-bandwidth product Slew-rate
GBW
SR
m o
o o o
max
o
max
g dv
A i C i I
C dt
dv I
dt C
! = = = =
= =
v
d
v g
m1 d
r
o2
v
out
//r
o4
C
-3"&$*B/)#&* F61- 17! =*/3&"
("2@) F%00%"B0%,*9 1@)2@)
MM
2
v
d
DD
V
M
1
M
3
M
4
! I
SS
-V
SS
C
Load
1
2
3
1 ,
1
1 3
Input common mode (min)
Input common mode (max)
Out
Consider all 0.2V
Current source in "Saturation"
2
in saturati
put common
on
m

GS t
INC GS OVD ISS OVD t
D INC t DD OVD t INC t INC DD OVD
V V
V V V V V
M
V V V V V V V V V V V
! "
= + " +
> ! # ! ! > ! # < !
2
2 2
4
4 4
and Current source in "Saturation"
in saturation
ode (min)
Output common mode )

(max
OUTC INC GS OVD OUTC INC t
D DD OVD t OUTC DD OVD
M
V V V V V V V
M
V V V V V V
> ! + # > !
< ! # < !
2V
OVD
+V
t
Depend on
V
INC
: -V
t
2V
OVD
V
OVD
V
OVD
V
INC
V
OUTC
V
DD
V
SS
v
pp
v
pp
-3"&$*B/)#&* F61- 17! =*/3&"
6#G30@0 H:I
MM
2
v
d
DD
V
M
1
M
3
M
4
!
I
SS
-V
SS
C
Load
1
2
3
1 Max
1
1
1
GBW GBW
. . 0.2V 1A 1pF GBW 1MHz ( 800kHz)
GBW
Most simple FoM for amplifiers: F
Gain-bandwidth product
(2 )
oM= 1000 MHz pF/mA
m SS
o
GS t
GS t SS
SS
g I
A
C V V C
e g V V I C
C
I
!
"
= = # =
$
$ % = = & %
'
%
!
-3"&$*B/)#&* F61- 17! =*/3&"
J", 2%$* K 5<#/* 6#+&3"
MM
2
v
d
DD
V
M
1
M
3
M
4
!
I
SS
-V
SS
C
Load
1
2
3
( )
1
Load 1
3
nd
2
3
2 nd
nd
Dominant Pole GBW
2
Non-dominant pole f
2
2 2 4 f Dominant pole
4
Furthermore it creates a zero at 2 f , making its influence even more neg
Gain-bandwidth pro
l
duct
m
n
m
n
t
n GS DB GS
g
C C
g
C
f
C C C C
!
!
" =
+
" =
# + # " #
$
!
igible.
-3"&$*B/)#&* F61- 17! =*/3&"
=*/3&" #22+%#><
Load 1
min
1) Define DC
Verify other specs: SR.
Assume ; . . 200mV Calculate W/L
Verify other specs: Common mode input, Outp
2) GBW and calc
ut amplitude.
4) Assume L=3 L C
ulate
alcu
,
3)
late
GS
S
OV
S
t
m
D
C g I
V V V e g ! = "
# "
"
nd
W.
5) Confirm f is far from first pole ? No: make the transistors smaller, iterate.
Verify other specs: offset, noise.
MM
2
v
d
DD
V
M
1
M
3
M
4
! I
SS
-V
SS
C
Load
1
2
3
!"#$%& (")*&+#)*, -./)*0/

#2
#3
#1
Input test setup.
#4
7;%B/)#&* F61- 17! =*/3&"

I
Ref
V
DD
M
5
M
8
M
7
M
3
M
2
M
1
M
4
M
6
v
in-
v
in+
v
out
C
C
C
Load
1
2
3
4
5
7;%B/)#&* F61- 17! =*/3&"

( ) ( )
1 2 4 6 6 7
6 7
Voltage Gain
Input Resist
/ / / /
/
ance
Output Resistance
/
d m o o m o o
id
o o o
A g r r g r r
R
R r r
= !
= "
=
v
d
v g
m1 d
r
o2
//r
o4
C
n1
v g
m6 1
r
o6
v
out
//r
o7
C
Load
+C
n4
1
v
C
C
1,2
1) estimate from gain and noise
m
g !
7;%B/)#&* F61- 17! =*/3&"

( ) ( )
1
2 4 6 6 7
1
0 1
1 1
Frequency response (Miller effect)
Dominant Pole: (gain bandwidth p
1
/ / / /
G roduct BW
1 1
GB
)
W
2 2 GBW
p
o o C m o o
m
p
C
m m
C
C
r r C g r r
g
A
C
g g
C
C
!
!
" "
#
= =
= $ =
!
1,2
2) estimate from GBW and
C m
C g !
v
d
v g
m1 d
r
o2
//r
o4
C
n1
v g
m6 1
r
o6
v
out
//r
o7
C
Load
+C
n4
1
v
C
C
7;%B/)#&* F61- 17! =*/3&"

5
7
Load
1: SR
Slew rate (at the two no
4:
des)
SR
D
C
D
C
I
C
I
C C +
!
!
5 7
1,2
3) estimate and
4) estimate
D D
I I
W
L
! "
# $
% &
v
d
v g
m1 d
r
o2
//r
o4
C
n1
v g
m6 1
r
o6
v
out
//r
o7
C
Load
+C
n4
1
v
C
C
7;%B/)#&* F61- 17! =*/3&"

6 6
Load 1
GBW
PM 90
1
for 60 2
Phase Mar
2
typical values: 2 to
g n

i
3
nd
m m Load
nd
m C
Load C
arctg
f
g g C
f
C g C
C C
!
= "
= # $
# = % %
!
6 7
6
5) calculate and with estimate
m D
W
g I
L
! "
# $
% &
7;%B/)#&* F61- 17! =*/3&"

( )
6
6
6
1 6 1
1 6 1
1
1
( ) 0 ( ) ( )
0, same order of magnitude as GBW reduces stability
possible solution:
1 1
( ) 0 ( ) ( )
1/
it can be or 0
Zero:
m
m
m
o C m z
C
z
C
o m z
C
C
z
g
V s sC V s g V s s
C
s
R C
V s V s g V s s
R sC
C g R
R g s
!
!
= " = " =
> "
" +
= " = " =
+
!
# " = $ <
v
d
v g
m1 d
r
o2
//r
o4
C
n1
v g
m6 1
r
o6
v
out
//r
o7
C
Load
+C
n2
1
v
C
C
R
6
1
6) calculate
m
R
g
=
7;%B/)#&* F61- 17! =*/3&"

I
Ref
V
DD
M
5
M
8
M
7
M
3
M
2
M
1
M
4
M
6
v
in-
v
in+
v
out
C
C
C
Load
1
2
3
4
5
1 2 3 4
5
3 4
3 3 4 4
6
6 4 6 4
4
7
5 7 7 5
5
5
4 7 6
5 4
6 7
7) Biasing and
common mode voltages
;
2
1
2
2
D
D D
GS DS GS DS
GS GS D D
SG SG D D
D
D
D D
M M M M
I
I I
V V V V
k
V V I I
k
k
V V I I
k
I
I k k
k k
I I
= =
= =
! = = =
"
= ! =
#
#
$
#
= ! =
#
%
"
=
#
! =
$
#
=
%
!"#$%& (")*&+#)*, -./)*0/

#2
#3
#1
Input test setup.
#4
F#/>%,* %+ 7*$*/>%23> 17!
LB/)#&* #02$343*+
V
DD
M
9
M
7
M
8
v
out
M
2
M
1
v
in-
v
in+
V
BIAS
V
DD
M
9
M
7
M
8
v
out
M
2
M
1
v
in-
v
in+
V
BIAS
M
4
M
3
M
5
M
6
V
BIAS 2
F#/>%,* %+ 7*$*/>%23> 17!
LB/)#&* #02$343*+
V
DD
M
9
M
7
M
8
v
out
M
2
M
1
v
in-
v
in+
V
BIAS
M
4
M
3
M
5
M
6
V
BIAS2
( ) ( )
( ) ( )
1 2
4 4 2 6 6 8
4 4 2 6 6 8
4
Transconductance
Input resistance
Output resistance
Voltage ga
High gain:~10
Common mode voltages:
5 stacked transistors
/ /
in
/ /
m m m
GS T
id
o m o o m o o
d m m o o m o o
I
g g g
V V
R
R g r r g r r
A g g r r g r r
= = =
!
= "
=
=
#
$ %
& '
log |gain| [dB]

log f
-3dB
BW GBW
10
2
10
2
-3dB
BW
M%$,*, F#/>%,* 17!
LB/)#&* #02$343*+
It has twice the cuiient.
11
1,2
5,6,7,8
9,10
11 7 8
Biasing
2
2
Total Current: 2
I I
I
I
I
I
I I
I I I I
=
=
=
=
+ + =
M
9
M
10
M
3
M
4
V
BIAS 2
V
BIAS3
M
8
M
7
M
6
M
5
V
DD
v
out
V
DD
M
11
V
BIAS
M
1
v
in-
v
in+
M
2
1 2
3
4
5
6 7
M%$,*, F#/>%,* 17!
LB/)#&* #02$343*+
( ) ( )
( ) ( )
1 2
4 4 2 10 6 6 8
1 4 4 2 10
4
6 6 8
( / /
High gain:~10
Commo
Transconductance
Input resistance
Output resistance
Volt
n mode volta
) / /
( / / ) / /
age gai
ges:
4 sta k d
n
c e
m m m
GS T
id
o m o o o m o o
d m m o o o m o o
I
g g g
V V
R
R g r r r g r r
A g g r r r g r r
= = =
!
= "
=
= # $
% &
' transistors
M
9
M
10
M
3
M
4
V
BIAS 2
V
BIAS3
M
8
M
7
M
6
M
5
V
DD
v
out
V
DD
M
11
V
BIAS
M
1
v
in-
v
in+
M
2
!" $%& &'(')%*)+ "$, &%(, -%'./
"0'1, "$, 12**,."3
%45%."%-,&6
M%$,*, F#/>%,* 17!
LB/)#&* #02$343*+
M
9
M
10
M
3
M
4
V
BIAS 2
V
BIAS3
M
8
M
7
M
6
M
5
V
DD
v
out
V
DD
M
11
V
BIAS
M
1
v
in-
v
in+
M
2
1 2
3
4
5
6 7
1
Load
3
nd
1
1 3 2 9
3
nd
Dominant Pole GBW
2
Non-dominant pole f
2
3
f Dominant pole
3
It can have a high G
Gain-bandwidth pro u
B
d ct
W.
m
m
n
n GS DB DB GS
t
g
C
g
C
C C C C C
f
!
!
" =
" =
# + + #
" # !
M%$,*, F#/>%,* 17!
LB/)#&* #02$343*+
M
9
M
10
M
3
M
4
V
BIAS 2
V
BIAS3
M
8
M
7
M
6
M
5
V
DD
v
out
V
DD
M
11
V
BIAS
M
1
v
in-
v
in+
M
2
1 2
3
4
5
6 7 10,4
6,8
Output common mode (min)
Output c
Consider all 0.2V
Saturation
2 (Independent of )
in saturation
ommon mode (max)
Input common mode (mi
(Independent
n)
of )
Curre
GS t
OUTC OVD INC
OUTC DD GS OVD INC
V V
M
V V V
M
V V V V V
! "
>
< ! !
1
In
nt
put
source
common
in "Saturat
mode (max
ion"
(can go below gnd)
in saturation
2
)
INC OVD t
INC DD OVD t
V V V
M
V V V V
> !
< ! !
7;%B/)#&* F61- 17! =*/3&"
-.00*)+3>#$
V
DD
M
9
M
7
M
8
M
2
M
1
M
6
v
in-
v
in+
v
out
C
Load
1 2
3
4
5
M
3
M
4
M
5

V
BIAS
3 4
5 6
7 8
5
3
1
6 8
;
/ / ;
m m
o o o
o m o
M M
M M
M M
W
L
h
W
L
G h g
R r r
A G R
=
=
=
! "
# $
% &
=
! "
# $
% &
=
=
=
7;%B/)#&* F61- 17! =*/3&"
-.00*)+3>#$
( )
( )
6,8
1 6 8
1
6 8 LOAD
1
LOAD
/ /
1 1
BW
2 / /
1
GBW
2
1
note:
E
o m o o
OVD
o o
m
E
V L
A g h r r
V
r r C
g
h
C
V L
!
!
"
= =
=
=
#
V
DD
M
9
M
7
M
8
M
2
M
1
M
6
v
in-
v
in+
v
out
C
Load
1 2
3
4
5
M
3
M
4
M
5

V
BIAS
7;%B/)#&* F61- 17! =*/3&"
-.00*)+3>#$
1 2
R
2C
1 2
R
C
1
LOAD
n1 4 4 2
4 4
n1
1
GBW
2
(1 ) (3 )
1
2 3
m
GS DB DB GS
m t
nd
g
h
C
C h C C C h C
g f
f
C h
!
!
=
= + + + " +
= "
+
V
DD
M
9
M
7
M
8
M
2
M
1
M
6
v
in-
v
in+
v
out
C
Load
1 2
3
4
5
M
3
M
4
M
5

V
BIAS
7;%B/)#&* F61- 17!
(NNN F3+>@3)/ #", -./)*0/ 6#&#O3"* MPJQLL
!"#$%& (")*&+#)*, -./)*0/

#2
#3
#1
Input test setup.
#4
(,*#$ F%02#+#)%+
+
-
V
DD
V
REF
v
I
v
O
V
DD
v
O
V
DD
v
I
V
REF
Bighly non-lineai ciicuit! (it can be lineaiizeu in ceitain stuuies)
Amplifiei with infinite gain: Continous time oi clockeu (SC)
0sing a positive feeuback latch: Compaies only in specifieu instants.
Impoitant Specs:
low offset anu high iesolution (non iueal tiansition iegion)
speeu of uecision (uefines opeiating fiequency, uepenus on input
value if clockeu ); Slew-iate limitations
F%")3"%@/ 730*
F%")3"%@/ )30* <3&< &#3" #02$343*+
f
p
A
V
[dB]
A
0
F[Hz]
V
DD
v
O
V
DD
v
I
V
REF
Defines resolution
offset
+
-
V
DD
V
REF
v
I
v
O
A
V
Resolution limitations anu offset:
Bigh gain allows high iesolution:
6uuB-#
$$
1uuu~Smv same oiuei of offset
(N0S), no neeu foi moie gain.
Speeu limitations: banuwiuth anu slew-iate
open-loop time constant: 1(2%
&
) ~ (s)
uepenuing on phase maigin; it neeus
seveial time constants to settle
slew-iate: IC ! ~ (ApF~s)

F$%>R*, F%02#+#)%+ AF%")3"@%/ 730*C
@/3"& # 2%/3)3?* D**,8#>R S$#)><T
F$%>R*, F%02#+#)%+
@/3"& # 2%/3)3?* D**,8#>R S$#)><T
F$%>R*, F%02#+#)%+
@/3"& # 2%/3)3?* D**,8#>R S$#)><T
Ciicuit
implementation
F$%>R*, F%02#+#)%+
@/3"& # 2%/3)3?* D**,8#>R S$#)><T
V
DD
V
OUT-
V
OUT+
V
IN-
V
IN+
V
REF+
V
REF-
Latch
Latch
Bynamic Latcheu
Compaiatoi
- Fully uiffeiential
- Amplifieilatch
combineu
- Requiies anothei
latch stage to
achieve iail-to-iail
values
F$%>R*, F%02#+#)%+
@/3"& # 2%/3)3?* D**,8#>R S$#)><T
V
DD
V
OUT-
V
OUT+
V
IN-
V
IN+
V
REF+
V
REF-
W
1
W
1
W
2
W
2
Sample mode
Cgs Cgs Cgs Cgs
V
DD
V
OUT-
V
OUT+
V
IN-
V
IN+
V
REF+
V
REF-
W
1
W
1
W
2
W
2
Latch mode
Cgs Cgs Cgs Cgs
V
IN-
V
IN+
V
REF+
V
REF-
V
IN+
V
IN-
V
REF-
V
REF+
agnd agnd
F$%>R*, F%02#+#)%+
-;3)><*, F#2#>3)%+
+
-
V
REF
v
I
v
O
A
V
!
1
C
!
1
!
2
v
O
v
O
Comparison phase:
!
2
closed ; !
1
open
!
1
+
-
v
I
A
V
!
1
C
Reset phase:
!
1
closed ; !
2
open
+
-
V
REF
A
V
C
!
2
V
OS
V
OS
+ - + -
Foi offset cancellation - SC
( )
( )
Reset phase:
Comparison phase:
( ) ( )
"1" if

"0" if
o OS
C I OS
C I OS
C REF C REF I OS
o v C OS v I REF
o I REF
o I REF
v V
v v V
v v V
v V v V v V
v A v V A v V
v v V
v v V
!
!
= "
#
= !
$
= ! "
%
= ! = ! +
#
%
= ! + = !
$
& > "
'
#
& <
$
Non-overlapped clocks
("2@) /3&"#$
Test setup
anu metastability
U*&*"*+#)3?* F%02#+#)%+
A-><03)) )+3&&*+C
v
I
v
X
v
I
v
O
v
O V
SAT+
V
SAT-
+
-
R
2
R
1
-(R
1
/R
2
)V
SAT+
-(R
1
/R
2
)V
SAT-
Inveiting
Non-inveiting
v
I
v
X
v
O
+
-
R
2
R
1
v
I
v
O
V
SAT+
V
SAT-
!V
SAT+
v
I
v
O
V
SAT+
V
SAT-
!V
SAT-
v
I
v
O
1
1 2
X O
v v
R
R R
!
!
=
=
+
2 1
1 2 1 2
X I O
R R
v v v
R R R R
= +
+ +

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3 AdvancedAmplifiers&amp;ComparatorsDesign 12 13x2

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3 AdvancedAmplifiers&amp;ComparatorsDesign 12 13x2

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Available Formats

4/6/13 Analog Integrated Systems jrf@ist.utl.

log |gain| [dB]

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3 AdvancedAmplifiers&ComparatorsDesign 12 13x2

3 AdvancedAmplifiers&ComparatorsDesign 12 13x2