I HC QUC GIA TP.

H CH MINH
TRNG I HC BCH KHOA
KHOA IN-IN T
B MN K THUT IN T
11
CHNG 3
H VI IU KHIN 8051
3.4 Timer
(Mch nh thi)
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Ni dung
1) Gii thiu
2) Cc thanh ghi c chc nng c bit (SFR)
3) Cc ch hot ng ca timer
4) Cc ngun to xung nhp
5) iu khin cc timer
6) Khi to tr v truy cp cc thanh ghi timer
7) Cc v d
8) Lp trnh counter
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1) Gii thiu v timer
Timer l mt chui cc flip-flop chia i tn s mc ni tip vi
nhau, chng nhn tn hiu vo lm ngun xung nhp. Xung nhp
c a vo flip-flop th nht chia i tn s xung nhp.
Ng ra ca flip-flop th nht lm xung nhp cho flip-flop th hai
(cng lm vic chia i tn s),v v.v...
V mi tng k tip chia i cho nn timer c n tng s cho xung
ra c tn s l tn s xung nhp chia cho 2
n
. Ng ra ca tng cui
lm xung nhp cho flip-flop bo trn ca timer (cn gi l c
timer TF [Timer Flag]).
Gi tr nh phn trong cc flip-flop ca timer c th xem nh s
m s xung nhp (hoc cc s kin) t khi timer bt u chy.
Th d timer 16 bit s m ln t 0000H n FFFFH. C bo trn
s ln 1 khi s m trn t FFFFH n 0000H.
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TD: Timer 3 bit
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Timer trong 8051
8051/8031 c hai timer 16 bit (T0 v T1), mi timer c bn ch
hot ng.
Ngi ta s dng cc timer :
a) nh khong thi gian,
b) m s kin hoc
c) to tc baud cho cng ni tip c sn trong 8051/8031.
Mi timer 16 bit c 16 tng hay tng cui cng chia tn s xung
nhp cho 2
16
=65536. Ngun xung nhp cho cc timer l xung
vung c tn s bng 1/12 tn s xung nhp cung cp cho 8051.
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Trong cc ng dng nh khong thi gian, ngi ta lp trnh cho
timer trn mt khong u n v t c trn timer ln 1. C
c dng ng b ha hoc o thi gian tri qua gia hai s
kin (v d: o rng xung).
m s kin c dng xc nh s ln xy ra ca mt s
kin hn l o khong thi gian tri qua gia cc s kin. Mt
s kin l bt c tc ng bn ngoi no c th cung cp mt
chuyn tip 1 sang 0 t chn T0, T1( P3) ca 8051/8031.
Cc timer cng c th cung cp xung nhp tc baud cho cng
ni tip c sn trong 8051/8031.
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2) Cc SFR ca timer
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2) Cc thanh ghi timer
Timer (T0/T1) ca 8051 c to bi 2 thanh ghi 8
bit.
Timer 0 (T0) c to bi
TL0 vTH0 (L=Low v H=High)
Truy cp chng nh cc thanh ghi khc, TD:
MOV TL0, #55H
MOV R1, TH0
Timer 1 (T1) c to bi
TL1 and TH1
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a) Thanh ghi iu khin timer (TCON)
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b) Thanh ghi ch timer (TMOD)
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3) Cc ch timer v c bo trn
Mode 3 : two 8-bit counter
the other counter will not
output overflow (interrupt)
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Bn ch hot ng
Mode 0 : 13-bit counter
(4048 mode)
Mode 1 : 16-bit counter
Mode 2 : 8-bit auto reload counter
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a) Ch timer 13 bit (Ch 0)
Ch 0 l ch timer 13 bit tng thch vi b x l
trc 8051 l 8048
Vi cc thit k mi ngi ta t dng ch hot ng ny
Byte cao ca timer (THx) ni tip vi 5 bit thp ca byte
thp ca timer (TLx) to thnh timer 13 bit
Ba bit cao ca TLx khng c s dng
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b) Ch timer 16 bit (ch 1)
Ch 1 l ch timer 16 bit ging nh ch
0, ngoi tr lc ny timer hot ng nh timer 16
bit y .
Trn xy ra khi c chuyn tip t FFFFH sang
0000H trong s m v n t c bo trn timer
ln 1. Timer tip tc m tip.
C bo trn l bit TFx trong TCON m ngi ta c
th c ra hoc ghi vo bng phn mm
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c) Ch timer 8 bit t np li tr u (ch 2)
Ch 2 l ch t ng np gi tr u. Byte thp ca timer TLx
lm vic nh timer 8 bit trong khi byte cao ca timer THx gi gi
tr cn np li.
Khi b m trn t FFH sang 00H th khng nhng c timer c t
ln 1 m gi tr trong THx cn c np vo TLx, vic m tip tc t
gi tr ny n chuyn tip t FFH sang 00H k, v c tip tc nh vy.
Ch ny tin li v trn timer xy ra theo nhng khong thi gian
c chu kz mt khi TMOD v THx c khi to tr
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d) Ch tch timer (ch 3)
Ch 3 l ch tch timer th khc nhau vi mi
timer. Timer 0 ch 3 c tch thnh 2 timer 8
bit.
TL0 v TH0 lm vic nh 2 timer c lp vi cc bo
trn t cc c TF0 v TF1 tng ng.
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c im ca ch 3
Timer 1 b dng ch 3, nhng c th cho n chy bng
cch chuyn sang 1 trong cc ch khc.
Gii hn duy nht l c bo trn thng thng ca Timer 1
(TF1) khng b nh hng bi s bo trn trong Timer1 v
TF1 c ni vo TH0.
Ch 3 ch yu cho thm 1 timer 8 bit (8051 ging nh c
thm timer th ba). Khi Timer 0 ch 3, ta c th bt hay
tt Timer 1 bng cch chuyn n ra khi hay i vo chnh ch
3 ca n. N vn c th c cng ni tip s dng lm
b to tc baud hoc c th c s dng theo bt c
cch no m khng cn ngt (v n khng cn tc ng c
vi TF1).
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4) Cc ngun to xung nhp
C 2 ngun xung nhp, m ta c th chn bng cch
ghi vo bit chn b m/timer trong TMOD khi to cc
tr khi ng timer.
Mt ngun xung nhp c dng nh th khong
thi gian, cn ngun kia m s kin.
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nh th khong thi gian
Nu = 0, hot ng timer lin tc c chn v timer c
cp xung nhp t mch dao ng trn chip. Mt tng chia 12
c thm vo gim tn s xung nhp xung gi tr thch hp
cho phn ln cc ng dng trong iu khin.
Khi chn hot ng timer lin tc th timer c s dng
nh th khong thi gian (interval timing). Cc thanh ghi timer
(TLx/THx) tng ni dung thm 1 c theo tn s l 1/12 tn s
dao ng trn chip; nh vy vi thch anh 12 MHz th xung nhp
ca timer l 1 MHz.
Trn timer xy ra c sau mt s cc xung nhp c nh m ty
theo gi tr u c np vo cc thanh ghi TLx/THx
C/T
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m s kin
Nu = 1, timer c cp xung nhp t ngun bn ngoi. Trong phn ln
cc ng dng, ngun bn ngoi ny cung cp timer mt xung khi xy ra s
kintimer c s dng m s kin (event counting). S s kin c
xc nh trong phn mm bng cch c cc thanh ghi TLx/THx, t gi tr
16 bit trong cc thanh ghi ny tng thm 1 cho mi s kin.
Ngun xung nhp bn ngoi c cung cp bng cch a vo cc chn c
chc nng thay th Port 3:ng vo xung nhp cho Timer 0 l T0 (chn P3.4)
hay cho timer l T1 (chn P3.5)
Trong cc ng dng b m, cc thanh ghi timer c tng thm 1 khi c
chuyn tip 1 sang 0 ng vo bn ngoi Tx. Ng vo bn ngoi ny c ly
mu trong S5P2 ca mi chu kz my; nh vy khi ng vo mc 1 trong 1 chu
kz v mc 0 trong chu kz k th s m c tng thm 1. Gi tr mi xut
hin trong cc thanh ghi timer trong S3P1 ca chu kz theo sau chu kz m
chuyn tip c pht hin. T n mt 2 chu kz my (2 s) ghi nhn
chuyn tip 1 sang 0, do tn s bn ngoi ti a l 500 KHz (gi s hot
ng 12 MHz)
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C/T
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5) Khi to tr v truy cp cc thanh ghi timer
Cc tc v:
t ch lm vic
Cho timer chy
Kim tra c trn
Dng timer
Xa c bo trn
c v cp nht cc thanh ghi timer
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t ch lm vic Cho timer chy Dng timer
TD:
t ch lm vic
MOV TMOD, #00010000B
timer 1: Gate=0, C/T=0, M1M0=01 (mode 1)
timer 0: Gate=0, C/T=0, M1M0=00 (mode 0)
Cho timer chy
SETB TR1
Dng timer
CLR TR1
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Kim tra c v truy cp cc thanh ghi timer
TD:
Kim tra c v xa c
WAIT: JNB TF1, WAIT
CLR TR1 ; dng timer T1
CLR TF1 ; xa c bo trn
Cp nht cc thanh ghi timer
MOV TL1, #9CH
MOV TH1, #0FFH
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c gi tr m ca timer ang chy
R7 TH1, R6 TL1
Trc ht c byte cao
Vn c th xy ra:
khi trn byte thp c li ln na
AGAIN: MOV A, TH1
MOV R6, TL1
CJNE A, TH1, AGAIN
MOV R7, A
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Cc bc lp trnh Timer mode 0 hay 1
1. Np tr cho TMOD
2. Np tr s cho cc thanh ghi TL v TH
3. Cho timer chy (SETB TR0 hay SETB TR1)
4. Kim tra/theo di c bo trn timer (TF)
i n khi c TF = 1
5. Dng timer (CLR TR0 hay CLR TR1)
6. Xa c TF
7. Quay v bc 2
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Cc bc lp trnh Timer mode 2
1. Np tr cho TMOD
2. Np tr s cho cc thanh ghi TH
3. Cho timer chy (SETB TR0 hay SETB TR1)
4. Kim tra/theo di c bo trn timer (TF) i
n khi c TF = 1
5. Dng timer (CLR TR0 hay CLR TR1)
6. Xa c TF
7. Quay v bc 3
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nh th khong thi gian ngn v khong thi gian di
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V d 1: To dng xung trn chn P1.0
Vit mt chng trnh to ra dng sng c chu kz trn P1.0 vi tn s cao nht c th
c. Tn s v chu kz nhim v ca dng sng ny l bao nhiu?
(gi s ta dng XTAL = 12MHz 1 MC = 1us)
Vi dng sng rt ngn: khng cn timer
ORG 8000H
LOOP: SETB P1.0 ; 1 MC
CLR P1.0 ; 1 MC
SJMP LOOP ; 2 MC
Tn s = 250 Khz (1/4 us)
T
ON
= 1 us, T
OFF
= 3us duty cycle = T
ON
/(T
ON
+T
OFF
)= 25% (1/4)
P1.0
1 us
(1 MC)
SETB CLR SJMP SETB
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V d 1: To sng vung trn chn P1.0
ORG 8000H
LOOP: SETB P1.0 ; 1 MC
NOP ; 1 MC
NOP ; 1 MC
CLR P1.0 ; 1 MC
SJMP LOOP ; 2 MC
Tn s = 166.7 Khz ( 1/ 6 us )
T
ON
= 3 us, T
OFF
= 3us duty cycle = T
ON
/(T
ON
+T
OFF
)= 50% (3/6)
P1.0
1 us
(One machine cycle)
NOP
SJMP
SETB NOP CLR SETB
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V d 2: To sng vung 10 KHz chn P1.0
To sng vung 10 KHz
Tn s = 10KHz chu kz T =1/10000 = 100 us
T
ON
= 50 us, T
OFF
= 50us
Dng mode 2 ( 8 bit mode ), v khong thi gian < 256 us.
ORG 8000H
MOV TMOD, #02H ; ch t np li 8 bit
MOV TH0, #-50 ; 256 50 = 206
SETB TR0 ; cho timer T0 chy
LOOP: JNB TF0, LOOP ; i timer T0 trn
CLR TF0 ; xa c bo trn
CPL P1.0 ; o bit cng
SJMP LOOP ; lp li
END
Timer 0 mode 2
Reload value = -50
Start Timer 0
Overflow?
(TF0=1?)
N
Y
Clear overflow flag
P1.0 NOT (P1.0)
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V d 3: To sng vung 1 KHz trn chn P1.0
To sng vung 1 KHz
Tn s = 1KHz chu kz T =1/1000 = 1000 us
TON = 500 us, TOFF= 500us
Dng mode 1 ( 16 bit mode ), v khong thi gian > 256 us.
ORG 8000H
MOV TMOD, #01H ; ch 1 (16 bit)
LOOP: MOV TH0, #0FEH
MOV TL0, #0CH ; -500 (-01F4H)
SETB TR0 ; cho timer T0 chy
WAIT: JNB TF0, WAIT ; i timer trn
CLR TR0 ; dng timer 0
CLR TF0 ; xa c bo trn
CPL P1.0 ; o bit cng
SJMP LOOP ; lp li
END
Ch : MOV TH0, #0FEH MOV TH0, #HIGH(-500)
MOV TL0, #0CH MOV TL0, #LOW(-500)
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TD: Giao tip buzzer (1/2)
Mt buzzer c ni vo chn P1.7 v mt cng tc khng ny
(debounce switch) c ni vo chn P1.6. Vit chng trnh c
mc logic do cng tc cp v to ra m thanh buzzer trong 1 giy
sau mi ln pht hin chuyn trng thi t 1 xung 0.
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TD: Giao tip buzzer (2/2)
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Lp trnh counter
ch counter: TMOD, TH, TL ging nh vi timer. Cc ch
timer cng ging
Tuy nhin thay v dng tn s thch anh, counter m xung t
bn ngoi a vo 8051 thng qua P3.4, P3.5
Bit C/T trong TMOD quyt nh ngun xung nhp.
Khi C/T = 1, counter m ln khi c xung a vo cc chn T1
v T0 ( P3)
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Hot ng Counter
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to Timer
Internal clock f
CLK
= f
Crystal
/ 12
External clock
C/T Clock Function
0 Internal Timer (interval timing, delay)
1 External Counter (event counting)
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Counter ch 1
C/T = 1
16-bit counter (TH0 and TL0)
TH0-TL0 c tng ln 1 khi TR0 = 1 v c 1 xung xut hin trn
T0
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Timer 0
external clock
input
(P3.4/T0)
TR0
TH0 TL0 TF0
TF0 goes high
when FFFF 0
Overflow
flag
C/T = 1
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V d 1: Counter BarLed
Mt nt nhn c kt ni vo chn P3.4 (T0). B qua hin tng rung khi n
nt nhn, vit chng trnh m s ln nhn nt nhn v hin th kt qu ln
bar led kt ni vo port 1
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V d 1: Counter BarLed
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ORG 0000H
MAIN:
MOV TMOD,#00000101B;Timer 0, 16 bit, external clock
;(counter operation)
;Gate=0, C/T=1, M1 M0 = 01
MOV TH0,#0
MOV TL0,#0
SETB TR0 ;Start Timer
LOOP: MOV A,TL0 ;Read Timer
MOV P1,A ;Display on Bar-LED
SJMP LOOP
END
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V d 2: Counter_7segLED
Mt nt nhn c kt ni vo chn P3.4 (T0). B qua hin
tng rung nt nhn, vit chng trnh m s ln nhn nt
nhn v hin th kt qu ln led 7 on anode chung kt ni vo
port 1
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V d 2: Counter_7segLED
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ORG 0000H
MAIN: MOV TMOD,#00000101B
MOV TH0,#0
MOV TL0,#0
SETB TR0
LOOP: MOV A,TL0
CJNE A,#10,NEXT
CLR A
MOV TL0,#0
NEXT: ACALL DISPLAY
SJMP LOOP
DISPLAY:
ACALL BCDTO7SEG
MOV P1,A
RET
BCDTO7SEG:
MOV DPTR,#TABLE
MOVC A,@A+DPTR
RET
TABLE: DB 40h,79h,24h,30h,19h
DB 12h,02h,78h,00h,10h
DONE: NOP
END
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Ch khi c dng ngt ngoi (TD: ch 1)
- Khi GATE = 1, timer c iu
khin bng /INTx
- Hu ch o rng xung
42 L Ch Thng
GATE=0
Internal control
The start and stop of the timer are controlled by the software
Ex: SETB TR1 ; Run Timer 1
CLR TR1 ; Stop Timer 1
GATE=1
External control
The hardware way of
starting and stopping
the timer by software
and an external source.
When GATE is set and TRx is set
(SETB TRx), Timer runs only while the INTx pin is high.
GATE=1
Timer
runs
Timer
stops
43 L Ch Thng
V d 3: Pulse_width_7segLED
Mt ngun xung c kt ni vo chn P3.2 (/INT0). Vit chng
trnh hin th rng xung theo n v us trn led 7 on anode
chung c kt ni vo port 1
44 L Ch Thng
V d 3: Pulse_width_7segLED
ORG 0000H
MOV TMOD,#00001001B
;Timer 0,16 bit,internal clock,GATE=1
MOV TH0,#0
MOV TL0,#0
SETB TR0
AGAIN: MOV A,TH0
CJNE A,TH0,AGAIN
MOV B,#4
DIV AB
;A=Pulse width in us/256/4
;approximate /1000
ACALL DISPLAY
SJMP AGAIN
DISPLAY:
ACALL BCDTO7SEG
MOV P1,A
RET
BCDTO7SEG:
MOV DPTR,#TABLE
MOVC A,@A+DPTR
RET
TABLE: DB 40h,79h,24h,30h,19h
DB 12h,02h,78h,00h,10h
DONE: NOP
END
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Ti liu tham kho
L Ch Thng
H Trung M, Vi x l{, Nh xut bn i hc Quc Gia
Tp. HCM - 2003
I. Scott MacKenzie , The 8051 Microcontroller, 2nd
Edition, Prentice-Hall, 1995
Slide bi ging thy H Trung M
Slide bi ging thy L Ch Thng.