Tm hiu phn mm tng tc ISE

Tm hiu ph$n m&m t'(ng tc ISE

1

Ch'(ng I: T)ng quan v& m ph+ng ISE (ISim)
ISE - Interative Software Engineering l ph$n m&m t'(ng tc cho php b,n th-c hi.n
phi/m hm v 01nh gi3 trong m ph+ng cho VHDL(- very-high speed integrated circuit
hardware description language - ngn ng5 m t7 ph$n c8ng m,ch t) h:p t;c 0< cao) v
Verilog, tr<n l=n cc ngn ng5 thi/t k/
- Xilinx ISE Simulator l ngn ng5 m t7 ph$n c8ng (Hardware Description Language
- HDL).
N m ph+ng kh7 n?ng th-c hi.n ch8c n?ng v m ph+ng th3i gian cho cc thi/t k/ VHDL
v Verilog. Ch8c n?ng cAa Test Bench Waveform Editor trong ISE Simulator cCng cho b,n
kh7 n?ng tao ra test benches cho VHDL v Verilog 0 kim tra gi tri c; 01nh bDng cch sE
dFng m<t giao di.n 0G hHa.
Khi mI Project Navigator, cc cEa s) sau 0y c sJn:
Waveform Editor window cEa s) bin tKp sng (sE dFng 0G th1)
Waveform Display window cEa s) hin th1 sng .
Hierarchy Browser window - CEa s) b< duy.t phn cLp.
Simulation Console window - CEa s) bn 0i&u khin m ph+ng.
- Mi tr'3ng lKp trnh ISE ny gGm c nh5ng ph$n chnh sau:
Vhpcomp (VHDL compiler- ng'3i bin tKp VHDL)
Vlogcomp (Verilog compiler- ng'3i bin tKp)
Fuse c$u ch (HDL chi ti/t v k/t n;i)
Simulation Executable th-c hi.n m ph+ng
isimgui - ISim Graphical User Interface (ISim sE dFng giao di.n 0G hHa)
+ Vhpcomp, vlogcomp :
Phn tch, bin tKp VHDL, Verilog nh5ng tKp tin nguGn t'(ng 8ng. M 0;i t':ng
0':c pht sinh bIi nh5ng ng'3i bin tKp 0':c sE dFng bIi (fuse- c$u ch) b< k/t n;i HDL 0
t,o ra m<t s- m ph+ng c th th-c hi.n.
+ Fuse (c$u ch):
L.nh fuse-c$u ch l chi ti/t ngn ng5 (HDL - m t7 Ph$n c8ng) v b< k/t n;i 0':c
dng bIi ISim. nh5ng hi.u 8ng fuse chi ti/t ha c; 01nh trn thi/t k/ t,o ra nh5ng 0(n v1 thi/t
k/ v sau 0 nh5ng 0(n v1 thi/t k/ 0':c bin tKp tMi m 0;i t':ng. Nh5ng tKp tin 0;i t':ng
thi/t k/ sau 0 0':c lin k/t cng nhau t,o ra m<t s- m ph+ng c th th-c hi.n.
Fuse c th lin k/t cc 0(n v1 thi/t k/ bin d1ch tr'Mc 0 vMi vhpcomp hoNc
vlogcomp. Ngoi ra, fuse c th t- 0<ng gHi vlogcomp v vhpcomp cho mOi VHDL hay
Verilog m nguGn li.t k trong m<t tKp tin d- n (. prj). Ph'(ng php ny cho php bin d1ch
nguGn "on-the-fly ".
+ Simulation Executable -Th-c thi m ph+ng:
Th-c thi m ph+ng 0':c t,o ra bIi l.nh fuse. P ch,y m ph+ng m<t thi/t k/ trong
ISim, s- m ph+ng 0':c t,o ra 0':c c$n c s- khIi 0<ng. khi ISim chay bn trong giao di.n
ISE Project Navigator , ISE lQm bQt s- ko theo 0 t,o ra m ph+ng. M<t ng'3i sE dFng
dng l.nh c$n ph7i r rng gHi m ph+ng t,o ra hi.u 8ng m ph+ng. Cc hi.u 8ng m ph+ng
0i&u khin s- ki.n 01nh h'Mng m ph+ng v hO tr: phong ph cho 01nh h'Mng v th?m d
m ph+ng bDng cch sE dFng Tcl

Tm hiu ph$n m&m t'(ng tc ISE

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Ch : S- M ph+ng ISE C th th-c hi.n mI r<ng m<t exe trong c7 linux l=n windows. Kiu
0Nt tn c d,ng mNc 01nh l X.exe
+ Isimgui.exe
isimgui.exe (isimgui on Linux) l h. giao di.n 0G ho, ISim. N bao gGm cEa s) hi.n
sng, nh5ng thanh cng cF, nh5ng b7ng, v thanh tr,ng thi. Trong cEa s) chnh, b,n c th
thLy r nh5ng ph$n m ph+ng thi/t k/ thm v xem tn hi.u trong cEa s) hi.n sng dng nh5ng
l.nh ISim 0 ch,y s- m ph+ng, kh7o st thi/t k/ v sEa lOi c$n thi/t
I/ Th vi!n M ph$ng:
- Cc th' vi.n thi/t b1 m ph+ng Xilinx 0':c bin d1ch sJn, v 0':c cKp nhKt t- 0<ng
khi cc
gi d1ch vF 0':c ci 0Nt. Khng c$n ph7i ch,y CompXlib 0 bin d1ch cc th' vi.n, hay ph7i
t7i xu;ng cKp nhKt nh5ng th' vi.n.
+ CompXlib compiling Simulation Libraries_ bin d1ch cc th' vi.n m
ph+ng Xilinx. N khng dng vMi ModelSim XE (Xilinx Edition) hoNc ISE Simulator. N chR
hO tr: vi.c lKp th' vi.n m ph+ng HDL Xilinx cho m ph+ng sau:
ModelSim SE (all Xilinx supported platforms) ModelSim SE (tLt c7 cc n&n
t7ng hO tr: Xilinx)
ModelSim PE (all Xilinx supported platforms) ModelSim PE (tLt c7 cc n&n
t7ng hO tr: Xilinx)
NCSIM (all Xilinx supported platforms) NCSIM (tLt c7 cc n&n t7ng hO tr:
Xilinx)
VCS-MX (only on Solaris and Linux based platforms) VCS-MX (chR trn
Solaris v Linux d-a trn n&n t7ng)
VCS-MXi (only on Solaris and Linux based platforms) VCS-MXi (chR trn
Solaris v Linux d-a trn n&n t7ng)
II/ Nh&ng ()c tnh v nh&ng s, gi-i h0n c1a ISE
B7ng I d'Mi cho ta thLy nh5ng 0Nc tnh quan trHng v nh5ng s- giMi h,n cAa ISE
3)c tnh H4 Tr6
Language Support ngn ng& h4 tr6
VHDL VHDL-93
Verilog Verilog-2001
SDF SDF3.0
Mixed VHDL/Verilog Yes
VHDL FLI No
Verilog PLI No
Operating System Support h. 0i&u hnh hO tr:
Windows 2000 PC my tnh
Win XP Pro 32bit
Linux Red Hat Enterprise Linux 3.0
Unix No
General t)ng quan
Incremental Compilation t?ng bin so,n Yes
Source Code Debugging- S- chRnh l m Yes
Tm hiu ph$n m&m t'(ng tc ISE

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nguGn
SDF annotation Yes
VCD generation Yes
Swift Interface (SmartModels) No

III/ H! (i7u hnh h4 tr6:
Ba h. 0i&u hnh m ISE hO tr::
Microsoft Windows


Red Hat
Linux, v SUSE Linux
Tm hiu ph$n m&m t'(ng tc ISE

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IV/ Cc h8 ki9n trc: ISE 11 hO tr: ba hH ki/n trc: Virtex, Spartan v CPLD.
Tm hiu ph$n m&m t'(ng tc ISE

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Ch'(ng II: H'Mng d=n sE dFng ISE 11
I/ Giao di!n Project Navigator:
- P':c chia ra lm 4 cEa s) chnh nh' hinh d'Mi
1.C:a s; Sources: (Sources Window)
- Hin th1 tn Project, b7ng nguGn v nh5ng ti li.u 0':c sE dFng v nh5ng tKp tin
nguGn thi/t k/ lin quan 0/n thi/t k/ 0':c l-a chHn.
2. c:a s; x: l: (Processes Window)
Add an Existing Source - Thm m<t NguGn
Hi.n h5u
Create New Source T,o nguGn mMi
View Design Summary Tm l':c thi/t k/
Design Entry Utilities Ti.n ch thi/t k/
User Constraints
Synthesis T)ng h:p
Implement Design Th-c hi.n thi/t k/
Tm hiu ph$n m&m t'(ng tc ISE

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Generate Programming File T,o file lKp trnh.
3. c:a s; tr0ng thi: (Transcript Window )
GGm 5 tab mNc 01nh: Console, Errors, Warnings, Tcl Console, Find in Files.
Console Bn di&u khin: hin th1 lOi, c7nh bo v thng bo thng tin.
LOi l dng thng bo mu 0+ (X) bn c,nh thng bo, trong khi nh5ng
c7nh bo dnh dLu (!) mu vng.
Warnings chR hin th1 c7nh bo. Nh5ng thng bo khc 0':c lHc ra tT
Console.
Errors chR hin th1 lOi. Nh5ng thng bo khc 0':c lHc ra tT Console.
Tcl Console bn 0i&u khin Tcl, L m<t bn 0i&u khin t'(ng tc vMi ng'3i
sE dFng. Trong vi.c thm trnh by nh5ng lOi, c7nh bo v thng tin. Bn 0i&u
khin Tcl cho php m<t ng'3i sE dFng g vo nh5ng l.nh Tcl 0Nc bi.t.
Find in Files hin th1 k/t qu7 trong ch8c n?ng tm ki/m Edit > Find in
Files.
II/ T0o m<t Project trong ISE Project Navigator
Th-c hi.n theo cc b'Mc sau 0 t,o m<t Project ISE bDng cch sE dFng New Project Wizard.
B1. khIi 0<ng ISE Project Navigator bDng cch nhLp 0p vo biu t':ng nh' hnh 1:





B2. NhLp vo nt New Project 0 khIi ch,y New Project Wizard.
HoNc vo file -> new Project. Hnh 2


Hnh 1
NhLp vo
0y!
Hnh 2
Tm hiu ph$n m&m t'(ng tc ISE

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B3. Cung cLp m<t tn v v1 tr l'u thch h:p cho project Hnh 3:








NhKp tn vo 0y
T,o 0'3ng d=n
Hnh 3
B4.Click next 0 ti/p tFc v chHn thi/t b1 v ngn ng5 nh' Hnh 4
Tm hiu ph$n m&m t'(ng tc ISE

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.



B7. Click Next 0 ti/p tFc v nhLn nt New source 0 t,o source rGi click next nh' Hnh 5
Hnh 4
Tm hiu ph$n m&m t'(ng tc ISE

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B8. ChHn kiu Source. U 0y chHn verilog Module v 0Nt tn cho module. Click next Hnh 6



B9. NhKp tn cho input v output, Click next nh' Hnh 7



Hnh 7
Hnh 6
Hnh 7
Tm hiu ph$n m&m t'(ng tc ISE

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B10. Kim tra l,i v click Finish. Hnh 8



B11. Ti/p tFc Click next Hnh 9


Hnh 8
Hnh 9
Tm hiu ph$n m&m t'(ng tc ISE

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B12. Kim tra l,i cc 0Nc tnh cAa Project vTa t,o. Click Finish

B13. CEa s) lm vi.c cAa ISE.


























3
1
2
4
Hnh 10
Hnh 11
Tm hiu ph$n m&m t'(ng tc ISE

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1. Toolbar thanh cng cF
2. Design panel - B7ng Thi/t k/
3.Workspace - Khng gian lm vi.c
4.Transcript window cEa s) tr,ng thi
B14.Sau khi hon thnh cc b'Mc t,o m<t Project mMi, trong cEa s) lm vic ta vi/t thm
code 0 hon thnh m<t module.




B15. Save v kim tra lOi:





















Click chHn Synthesize 0 kim
tra lOi
Hnh 13
Hnh 12
Tm hiu ph$n m&m t'(ng tc ISE

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III/ T0o test bench:
B1.ChHn Project/new Source


B2.ChHn Verilog Test Fixture

Hnh 14
Hnh 15
Tm hiu ph$n m&m t'(ng tc ISE

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B4.P'3ng d=n v tn test bench 0':c hin th1. Click Finish
B3. Test bench vi/t cho my_and nh' Hnh16 Click next
Hnh 16
Hnh 17
Tm hiu ph$n m&m t'(ng tc ISE

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B5. Thm code 0 hon thnh m<t test bench Hnh 18
Hnh 18
B6.ChHn Create Timing Constraints
Hnh 19
Tm hiu ph$n m&m t'(ng tc ISE

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Click Yes
Click OK
Click double
Hnh 20
Tm hiu ph$n m&m t'(ng tc ISE

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B7. chHn add-all nh' Hnh 21 rGi click OK

B8. Save v chHn l,i tab Design

Add - all
Hnh 21
Tm hiu ph$n m&m t'(ng tc ISE

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B9. Trong Source For chHn Behaviroral Simulation rGi chHn Behavioral Check Syntax.
Hnh 23

























B10. Sau 0 ta chHn Simulate Behavioral Model 0 mI cEa s) hi.n sng.
Hnh 23
Hnh 23
Hnh 24
Tm hiu ph$n m&m t'(ng tc ISE

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B11. Trong cEa s) hi.n song ta c th thay 0)i mu cAa sng hin th1 bDng cch nhLp ph7i
chu<t vo I/O mu;n 0)i mu rGi chHn Signal color.





























Trong ISE con hO tr: cho mnh chHn chn cho con linh ki.n mnh vTa thi/t k/ nh'ng do th3i
gian co h,n nn nhm khng trnh by I 0y.
- P t,o m<t Source mMi hay add thm Source ta c th vo Project /chon 8ng dFng
mnh c$n. vd b'Mc 1 trong t,o test bench.
IV/T0o new Schematic - thi9t k9 m0ch add_half dng c;ng logic:
B1 0/n B7 lm gi;ng cc b'Mc t'(ng 8ng nh' trong ph$n t,o New Project.

B8. ChHn kiu Source. U 0y chHn Shematic v 0Nt tn cho module l add_half. Click next
Hnh 26
Hnh 25
Tm hiu ph$n m&m t'(ng tc ISE

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B9. T'(ng t- B10 trn ph$n t,o New Project.
Lm t'(ng t- B11, B12 trong t,o New Project.
Sau cc b'Mc trn ta 0':c nh' Hnh 27





















Hnh 26 Hnh 26
Tm hiu ph$n m&m t'(ng tc ISE

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B10. U 0y t,o m,ch c<ng nEa nn cn I c)ng and v m<t c)ng xor. NhKp tn c)ng logic c$n
lLy vo Symbol Name Fiter


Hnh 27
Tm hiu ph$n m&m t'(ng tc ISE

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B11. LLy c)ng xor2
























B12. NhLp chHn cng cF vW dy v n;i. Hnh 28
ChHn con tr+
ChHn m<t vng
Cng cF vW dy
PNt tn cho 0'3ng 0y v I/O
I/O
ChHn linh ki.n
Tm hiu ph$n m&m t'(ng tc ISE

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B13. Sau khi n;i dy chHn I/O 0 vW input v output. Nh' Hnh 29


Hnh 28
Hnh 29
Tm hiu ph$n m&m t'(ng tc ISE

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B14.chHn cng cF 0?t tn ri click double vo cc chn input v output 0 0?t l,i tn.



B14. Sau khi 0Nt tn cho input ca output 0':c nh' Hnh 31




Hnh 30
Hnh 31
Tm hiu ph$n m&m t'(ng tc ISE

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B15. Save v chHn tab Design rGi chHn Synthesize XST 0 kim tra lOi .


B16. T,o test bench t'(ng t- nh' ph$n t,o test bench I trn ph$n II.
Hnh 32
Hnh 33
Tm hiu ph$n m&m t'(ng tc ISE

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B17. Sau khi hon thnh cc b'Mc t,o test bench ta thm code nh' Hnh 34 I d'Mi.
























B18. Trong tab Source for chHn Behavioral Simulation rGi chHn Behavioral Check Syntax.
Hnh 34
Hnh 34
Tm hiu ph$n m&m t'(ng tc ISE

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B19.ChHn Simulate Behavioral Model. CEa s) ISim hin ra nh' Hnh 35


MOi kho7ng 100 ms th gi tr1 input thay 0)i.
Do I 0y thi/t k/ m,ch c<ng nEa nn c b7ng tr,ng thi sau.












Ta thLy bi thi/t k/ m,ch add_half nh' trn cho k/t qu7 0ng.

Sau khi kim tra thi/t k/ xong ta c th t,o add_half 0 sau ny sE dFng.
V/ t0o c;ng add_half
B1. TrI l,i cEa s) Project Navigator. Trong tab Source for chHn implementation
Trong Processes: add_half ta s) Design Utilities xu;ng rGi chHn Create
Schematic Symbol nh' Hnh 36
A
B S(sum) C(nhM)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Hnh 35
Tm hiu ph$n m&m t'(ng tc ISE

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B2. Sau khi th-c hi.n b'Mc 1 ta c th lLy add_half ra dng:
Trong cAa s) Project Navigator chHn tab Symbol => nhKp tn add_half vo Symbol
Name Fiter. C)ng add_half vTa t,o 0'(c l'u trong folder ch8a Project add_half.
Nh' Hnh 37
Hnh 36
Tm hiu ph$n m&m t'(ng tc ISE

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Tm hiu ph$n m&m t'(ng tc ISE

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M=c L=c
Ch.ng I: T;ng quan v7 m ph$ng ISE (ISim) ............................................. 1
I/ Th vi!n M ph$ng ............................................................2
II/ Nh&ng ()c tnh v nh&ng s, gi-i h0n c1a ISE.................2
III/ H! (i7u hnh h4 tr6 .........................................................3
IV/ Cc h8 ki9n trc ..........................................................4

Ch.ng II: H-ng d>n s: d=ng ISE 11 ......................................................... 5
I/ Giao di!n Project Navigator .................................................. 5
II/ T0o m<t Project trong ISE Project Navigator..................6
III/ T0o test bench ................................................................13
IV/T0o new Schematic - thi9t k9 m0ch add_half dng c;ng
logic .................................................................................................19
V/ t0o c;ng add_half ............................................................27