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Ec303 Practical 3
Ec303 Practical 3
Learning Outcomes:
At the end of this practical, student are able to:
i. Design schematic circuit for Synchronous JK -counter .
ii. Simulate digital output for Synchronous JK -counter .
Laboratory Equipment:
i.
ii.
Computer
Software Altera Max+Plus II Baseline 10.2 software
Theory:
Counter can be developed by cascading the flip-flop. It has been categorized into two,
asynchronous and synchronous counter. We can define the asynchronous counter as a counter
where the flip-flop is triggered from external clock and the subsequent flip-flop clock is triggered
by the output Q from previous flip-flop. This counter is also known as a ripple counter. Figure 1
below is an example of logic schematic for asynchronous counter.
Table 1 below summarized the flip-flop schematic connection for forward or backward counter.
Table 1
Connection
between
Q
CLK
CLK
Count down
Count up
Count up
Count down
In asynchronous counter, the more the flip-flop been used in the circuit, it will add more
propagation delay to the output. A synchronous circuit can be use to solve this problem where all
the flip-flop in the schematic receives the clock pulses at the same time. Besides counting
forward and backward, this counter can be designed to count randomly.
B.
D.
Compiling Project
1. Select File Project Save and Compile.
Figure 2: Compiling
A.
Simulating project
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
16. Then, fill up the Table 1 below based on result Q0, Q1 and Q2 :
Q2
Q1
Q0
INITIALLY
1
2
3
4
5
6
7
8 (RECYCLES)
QUESTION
END OF PRACTICAL 3
PRACTICAL ANSWER
SHEET
COURSE
PRACTICAL NO.
PRACTICAL TITLE
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NO
REG. NO.
STUDENT NAME
1
2
3
TOTAL
PRACTICAL 3
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PRACTICAL 3
2.0
Result
Show the waveform, truth table and all the finding from practical.
2.1 Waveform
Q2
Q1
Q0
INITIALLY
1
2
3
4
5
6
7
8 (RECYCLES)
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PRACTICAL 3
3.0
Question
Answer all the question below
1. Explain the operation of 3-bit binary counter. [2 marks]
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PRACTICAL 3
4.0
Discussion
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5.0
Conclusion
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