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module fulladder(in1,in2,in3,sum,carry);
input in1,in2,in3;
output sum,carry;
assign sum=(in1^in2)^in3;
assign carry=((in1&in2)|(in1&in3)|(in2&in3));
endmodule
2.2. SYNTHESIS OF HALF ADDER
module halfadder(in1,in2,sum,carry);
input in1,in2;
output sum,carry;
assign sum=(in1^in2);
assign carry=in1&in2;
endmodule
module sadd(sum,carry);
output[11:0]sum;
output[3:0]carry;
reg[11:0]sum;
reg[3:0]carry;
reg[11:0]in1=12'b111100101100;//F2C
reg[11:0]in2=12'b110111000101;//DC5
reg[11:0]in3=12'b000100110011;//133
reg[11:0]in4=12'b010101101001;//569
reg[11:0]in5=12'b101001000111;//A47
reg[11:0]in6=12'b011010001101;//68D
reg[11:0]in7=12'b100111001111;//9CF
reg[11:0]in8=12'b111001110110;//E76
reg[12:0]temp=13'b1000000000000;
reg[15:0]temp1=16'b1000000000000000;
wire[11:0]sum1;
reg[12:0]a1,a2,a3,a4,a5,a6,a7,a8;
reg[2:0]car0=3'b000;
wire[2:0]car1,car2,car3,car4,car5,car6,car7,car8,car9,car10,car11,car12;
reg[14:0]c=15'b000000000000000;
reg[15:0]res=16'b0000000000000000;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8)
begin
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
end
fhadd bitadd1(a1[0],a2[0],a3[0],a4[0],a5[0],a6[0],a7[0],a8[0],car0,sum1[0],car1);
fhadd bitadd2(a1[1],a2[1],a3[1],a4[1],a5[1],a6[1],a7[1],a8[1],car1,sum1[1],car2);
fhadd bitadd3(a1[2],a2[2],a3[2],a4[2],a5[2],a6[2],a7[2],a8[2],car2,sum1[2],car3);
fhadd bitadd4(a1[3],a2[3],a3[3],a4[3],a5[3],a6[3],a7[3],a8[3],car3,sum1[3],car4);
fhadd bitadd5(a1[4],a2[4],a3[4],a4[4],a5[4],a6[4],a7[4],a8[4],car4,sum1[4],car5);
fhadd bitadd6(a1[5],a2[5],a3[5],a4[5],a5[5],a6[5],a7[5],a8[5],car5,sum1[5],car6);
fhadd bitadd7(a1[6],a2[6],a3[6],a4[6],a5[6],a6[6],a7[6],a8[6],car6,sum1[6],car7);
fhadd bitadd8(a1[7],a2[7],a3[7],a4[7],a5[7],a6[7],a7[7],a8[7],car7,sum1[7],car8);
fhadd bitadd9(a1[8],a2[8],a3[8],a4[8],a5[8],a6[8],a7[8],a8[8],car8,sum1[8],car9);
fhadd bitadd10(a1[9],a2[9],a3[9],a4[9],a5[9],a6[9],a7[9],a8[9],car9,sum1[9],car10);
fhadd bitadd11(a1[10],a2[10],a3[10],a4[10],a5[10],a6[10],a7[10],a8[10],car10,sum1[10],car11);
fhadd bitadd12(a1[11],a2[11],a3[11],a4[11],a5[11],a6[11],a7[11],a8[11],car11,sum1[11],car12);
always@(car12,sum1,temp1,c,res)
begin
c<={car12,sum1};
res<=temp1-c;
sum<=res[11:0];
carry<=res[15:12];
end
endmodule
//fhadd(8 bit addition)
module fhadd(i1,i2,i3,i4,i5,i6,i7,i8,cp,s,c);
input i1,i2,i3,i4,i5,i6,i7,i8;
input [2:0]cp;
output s;
output [2:0]c;
reg s;
reg [2:0]c;
reg [3:0]s2;
wire [3:0]s1;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18;
wire ca1,ca2,ca3,ca4,ca5,ca6,ca7,ca8,ca9,ca10,ca11,ca12;
wire ca13,ca14,ca15,ca16,ca17,ca18,ca19,ca20,ca21,ca22;
hala ha1(i1,i2,x1,ca1);
hala ha2(x1,i3,x2,ca2);
hala ha3(x2,i4,x3,ca3);
hala ha4(x3,i5,x4,ca4);
hala ha5(x4,i6,x5,ca5);
hala ha6(x5,i7,x6,ca6);
hala ha7(x6,i8,s1[0],ca7);
hala ha8(ca1,ca2,x7,ca8);
hala ha9(ca3,x7,x8,ca9);
hala hal0(ca4,x8,x9,ca10);
hala hal1(ca5,x9,x10,ca11);
hala hal2(ca6,x10,x11,ca12);
hala hal3(ca7,x11,s1[1],ca13);
hala hal4(ca8,ca9,x12,ca14);
hala hal5(ca10,x12,x13,ca15);
hala hal6(ca11,x13,x14,ca16);
hala hal7(ca12,x14,x15,ca17);
hala hal8(ca13,x15,s1[2],ca18);
hala hal9(ca14,ca15,x16,ca19);
hala ha20(ca16,x16,x17,ca20);
hala ha21(ca17,x17,x18,ca21);
hala ha22(ca18,x18,s1[3],ca22);
always@(s1,cp,s2)
begin
s2<=s1+cp;
s<=s2[0];
c<=s2[3:1];
end
endmodule
// hala(2 bit addition)
module hala(a,b,s,c);
input a,b;
output s,c;
reg s,c;
always@(a,b)
begin
s=a^b;
c=a&b;
end
endmodule
reg[15:0] temp1=16'b1000000000000000;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a2,a3,a4,a5,a6,a7,a8,temp,c,res)
begin
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
c<=a1+a2+a3+a4+a5+a6+a7+a8;
res<=temp1-c;
sum<=res[11:0];
carry<=res[15:12];
end
endmodule
5. 12 BIT SERIAL SUBTRACTOR
module ssub(res);
output[15:0]res;
reg s_sign;
reg[15:0]res;
reg[11:0]in1=12'b111111111111;
reg[11:0]in2=12'b000000000101;
reg[11:0]in3=12'b000000000011;
reg[11:0]in4=12'b000000001001;
reg[11:0]in5=12'b000000000111;
reg[11:0]in6=12'b000000001101;
reg[11:0]in7=12'b000000001111;
reg[11:0]in8=12'b000000000110;
reg[12:0] a1,a2,a3,a4,a5,a6,a7,a8;
reg[12:0]temp1=13'b1000000000000;
wire[11:0] sum1;
wire[2:0] car0 = 3'b000;
wire[2:0] car1,car2,car3,car4,car5,car6,car7,car8,car9,car10,car11,car12;
reg[14:0] c = 15'b000000000000000;
reg[12:0]temp=13'b10000000000000;
always@(temp1,in1,in2,in3,in4,in5,in6,in7,in8)
begin
a1<={1'b0,in1};
a2<=temp1-in2;
a3<=temp1-in3;
a4<=temp1-in4;
a5<=temp1-in5;
a6<=temp1-in6;
a7<=temp1-in7;
a8<=temp1-in8;
end
fhadd bitadd1(a1[0],a2[0],a3[0],a4[0],a5[0],a6[0],a7[0],a8[0],car0,sum1[0],car1);
fhadd bitadd2(a1[1],a2[1],a3[1],a4[1],a5[1],a6[1],a7[1],a8[1],car1,sum1[1],car2);
fhadd bitadd3(a1[2],a2[2],a3[2],a4[2],a5[2],a6[2],a7[2],a8[2],car2,sum1[2],car3);
fhadd bitadd4(a1[3],a2[3],a3[3],a4[3],a5[3],a6[3],a7[3],a8[3],car3,sum1[3],car4);
fhadd bitadd5(a1[4],a2[4],a3[4],a4[4],a5[4],a6[4],a7[4],a8[4],car4,sum1[4],car5);
fhadd bitadd6(a1[5],a2[5],a3[5],a4[5],a5[5],a6[5],a7[5],a8[5],car5,sum1[5],car6);
fhadd bitadd7(a1[6],a2[6],a3[6],a4[6],a5[6],a6[6],a7[6],a8[6],car6,sum1[6],car7);
fhadd bitadd8(a1[7],a2[7],a3[7],a4[7],a5[7],a6[7],a7[7],a8[7],car7,sum1[7],car8);
fhadd bitadd9(a1[8],a2[8],a3[8],a4[8],a5[8],a6[8],a7[8],a8[8],car8,sum1[8],car9);
fhadd bitadd10(a1[9],a2[9],a3[9],a4[9],a5[9],a6[9],a7[9],a8[9],car9,sum1[9],car10);
fhadd bitadd11(a1[10],a2[10],a3[10],a4[10],a5[10],a6[10],a7[10],a8[10],car10,sum1[10],car11);
fhadd bitadd12(a1[11],a2[11],a3[11],a4[11],a5[11],a6[11],a7[11],a8[11],car11,sum1[11],car12);
always@(car12,sum1,temp)
begin
if (car12 == 3'b111)
begin
s_sign <= 1'b0; //(no carry)
res<= {4'b0000,sum1};
end
else
begin
always@(in1,in2,in3,in4,in5,in6,in7,in8,temp,p1,p2,res1,store)
begin
//store<= {5'b00000,in1}+{5'b00000,in2}+{5'b00000,in3}+{5'b00000,in4}+{5'b00000,in5}+{5'b00000,in6}
//+{5'b00000,in7}+{5'b00000,in8};
store<= {5'b00000,in2}+{5'b00000,in3}+{5'b00000,in4}+{5'b00000,in5}+{5'b00000,in6}
+{5'b00000,in7}+{5'b00000,in8};
p1<= temp-store[15:0];
//p2<=p1;
p2<=in1+p1;
if(p2[16]==1'b1)
begin
res<=p2[15:0];
s_sign<=1'b0;
end
else
begin
res1<= temp-p2;
res<= res1[15:0];
s_sign<=1'b1;
end
end
endmodule
7. TRAFFIC LIGHT CONTROLLER IN VERILOG HDL
module tlc(clk,reset,p1,p2,p3,p4,pl);
input clk;
input reset;
output[4:0]p1;
output[4:0]p2;
output[4:0]p3;
output[4:0]p4;
output[3:0]pl;
reg[4:0]p1;
reg[4:0]p2;
reg[4:0]p3;
reg[4:0]p4;
reg[3:0]pl;
reg[5:0]sig;
always @(posedge clk or negedge reset)
begin
if(reset==1'b0)
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
sig<=6'b000000;
end
else
begin
sig<=sig+1;
case(sig[5:0])
6'b000000:
begin
p1<=5'b10011;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b000100:
begin
p1<=5'b01000;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b001000:
begin
p1<=5'b00100;
p2<=5'b10011;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b001100:
begin
p1<=5'b00100;
p2<=5'b01000;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b010000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b10011;
p4<=5'b00100;
pl<=4'b1111;
end
6'b010100:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b01000;
p4<=5'b00100;
pl<=4'b1111;
end
6'b011000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b10011;
pl<=4'b1111;
end
6'b011100:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b01000;
pl<=4'b1111;
end
6'b100000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b0000;
end
6'b100100:sig<=6'b000000;
default:begin
end
endcase
end
end
endmodule
6'b000000:
begin
p1<=5'b10011;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b000100:
begin
p1<=5'b01000;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b001000:
begin
p1<=5'b00100;
p2<=5'b10011;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b001100:
begin
p1<=5'b00100;
p2<=5'b01000;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b010000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b10011;
p4<=5'b00100;
p<=4'b1111;
end
6'b010100:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b01000;
p4<=5'b00100;
p<=4'b1111;
end
6'b011000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b10011;
p<=4'b1111;
end
6'b011100:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b01000;
p<=4'b1111;
end
6'b100000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b0000;
end
6'b100100:sig<=8'h0;
default:begin
end
endcase
end
end
endmodule
reg[7:0] ssdigit1;
reg[7:0] ssdigit2;
reg[7:0] ssdigit3;
reg[7:0] ssdigit4;
reg[7:0] ssdigit5;
reg[7:0] ssdigit6;
integer digit1;
integer digit2;
integer digit3;
integer digit4;
integer digit5;
integer digit6;
always @ (posedge clk or negedge rst)
begin
if (rst == 1'b0) begin
sig2 = 0;
sig3 = 0;
digit1 = 0;
digit2 = 0;
digit3 = 0;
digit4 = 0;
digit5 = 0;
digit6 = 0;
end
else begin
sig2 = sig2 + 1;
case (sig2[24:23]) //RTC Function
2'b00 : begin
digit6 = digit6 + 1;
if (digit6 > 9) begin
digit6 = 0;
digit5 = digit5 + 1;
if (digit5 > 5) begin
digit5 =0;
digit4 = digit4 + 1;
if (digit4 >9 ) begin
digit4 = 0;
digit3 = digit3 + 1;
if (digit3 > 5) begin
digit3 = 0;
digit2 = digit2 + 1;
if (digit2 >9) begin
digit2 = 0;
digit1 = digit1 + 1; if ((digit1 >= 2) & (digit2 >= 4)) begin digit1 = 0;
digit2 = 0;
end
end
end
end
end
end
sig2[24:23] = 2'b01;
end
2'b11 : begin
if (sig2[22:19] == 4'b1001)
sig2 = 0;
end
default : begin
end
endcase
end
// Display Settings
sig3 = sig3 + 1;
case (sig3[17:15])
3'b000 : begin
sl = 6'b111110;
case (digit1)
0 : ssdigit1 = 8'b00111111;
1 : ssdigit1 = 8'b00000110;
2 : ssdigit1 = 8'b01011011;
default : ssdigit1 = 8'b00000000;
endcase
atoh = ssdigit1;
end
3'b001 : begin
sl = 6'b111101;
case (digit2)
0 : ssdigit2 = 8'b00111111;
1 : ssdigit2 = 8'b00000110;
2 : ssdigit2 = 8'b01011011;
3 : ssdigit2 = 8'b01001111;
4 : ssdigit2 = 8'b01100110;
5 : ssdigit2 = 8'b01101101;
6 : ssdigit2 = 8'b01111101;
7 : ssdigit2 = 8'b00000111;
8 : ssdigit2 = 8'b01111111;
9 : ssdigit2 = 8'b01101111;
default : ssdigit2 = 8'b00000000;
ndcase
atoh = ssdigit2;
end
3'b011 : begin
sl = 6'b111011;
case (digit3)
0 : ssdigit3 = 8'b00111111;
1 : ssdigit3 = 8'b00000110;
2 : ssdigit3 = 8'b01011011;
3 : ssdigit3 = 8'b01001111;
4 : ssdigit3 = 8'b01100110;
5 : ssdigit3 = 8'b01101101;
default : ssdigit3 = 8'b00000000;
endcase
atoh = ssdigit3;
end
3'b100 : begin
sl = 6'b110111;
case (digit4)
0 : ssdigit4 = 8'b00111111;
1 : ssdigit4 = 8'b00000110;
2 : ssdigit4 = 8'b01011011;
3 : ssdigit4 = 8'b01001111;
4 : ssdigit4 = 8'b01100110;
5 : ssdigit4 = 8'b01101101;
6 : ssdigit4 = 8'b01111101;
7 : ssdigit4 = 8'b00000111;
8 : ssdigit4 = 8'b01111111;
9 : ssdigit4 = 8'b01101111;
default : ssdigit4 = 8'b00000000;
endcase
atoh = ssdigit4;
end
3'b110 : begin
sl = 6'b101111;
case (digit5)
0 : ssdigit5 = 8'b00111111;
1 : ssdigit5 = 8'b00000110;
2 : ssdigit5 = 8'b01011011;
3 : ssdigit5 = 8'b01001111;
4 : ssdigit5 = 8'b01100110;
5 : ssdigit5 = 8'b01101101;
default : ssdigit5 = 8'b00000000;
endcase
atoh = ssdigit5;
end
3'b111 : begin
sl = 6'b011111;
case (digit6)
0 : ssdigit6 = 8'b00111111;
1 : ssdigit6 = 8'b00000110;
2 : ssdigit6 = 8'b01011011;
3 : ssdigit6 = 8'b01001111;
4 : ssdigit6 = 8'b01100110;
5 : ssdigit6 = 8'b01101101;
6 : ssdigit6 = 8'b01111101;
7 : ssdigit6 = 8'b00000111;
8 : ssdigit6 = 8'b01111111; 9 : ssdigit6 = 8'b01101111;
default : ssdigit6 = 8'b00000000;
endcase
atoh = ssdigit6;
end
endcase
end
end
endmodule
USER CONSTRIANT FILE
NET "clk" LOC = "a8";
NET "rst" LOC = "j6";
NET "atoh<0>" LOC = "p8" ;
NET "atoh<1>" LOC = "p10" ;
NET "atoh<2>" LOC = "p9" ;
NET "atoh<3>" LOC = "p6" ;
NET "atoh<4>" LOC = "p4" ;
onebitadder ob1(a[0],b[0],c,sum[0],carry[0]);
onebitadder ob2(a[1],b[1],carry[0],sum[1],carry[1]);
onebitadder ob3(a[2],b[2],carry[1],sum[2],carry[2]);
onebitadder ob4(a[3],b[3],carry[2],sum[3],carryout);
endmodule
//onebit adder//
module onebitadder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=(a^b)^c;
assign carry=(a&b)|(a&c)|(b&c);
endmodule
Following is Verilog code for a flip-flop with a negative-edge clock and asynchronous clear.
module flop (clk, d, clr, q);
input clk, d, clr;
output q;
reg
q;
always @(negedge clk or posedge clr)
begin
if (clr)
q <= 1b0;
else
q <= d;
end
endmodule
Following is Verilog code for the flip-flop with a positive-edge clock and synchronous set.
module flop (clk, d, s, q);
input clk, d, s;
output q;
reg
q;
always @(posedge clk)
begin
if (s)
q <= 1b1;
else
q <= d;
end
endmodule
Following is Verilog code for the flip-flop with a positive-edge clock and clock enable.
module flop (clk, d, ce, q);
input clk, d, ce;
output q;
reg
q;
always @(posedge clk)
begin
if (ce)
q <= d;
end
endmodule
Following is Verilog code for a 4-bit register with a positive-edge clock, asynchronous set
and clock enable.
module flop (clk, d, ce, pre, q);
input
clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg
[3:0] q;
always @(posedge clk or posedge pre)
begin
if (pre)
q <= 4b1111;
else if (ce)
q <= d;
end
endmodule
Following is the Verilog code for a latch with a positive gate and an asynchronous clear.
module latch (g, d, clr, q);
input g, d, clr;
output q;
reg
q;
always @(g or d or clr)
begin
if (clr)
q <= 1b0;
else if (g)
q <= d;
end
endmodule
Following is Verilog code for a 4-bit latch with an inverted gate and an asynchronous
preset.
module latch (g, d, pre, q);
input
g, pre;
input [3:0] d;
output [3:0] q;
reg
[3:0] q;
always @(g or d or pre)
begin
if (pre)
q <= 4b1111;
else if (~g)
q <= d;
end
endmodule
Following is Verilog code for a tristate element using a combinatorial process and always
block.
module three_st (t, i, o);
input t, i;
output o;
reg
o;
always @(t or i)
begin
if (~t)
o = i;
else
o = 1bZ;
end
endmodule
Following is the Verilog code for a tristate element using a concurrent assignment.
module three_st (t, i, o);
input t, i;
output o;
assign o = (~t) ? i: 1bZ;
endmodule
Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear.
module counter (clk, clr, q);
input
clk, clr;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule
Following is the Verilog code for a 4-bit unsigned down counter with synchronous set.
module counter (clk, s, q);
input
clk, s;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 4b1111;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule
Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous load
from the primary input.
module counter (clk, load, d, q);
input
clk, load;
input [3:0] d;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule
Following is the Verilog code for a 4-bit unsigned up counter with a synchronous load with
a constant.
module counter (clk, sload, q);
input
clk, sload;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= 4b1010;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule
Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous clear
and a clock enable.
module counter (clk, clr, ce, q);
input
clk, clr, ce;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
Following is the Verilog code for a 4-bit unsigned up/down counter with an asynchronous
clear.
module counter (clk, clr, up_down, q);
input
clk, clr, up_down;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else if (up_down)
tmp <= tmp + 1b1;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule
Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset.
module counter (clk, clr, q);
input
clk, clr;
output signed [3:0] q;
reg
signed [3:0] tmp;
always @ (posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule
Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset and
a modulo maximum.
Following is the Verilog code for a 4-bit unsigned up accumulator with an asynchronous
clear.
module accum (clk, clr, d, q);
input
clk, clr;
input [3:0] d;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + d;
end
assign q = tmp;
endmodule
Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, serial
in and serial out.
module shift (clk, si, so);
input
clk,si;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
tmp
<= tmp << 1;
tmp[0] <= si;
end
assign so = tmp[7];
endmodule
Following is the Verilog code for an 8-bit shift-left register with a negative-edge clock, a
clock enable, a serial in and a serial out.
module shift (clk, ce, si, so);
input
clk, si, ce;
output
so;
reg
[7:0] tmp;
always @(negedge clk)
begin
if (ce) begin
tmp
<= tmp << 1;
tmp[0] <= si;
end
end
assign so = tmp[7];
endmodule
Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock,
asynchronous clear, serial in and serial out.
module shift (clk, clr, si, so);
input
clk, si, clr;
output
so;
reg
[7:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 8b00000000;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, a
synchronous set, a serial in and a serial out.
module shift (clk, s, si, so);
input
clk, si, s;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 8b11111111;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, a
serial in and a parallel out.
module shift (clk, si, po);
input
clk, si;
output [7:0] po;
reg
[7:0] tmp;
always @(posedge clk)
begin
tmp <= {tmp[6:0], si};
end
assign po = tmp;
endmodule
Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, an
asynchronous parallel load, a serial in and a serial out.
module shift (clk, load, si, d, so);
input
clk, si, load;
input [7:0] d;
output
so;
reg
[7:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, a
synchronous parallel load, a serial in and a serial out.
module shift (clk, sload, si, d, so);
input
clk, si, sload;
input [7:0] d;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Following is the Verilog code for an 8-bit shift-left/shift-right register with a positive-edge
clock, a serial in and a serial out.
module shift (clk, si, left_right, po);
input
clk, si, left_right;
output
po;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (left_right == 1b0)
tmp <= {tmp[6:0], si};
else
tmp <= {si, tmp[7:1]};
end
assign po = tmp;
endmodule
Following is the Verilog code for a 4-to-1 1-bit MUX using an If statement.
module mux (a, b, c, d, s, o);
input
a,b,c,d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
if (s == 2b00)
o = a;
else if (s == 2b01)
o = b;
else if (s == 2b10)
o = c;
else
o = d;
end
endmodule
Following is the Verilog Code for a 4-to-1 1-bit MUX using a Case statement.
module mux (a, b, c, d, s, o);
input
a, b, c, d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
case (s)
2b00
: o = a;
2b01
: o = b;
2b10
: o = c;
default : o = d;
endcase
end
endmodule
Following is the Verilog code for a 3-to-1 1-bit MUX with a 1-bit latch.
module mux (a, b, c, d, s, o);
input
a, b, c, d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
if (s == 2b00)
o = a;
else if (s == 2b01)
o = b;
else if (s == 2b10)
o = c;
end
endmodule
begin
case (sel)
3b000
3b001
3b010
3b011
3b100
3b101
3b110
default
endcase
end
endmodule
:
:
:
:
:
:
:
:
res
res
res
res
res
res
res
res
=
=
=
=
=
=
=
=
8b00000001;
8b00000010;
8b00000100;
8b00001000;
8b00010000;
8b00100000;
8b01000000;
8b10000000;
else if
code
else if
code
else if
code
else if
code
else if
code
else
code
(sel[3])
= 3b011;
(sel[4])
= 3b100;
(sel[5])
= 3b101;
(sel[6])
= 3b110;
(sel[7])
= 3b111;
= 3bxxx;
end
endmodule
Following is the Verilog code for an unsigned 8-bit adder with carry in.
module
input
input
input
output
Following is the Verilog code for an unsigned 8-bit adder with carry out.
module
input
input
output
output
wire
assign tmp = a + b;
assign sum = tmp [7:0];
assign co = tmp [8];
endmodule
Following is the Verilog code for an unsigned 8-bit adder with carry in and carry out.
module
input
input
input
output
output
wire
Following is the Verilog code for an unsigned 8-bit greater or equal comparator.
module compar(a, b, cmp);
input [7:0] a;
input [7:0] b;
output
cmp;
assign cmp = (a >= b) ?
1b1 : 1b0;
endmodule
compar(a, b, res);
[7:0] a;
[3:0] b;
[11:0] res;
assign res = a * b;
endmodule
Following Verilog template shows the multiplication operation placed outside the always
block and the pipeline stages represented as single registers.
module
input
input
input
output
reg
reg
wire
reg
mult(clk, a, b, mult);
clk;
[17:0] a;
[17:0] b;
[35:0] mult;
[35:0] mult;
[17:0] a_in, b_in;
[35:0] mult_res;
[35:0] pipe_1, pipe_2, pipe_3;
end
endmodule
Following Verilog template shows the multiplication operation placed inside the always
block and the pipeline stages are represented as single registers.
module mult(clk, a, b, mult);
input
clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg
[35:0] mult;
reg
[17:0] a_in, b_in;
reg
[35:0] mult_res;
reg
[35:0] pipe_2, pipe_3;
always @(posedge clk)
begin
a_in
<= a;
b_in
<= b;
mult_res <= a_in * b_in;
pipe_2
<= mult_res;
pipe_3
<= pipe_2;
mult
<= pipe_3;
end
endmodule
Following Verilog template shows the multiplication operation placed outside the always
block and the pipeline stages represented as single registers.
module
input
input
input
output
reg
reg
wire
reg
mult(clk, a, b, mult);
clk;
[17:0] a;
[17:0] b;
[35:0] mult;
[35:0] mult;
[17:0] a_in, b_in;
[35:0] mult_res;
[35:0] pipe_1, pipe_2, pipe_3;
mult
<= pipe_3;
end
endmodule
Following Verilog template shows the multiplication operation placed inside the always
block and the pipeline stages are represented as single registers.
module mult(clk, a, b, mult);
input
clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg
[35:0] mult;
reg
[17:0] a_in, b_in;
reg
[35:0] mult_res;
reg
[35:0] pipe_2, pipe_3;
always @(posedge clk)
begin
a_in
<= a;
b_in
<= b;
mult_res <= a_in * b_in;
pipe_2
<= mult_res;
pipe_3
<= pipe_2;
mult
<= pipe_3;
end
endmodule
Following Verilog template shows the multiplication operation placed outside the always
block and the pipeline stages represented as shift registers.
module
input
input
input
output
reg
reg
wire
reg
mult3(clk, a, b, mult);
clk;
[17:0] a;
[17:0] b;
[35:0] mult;
[35:0] mult;
[17:0] a_in, b_in;
[35:0] mult_res;
[35:0] pipe_regs [3:0];
end
endmodule
Following is the Verilog code for a single-port RAM with asynchronous read.
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule
Following is the Verilog code for a single-port RAM with "false" synchronous read.
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
do <= ram[a];
end
endmodule
Following is the Verilog code for a single-port RAM with synchronous read (read through).
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule
Following is the Verilog code for a single-port block RAM with enable.
module raminfr (clk, en, we, a, di, do);
input
clk;
input
en;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (en) begin
if (we)
ram[a] <= di;
read_a <= a;
end
end
assign do = ram[read_a];
endmodule
Following is the Verilog code for a dual-port RAM with asynchronous read.
Following is the Verilog code for a dual-port RAM with false synchronous read.
module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
reg
[3:0] spo;
reg
[3:0] dpo;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
spo = ram[a];
dpo = ram[dpra];
end
endmodule
Following is the Verilog code for a dual-port RAM with synchronous read (read through).
module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
Following is the Verilog code for a dual-port RAM with enable on each port.
module raminfr (clk, ena, enb, wea, addra, addrb, dia, doa, dob);
input
clk, ena, enb, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] doa, dob;
reg
[3:0] ram [31:0];
reg
[4:0] read_addra, read_addrb;
always @(posedge clk)
begin
if (ena) begin
if (wea) begin
ram[addra] <= dia;
end
end
end
always @(posedge clk)
begin
if (enb) begin
read_addrb <= addrb;
end
end
assign doa = ram[read_addra];
assign dob = ram[read_addrb];
endmodule
input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
4b0000: data
4b0001: data
4b0010: data
4b0011: data
4b0100: data
4b0101: data
4b0110: data
4b0111: data
4b1000: data
4b1001: data
4b1010: data
4b1011: data
4b1100: data
4b1101: data
4b1110: data
4b1111: data
default: data
endcase
end
endmodule
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
4b0010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;
4b1100;
4b0000;
4b1010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;
4b1100;
4b0000;
4bXXXX;
data
data
data
data
data
data
=
=
=
=
=
=
4b0010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;
4b0110:
4b0111:
4b1000:
4b1001:
4b1010:
4b1011:
4b1100:
4b1101:
4b1110:
4b1111:
default:
endcase
data
data
data
data
data
data
data
data
data
data
data
=
=
=
=
=
=
=
=
=
=
=
4b1100;
4b0000;
4b1010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;
4b1100;
4b0000;
4bXXXX;
end
endmodule
endcase
end
end
endmodule