ECE176 Digital System Design Using Verilog (3 Units)

Fall 2007
Department of Electrical and Computer Engineering
California State University Fresno
Instructor: Dr. Charles Won
Office: EE 264
Phone: 559-278-4415
Email: chwon@csufresno.edu
Office hours:
Course Prerequisites & Coverage
Prerequisites: ECE120L or concurrently
The coverage includes following topics:
Use of CAE tools for digital system design and implementation
Design projects using a full design cycle from specification to implementation
using FPGA and CPLDs RTL design, simulation, timing analysis
Hands-on experience using CAE tools
Course Objectives
This class was designed for the upper level electrical engineering and computer
engineering major students to achieve the following educational objectives:
To familiarize the use of the CAE tools for medium-scale digital system design:
Verilog-HDL and FPGA/EPLD Logic Synthesizer
To design digital system using the CAE Tools
To use a simulator (Verilog Simulator) to validate design
To implement digital circuit on FPGA/EPLD devices
To practice various digital system designs
Course Material Requirements (Tentative)
Textbook: Verilog Digital System Design, 2nd Edition, Zainalabedin Navabi,
McGrawHill.
CAE Tools: Verilog Simulator, Logic Synthesizer, EPLD/FPGA Device
Programming Software.
Course Evaluation (Tentative)
Item

Point

Weight (%)

Final Grade

Quiz

100

20

Homework
Midterm Exam1
Midterm Exam2
Final Exam

100
100
100
100

20
20
20
20

Letter: Cumulative Score (%)

A: 450 500 ( 90 %)
B: 400 449 ( 80 %)
C: 350 400 ( 70 %)
D: 300 349 ( 60 %)
F: 0 299

Class Schedule (Tentative)

Week
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Date

Final Week

Topic
Ch1: Digital Design
Verilog-HDL Language Overview
Ch2: Register Transfer Level (RTL) Design
Tutorial: Digital Design using Verilog
Elements of Verilog
Ch3: Verilog Language Syntax
Ch4: Combinational Circuit Design
Hierarchical Design
Behavioral Description
Combinational Circuit Synthesis
Ch5: Sequential Circuit
Sequential Circuit Models
Registers: Shift Reg., Counters, LFSR,
MISR, Stacks & Queues
State Machine Coding
Sequential Circuit Synthesis
An embedded processor design
No Class

Assignments
HW1, QZ
HW2, QZ
HW3, QZ
HW4, QZ
HW5, QZ
HW6, QZ
HW7, QZ
HW8, QZ
HW9, QZ
HW10, QZ
HW11, QZ
HW12, QZ
HW13, QZ

Tests

Midterm Exam1

Midterm Exam2

HW14, QZ
HW15, QZ
Final Exam