Register Number

SATHYABAMA UNIVERSITY
(Established under section 3 of UGC Act, 1956)

Course & Branch: M.E/M.Tech-EMBED/VLSI

Title of the Paper: VLSI Design
Sub. Code: SECX5018
Date: 11/12/2010

Max. Marks: 80
Time: 3 Hours
Session: FN

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PART - A
(6 X 5 = 30)
Answer ALL the Questions
1.

Draw the small signal model for MOS transistor and explain the
different parameters. Write the expression for transconductance.

2.

Explain the noise margin of CMOS circuit with neat diagram.

3.

Draw the layout diagram for Half adder.

4.

Design a 3:1 Mux using CMOS logic.

5.

Explain the structure of Barrel shifter with diagram.

6.

Explain the operation of Six transistor Static CMOS Memory

Cell structure.

7.

8.

PART B
(5 x 10 = 50)
Answer ALL the Questions
Explain the energy band diagram of MOS structure while
conducting with energy work function and derive the expression
for threshold voltage.
(or)
Explain all the secondary effects of MOSFET with necessary
diagram and expressions.

9.

What is DRC? Explain the n-well rules with neat diagram.

(or)
10. Explain n/p ratio. Explain how the characteristics differ in
saturated and depleted load inverter.
11. Draw the SUM part of the full adder in dynamic CMOS and
Clocked CMOS logic.
(or)
12. What is PLA? Draw the structure of PLA for the following using
MOS structure.
(a) Z1 = a + b
(b) Z2 = ab + cd
(c) Z3 = (a+b) (c+d)
13. Explain the characteristics of Gate, diffusion and routing
capacitance in CMOS.
(or)
14. Draw 4 bit dynamic shift register with CMOS arrangement and
draw stick diagram for shift register cells.
15. Explain the carry select and carry skip adder structure with neat
diagram.
(or)
16. Explain the structure of 2s complement Multiplication using
Baugh Wooley method.