1 Day Arm 20071088

Standard Microcontroller
1-day ARM Training

Paolo Bernasconi
NXP Semiconductors, FAE
Agenda
9:30 LPC2000 Technical Training Part I
- Introduzione
- LPC2000 devices and roadmaps dev tools. I nuovi dispositivi della
famiglia LPC2300 e LPC2400. Novit per il 2007
Break
- Presentazione dell'Architettura ARM7 (mappa di memoria, system
control, peripherals)
12:30 Pranzo
13:30 LPC2000 Technical Training Part II
- Inizializzazione delle periferiche di sistema
PLL, Vector Interrupt Controller e USB
- presentazioni di esempi con tool Keil e scheda di valutazione Keil
Break
- Implementazone dellarchitettura ARM7 nella famiglia LPC23/24
- Q&A
17:30 Chiusura
CONFIDENTIAL
Subject/Department, Author, MMMM dd, yyyy
Standard Microcontroller Cores

32/16-bit
Throughput
100
10
LPC3000
ARM926EJ
LPC2000
ARM7TDMI-S
16-bit XA
8-bit
16-bit
LPC900 2-Clock
LPC700 6-Clock
1
6-Clock MX
C51X2 6-Clock
C51 12-Clock
Memory Size
2 KB
64 KB
1 MB
>16 MB
CONFIDENTIAL
NXP Embedded Flash Process Roadmap

Mature product line
low-cost, 3-5V OTP
5V Flash family
Si Foundry
LPC900 Family
3V Flash
MOS34 / ASMC
Planned
Embedded
Flash
CMOS90
LPC2000 Family
ARM7S-TDMI
1.8V Flash
MOS34 / SSMC
Crolles2
ARM926EJ
CMOS90
Crolles2
0.5
0.4
0.35
0.18 0.16 0.14
90n
ARM1156EJ
CMOS65
Crolles2
65n
Process Feature Size
CONFIDENTIAL
Standard Microcontroller
Strategy Summary
Develop Innovative and Cost Effective Products
Focus on 16/32-bit market with wide range
of ARM7 & ARM9 based products
Expand the successful LPC Family approach:
- New peripherals like USB, Ethernet, .......
Use highly competitive flash based processes:
- 0.35 m and 0.18 m Flash in production
- Shrink path down to 0.14 m
- First products in 90nm in 2005
Introduction of innovative packages:
- Chip scale packages like HVSON10, TFBGA256
CONFIDENTIAL
LPC2000 Family
16/32-bit ARM7TDMI-S Products
ARM Microcontrollers
NXP has developed a family of ARM-based Microcontrollers
For
- Low-Cost High Volume Applications
With
- Embedded Flash and SRAM
- On-board AMBA-bus Peripherals (Adv. C Bus Architecture)
- Real-Time Deterministic behavior (no Cache required)
-High performance NXP specific Flash Memory matrix
-and access design
- Full Debug, Real-time Monitoring and Trace facilities
To
- Continue on from our successful 8-bit 80C51 Family
- Enable new low-cost 16/32-bit Microcontroller-based applications
CONFIDENTIAL
NXP Standard Microcontrollers

The Ultimate Products..
LPC2000
13 mm
LPC3000
CONFIDENTIAL
History - NXP a leader in ARM

NXP relationship with ARM Ltd. spans a decade
One of the three founding partners of ARM
Development with cores starting from ARM2 through ARM11
NXP offers the most experience

Over 250 ARM designs - more than anyone else in the industry
In Top 3 for ARM shipments worldwide
More than a dozen ARM cores in over 7 CMOS processes
NXP is a long-term ARM licensee

Extensive license relationship provides continuous access to all architectures
Announcing off-the-shelf ARM microcontrollers with embedded Flash
CONFIDENTIAL
ARM vs. other 32/16-bit Emb. Architectures

450
400
350
ARM Volume in
Y2004: 190 MU
300
200
M units
250
150
100
0
7
05
03
01
02
04
06
0
20
20
20
20
20
20
20
0
20
0
99
19
98
19
SH MI
-7 PS
Po XX
X
w
er
P
SP
C
A
R
80 C
X
86
ST
20
+
R
M
68
K
50
Source: SEMICO Research, Q4 2002

Numbers excluding cell phone handsets
ARM : Leading solution for Industrial / Automotive,

CONFIDENTIAL
Communications and General Purpose
Million USD Revenues of ARM Holdings PLC
M Unit Shipment of ARM based products
Shipments of all ARM products
ARMs partners shipped 1,662 Mpcs in 2005 (+31%)

CONFIDENTIAL
ARM7TDMI-S NXP Choice

The ARM7TDMI-S is based on an ARM7 core
T- Thumb architecture extension

ARM Instructions are all 32 bit
Thumb instructions are all 16 bit
Two execution states to select which instruction set to execute
D- Core has debug extensions

M- Core has enhanced multiplier
I- Core has Embedded ICE Macrocell
S- Fully synthesis able
CONFIDENTIAL
2007
16/32-bit ARM7 LPC2000
Released (28)
UART(2), I2C
SPI/SSP, LV RTC
ADC(1-2), DAC
3V single p.supply
UART(2), I2C
SPI(2), RTC
ADC, CAN
Flash Security
1.8V and 3.3 V
I2C
UART(2),
SPI(2), RTC
ADC
1.8V and 3.3 V

LPC2106 /01
128K/64K
LPC2105 /01
128K/32K
LPC2104 /01
128K/16K
LPC2101/2/3
8/16/32K/Flsh
2/4/8KRam
ADC,LV,RTC
48pins
UART(2),
I2C(2), SPI,
SPI/SSP, RTC,
ADC
Flash Security
UART(2), I2C, USB

SPI/SSP, LV RTC
LPC21xx
ADC(1-2), DAC
3V p.supply UART(2), I2C
CAN(2)
LPC2146
LPC2129 /01 LPC2136 /01
256K/32K+8K
256K/16K
256K/32K
USB
ADC(2), DAC
CAN (2)
ADC(2), DAC
LPC2144
LPC2124 /01 LPC2134 /01
128K/16K+8K
128K/16K
256K/16K
USB
ADC(2), DAC
ADC
ADC(2), DAC
LPC2114 /01
128K/16K
ADC
LPC2132 /01
64K/16K
ADC, DAC
LPC2131 /01
LPC2142
64K/16K+8K
USB
ADC, DAC
LPC2141
32K/8K
ADC
32K/8K+8K
USB
ADC
64pins
64pins
UART(2), I2C
SPI(2), RTC
ADC, CAN
UART(2), I2C
SPI, SPI/SSP,
LV RTC
ADC(1-2), DAC
10b-ADC
Flash Security
1.8V and 3.3 V UART(2),
+ external bus
UART(4), I2C(3)
SPI(1), SSP(2),
LV RTC,
ADC, DAC,
PWM(2),
USB full
I2C10/100 Ethernet,
CAN(2), IRC
SPI(2), RTC
ADC, CAN
LPC2214 /01 Flash Security

256K/16K
1.8V and 3.3 V
ADC
+external bus
LPC2212 /01
128K/16K
ADC
LPC2220
0K/64K
ADC
LPC2210 /01
H2 06
/01
100 - 144 pins
Flash Security SPI(2), RTC
LPC2148
LPC2194 /01 LPC2138 /01
512K/32K+8K
256K/16K
512K/32K
USB
ADC(2), DAC
CAN (4)
ADC(2), DAC
LPC2119 /01
128K/16K
CAN (2)
UART(4)
2x AHB + Ethernet
+Single p supply
3.3V
Minibus
LPC2294 /01
256K/16K
CAN (4)
LPC2292 /01
256K/16K
CAN (2)
LPC2290 /01
0K/16K
ADC
0K/16K
CAN (2)
64pins
144pins
144pins
UART(2), I2C
SPI(2), USB,
LV RTC
ADC, DAC
UART(2), I2C
SPI(2), RTC
ADC
UART(2), I2C
SPI(2), RTC
ADC, CAN(2/4)
LPC2378
512K/58K
Ethernet,
USB, CAN,
MiniBus, MMC
LPC2368
512K/58K
Ethernet,
USB, CAN,
MMC
H1 2007
ARM7TDMI-S : LPC2000
ARM926EJ : LPC3000
+external bus
+ USB
OTG/Host
180 - 208 pins
UART(4), I2C(3)
SPI(1), SSP(2),
LV RTC,
ADC, DAC,
+ external
PWM(2),
bus
USB-OTG
10/100 Ethernet, 16 bits codec
CAN(2), IRC,
USB High
External Bus
speed device
LPC2366
256K/58K
Ethernet,
USB, CAN
LPC2468
512K/98K
Ethernet,
USB, CAN
LPC2364
128K/34K
Ethernet,
USB, CAN
LPC2458
512K/98K
Ethernet,
USB, CAN
LPC2888
Floating
point
coprocessor
USB Host full
speed
LPC3190
1M/64K
USB HS
LCD int
IIS,SPI
Ethernet
LPC2880
LPC3180
0M/64K
USB HS
64K RAM,
32+32K Cache
180 pins
Flex. Suppl.
HS USB,
Flex. Ext.
Mem.
LCDcontr.Interf
.
320 pins
ADC, 2xI2C,
2xSPI,
7xUART,USBOTG.
Timing/features/packages of non released parts may

CONFIDENTIAL
change without prior notification
Roadmap 32-bit portfolio
Functionality
Recently
released
Roadmap
LPC31xx: ARM9
SPI
LPC3190
IIS interface
Ethernet MAC controller
LCD interface
LPC2468
LPC2368 LPC2378
LPC23xx: ARM7
LPC2366 Ethernet (RMII)

LPC2364
LPC24xx: ARM7
Ethernet (MII+RMII)
USB FS Device
USB Host/OTG LPC2458
2 x CAN
Ext. Memory (SDRAM, SRAM)
96K SRAM
USB FS Device
2 x CAN
LPC3000
LPC3000
LPC3000
LPC3000
LPC2000
LPC2000
LPC2000
LCD
LCD
LCD
Recently released
LPC22xx/01
New releases
LPC21xx/01
2007
LPC210x/01
Feature and performance improvements
Time
CONFIDENTIAL
/00 Versions Status
Reset.1 bug fixed

LPC2104/00 and LPC2105/00 are
Indus. Temp. range qualified
Parts
Samples
LPC2104FBD48/00
Yes
LPC2105FBD48/00
Yes
LPC2106FBD48/00
Yes
LPC2106FHN48/00
Yes
LPC2114FBD64/00
Yes
LPC2124FBD64/00
Yes
LPC2119FBD64/00
Yes
LPC2129FBD64/00
Yes
LPC2194HBD64/00
Yes
LPC2212FBD144/00
Yes
LPC2214FBD144/00
Yes
LPC2292FBD144/00
Yes
LPC2292FET144/00
Yes
LPC2294HBD144/00
Yes
Status
RFS
RFS
RFS
RFS
RFS
RFS
RFS
RFS
RFS
RFS
RFS
RFS
RFS
RFS
CONFIDENTIAL
/01 Versions Status
All bugs corrected excepted core.1

Some enhanced features:
Fast I/O (3-4 times faster than
standard)
Counter inputs
Dedicated result registers per ADC
input
UART improvements
Program security (for the LPC210x)
Parts
Samples
LPC2104FBD48/01
No
LPC2105FBD48/01
No
LPC2106FBD48/01
No
LPC2106FHN48/01
No
LPC2114FBD64/01
No
LPC2124FBD64/01
No
LPC2119FBD64/01
No
LPC2129FBD64/01
No
LPC2131FBD64/01
Yes
LPC2132FBD64/01
Yes
LPC2132FHN64/01
Yes
LPC2134FBD64/01
Yes
LPC2136FBD64/01
Yes
LPC2138FBD64/01
Yes
LPC2138FHN64/01
No
LPC2194HBD64/01
No
LPC2210FBD144/01
Yes
LPC2290FBD144/01
Yes
LPC2212FBD144/01
No
LPC2214FBD144/01
No
LPC2292FET144/01
No
LPC2294HBD144/01
No
Status
Dev
Dev
Dev
Dev
Dev
Dev
Dev
Dev
RFS
RFS
RFS
RFS
RFS
RFS
RFS
Dev
RFS
RFS
Dev
Dev
Dev
Dev
RFS date
H1/07
H1/07
H1/07
H1/07
H1/07
H1/07
H1/07
H1/07
Now
Now
Now
Now
Now
Now
Now
H1/07
Now
Now
H1/07
H1/07
H1/07
H1/07
CONFIDENTIAL
Test/Debug
Memory
Memory
Accelerator
Accelerator
Vss
Vdd
RST
X2
System
System
Functions
Functions
PLL
PLL
System Clock
ARM
ARM 7TDMI-S
7TDMI-S
Local Bus
Real
Real Time
Time
Clock
Clock
Trace
Trace
Watchdog
Watchdog
Timer
Timer
AHBBridge
Bridge
AHB
SRAM
SRAM
Controller
Controller
X1
TDO
TDI
TCK
128
128KB
KB
FLASH
FLASH
TMS
16-64KB
16-64KB
SRAM
SRAM
RTCK
TRST
LPC2104/5/6 Block Diagram
Vectored
VectoredInterrupt
Interrupt
Controller
Controller
AHB
AHBto
toVPB
VPBBridge
Bridge
PWM
PWM
PWM1 - 6
Timer1
Timer1
MAT1.0-3
Timer0
Timer0
CAP1.0-3
UART1
UART1
MAT0.0-2
UART0
UART0
CAP0.0-2
SSEL
MOSI
MISO
SCK
SPI
SPI Port
Port
8 pins
GPIO
GPIO
GPIO
SDA
SCL
II22CC
2 pins
VLSI Peripheral Bus (VPB)
CONFIDENTIAL
LPC2101/2/3 Blocks
2/4/8Kb
Fast
Fast
GPIO
GPIO
Local Bus
ARM Local Bus
PLL
PLL
Real
Real Time
Time
Clock
Clock
Vbatt
TDO
ARM
ARM 7TDMI-S
7TDMI-S
AHB Bus
AHB
AHBto
toVPB
VPB
Bridge
Bridge
Watchdog
Watchdog
Timer
Timer
RTC
Osc
4 x MAT3
3 x MAT2
3 x CAP2
4 x MAT1
4 x CAP1
3 x MAT0
Timer0
Timer0 Timer1
Timer1 Timer2
Timer2 Timer3
Timer3
32-bit
32-bit 32-bit
32-bit 16-bit
16-bit 16-bit
16-bit
3 x CAP0
UART1
UART1
8 pins
UART0
UART0
2 pins
SPI/SSP
SPI/SSP
SSEL
SPI
SPI
SCK
MISO
MOSI
SDA
22xxI2I2CC
SCL
GPIO
GPIO
GPIO
AVDD
AVSS
ADC
ADC
10-bits
10-bits
8 Inputs
RTCX1
RTCX2
MOSI
SSEL
X1
X2
ETM
ETM
System
System
Functions
Functions
SCK
MISO
RST
TDI
EICE
Vectored
Vectored
Interrupt
Interrupt
Controller
Controller
AHB Bus
Internal
Internal Flash
Flash
Controller
Controller
SRAM
SRAM
Controller
Controller
TMS
Bootloader,
RealMonitor
TRST
Fast GPIO
FLASH
FLASH
SRAM
SRAM
TCK
8/16/32Kb
CONFIDENTIAL
16KB
16KB
SRAM
SRAM
128/256KB*
128/256KB*
FLASH
FLASH
JTAG
10
E-ICE
Flash
Flash Controller
Controller
// MAM
MAM
RT-Trace
ETM
ETM
ARM
ARM 7TDMI-S
7TDMI-S
System Clock
ARM Local Bus
Real
Real Time
Time
Clock
Clock
System
System
Functions
Functions
PLL
PLL
AHBBridge
Bridge
AHB
SRAM
SRAM
Controller
Controller
Package:
LQFP64
LPC2119, LPC2129,LPC2194
Vss
256KB
Vdd
LPC2129,94
RST
128KB
X2
LPC2119
X1
*Flash size:
AHB Bus
Vectored
Vectored
Interrupt
Interrupt
Controller
Controller
Watchdog
Watchdog
Timer
Timer
AHB
AHBto
toVPB
VPB
Bridge
Bridge
10-bit
10-bit ADC
ADC
AIN0 - 3
RD2
CAN2
CAN2
TD2
RD1
CAN1
CAN1
TD1
PWM
PWM
PWM1 - 6
Timer1
Timer1
MAT1.0-3
GPIO
Timer0
Timer0
CAP1.0-3
GPIO
GPIO
MAT0.0-3
UART0
UART0
CAP0.0-3
UART1
UART1
8 pins
SSEL
MOSI
MISO
SPI
SPI Port
Port
SCK
SDA
SCL
II22CC
8 pins
CONFIDENTIAL
SRAM
SRAM
Controller
Controller
Flash
Flash Controller
Controller
// MAM
MAM
ARM7TDMI-S
ARM7TDMI-S
PLL
PLL
System
Clock
D31:0
A23:0
WE
AHB
Vectored
VectoredInterrupt
Interrupt
Controller
Controller
Watchdog
Watchdog
Timer
Timer
OE
External
External Memory
Memory
Controller
Controller
AHB
AHB
Bridge
Bridge
ARM Local Bus

Real
Real Time
Time
Clock
Clock
System
System
Functions
Functions
ETM
ETM
BLS3:0
E-ICE
RT-Trace
CS3:0
10
144-Pin
Packages
Vss
Vdd
JTAG
RST
256KB
256KB
FLASH
FLASH
X2
16KB
16KB
SRAM
SRAM
X1
LPC2292, LPC2294
n: LPC2292 = 2
LPC2294 = 4
AHB
AHBto
toVPB
VPB
Bridge
Bridge
10-bit
10-bit
ADC
ADC
AIN0 - 7
CANn
CANn
RDn
...
TDn
RD1
CAN1
CAN1
TD1
PWM
PWM
PWM1 - 6
Timer1
Timer1
MAT1.0-3
GPIO
Timer0
Timer0
CAP1.0-3
GPIO
GPIO
MAT0.0-3
UART0
UART0
CAP0.0-3
UART1
UART1
8 pins
SPI1
SPI1
4 pins
SPI0
SPI0
4 pins
SDA
SCL
II22CC
8 pins
VPB
CONFIDENTIAL
Test/Debug
SRAM
SRAM
Controller
Controller
Memory
Memory
Accelerator
Accelerator
Trace
Trace
Vss
Vdd
RST
System Clock
AHB
Local Bus
Real
Real Time
Time
Clock
Clock
System
System
Functions
Functions
PLL
PLL
ARM
ARM 7TDMI-S
7TDMI-S
X2
X1
TDO
TDI
TCK
TMS
0/128/256
0/128/256KB
KB
FLASH
FLASH
TRST
16KB
16KB//64KB
64KB
SRAM
SRAM
RTCK
LPC2220 Flashless 72 MHz
Vectored
Vectored
Interrupt
Interrupt
Controller
Controller
AHB
AHBto
toVPB
VPBBridge
Bridge
Watchdog
Watchdog
Timer
Timer
External
External
Memory
Memory
Controller
Controller
CS 3:0
A 23:0
BLS 3:0
OE,WE
D 31:0
PWM
PWM
PWM1 - 6
Timer1
Timer1
MAT1.0-3
Timer0
Timer0
CAP1.0-3
GPIO
GPIO
MAT0.0-2
ADC
ADC
CAP0.0-2
0/2x
0/2x
CAN
CAN
GPIO
UART1
UART1
8 pins
UART0
UART0
8 pins
SSEL
MOSI
MISO
2xSPI/SSP
2xSPI/SSP
SCK
SDA
SCL
II22CC
2 pins
Package: LQFP144
CONFIDENTIAL
Test/Debug
SRAM
SRAM
Controller
Controller
Memory
Memory
Accelerator
Accelerator
Trace
Trace
Real
Real Time
Time
Clock
Clock
Vbat
Watchdog
Watchdog
Timer
Timer
Vss
Vdd
RST
BBrown
rownO
OututDDetect
etect
PPower
owerO
OnnRReset
eset
System Clock
Local Bus
32 kHz
System
System
Functions
Functions
PLL
PLL
ARM
ARM 7TDMI-S
7TDMI-S
X2
X1
TDO
TDI
TCK
TMS
RTCK
32512
32512KB
KB
FLASH
FLASH
832KB
832KB
SRAM
SRAM
TRST
LPC213x Block Diagram
and AHB
AHB
AHBto
toVPB
VPBBridge
Bridge
Vectored
VectoredInterrupt
Interrupt
Controller
Controller
LPC2131, LPC2132
NOT
ONLY ONE
LPC2131
PWM
PWM
PWM1 - 6
MAT1.0-3
Timer1
Timer1
CAP1.0-3
Timer0
Timer0
MAT0.0-2
GPIO
GPIO
CAP0.0-2
DAC
DAC
GPIO
ADC0/1
ADC0/1
1-10-bit
UART1
UART1
2x8 pins
UART0
UART0
8 pins
SSEL
MOSI
MISO
SSP
SSP Port
Port
SCK
SSEL
MOSI
SCK
SCL
SDA
MISO
SPI
SPI Port
Port
2
2x
2xII2CC
2 pins
Package: LQFP64/HVQFN64
CONFIDENTIAL
LPC213x Series Overview

60 MHz Operation (54MIPS)
from both on-chip Flash and SRAM
2 I2C, 2 UARTs, 1 SPI, 1 SPI/ SSP
Two 8-channel 10-bit ADCs
One 10-bit DAC
4 Timers (Capture/Match/PWM/WDT)
47 I/O pins (5V tolerant)
3.3V Single-Voltage Supply
32KHz RTC, BOD, POR
User-code security
Real-time Debugging & Trace
* Available Q1 2005
ISP, IAP, Parallel Programmer Support

Tiny Packages: QFP64 (10 x 10 x 1.4 mm), HVQFN64 (9 x 9 x 0.85 mm)
CONFIDENTIAL

Single Supply Voltage
CPU operating voltage range of 3.0V to 3.6V (3.3V +/- 10%) with 5 Volt tolerant I/O
pads.
Brown Out Detection (BOD @ 2-stage monitoring of the voltage)
Stage 1: Vdd < 2.9V, the Brown-Out Detector (BOD) asserts an interrupt signal to the
VIC (Vectored Interrupt Controller).
Stage 2: Vdd < 2.6 V LPC213x will be reset to prevent alteration of the Flash as
operation of the various elements of the chip would otherwise become unreliable due to
low voltage.
Power On Reset (POR)
The BOD circuit maintains this reset down below 1V, at which point the Power-On Reset
circuitry maintains the overall Reset.
CONFIDENTIAL

RTC with additional crystal pins
CONFIDENTIAL

RTC:
Can be clocked by a separate 32.768KHz or by prescaler divider
based on VPB clock
So RTC can run in Power Down mode
Has got its own supply pin Vbat which can be connected to battery
or to the (2.0 3.3 3.6 V) supply.
Typical power consumption is 14-20uA (@25 degree, with Vbat 2.5
to 3.6V respectively) when the device is in Power Down Mode
CONFIDENTIAL
Test/Debug
SRAM
SRAM
Controller
Controller
Memory
Memory
Accelerator
Accelerator
ETM
ETM
ARM
ARM 7TDMI-S
7TDMI-S
System Clock
PLL
PLL11
USB Clock
PLL
PLL22
32 kHz
Real
Real Time
Time
Clock
Clock
Vbat
Vss
Vdd
RST
System
System
Functions
Functions
BBrown
rownO
OututDDetect
etect
PPower
owerO
OnnRReset
eset
VIC
VIC
Local Bus
X2
X1
TDO
TDI
TCK
TRST
64-512
64-512KB
KB
FLASH
FLASH
16-32KB
16-32KB
SRAM
SRAM
TMS
LPC2142/44/46/48 Block Diagram
AMBA AHB Bus

88KB
KBSRAM
SRAM
shared
sharedw/
w/DMA
DMA
AHB
AHBto
to
VPB
VPB
Bridge
Bridge
Watchdog
Watchdog
Timer
Timer
(LPC2148
(LPC2148only)
only)
D+
DUp_LED OR
Connect
Vbus
USB
USB2.0
2.0Full
Full
Speed
SpeedDevice
Device
w/
w/ DMA
DMA
Has 1.8V Regulator. Only 3V input needed
PWM
PWM
PWM1 - 6
MAT x 8
Timer0/1
Timer0/1
CAP x 8
Modem
pins (6)
UART0/1
UART0/1
Tx/RX 0,1
DAC
DAC
1-10-bit
ADC
ADC0/1
0/1
6+8 pins
Fast
Fast I/O
I/O
GPIO
46 max
SSEL
MOSI
MISO
SSP
SSP Port
Port
SCK
SSEL
MOSI
MISO
SCK
SPI
SPI Port
Port
SDA
II22CC0/1
0/1
SCL
64-pin LQFP
CONFIDENTIAL

60 MHz Operation from both on-chip
Flash and SRAM
2 I2C, 2 UARTs, 1 SPI, 1 SPI/ SSP
Up to 14-channels 10-bit ADCs
One 10-bit DAC
4 Timers (Capture/Match/PWM/WDT)
45 I/O pins (5V tolerant)
3.5 times faster than older I/O!
Spec
LPC2142
LPC2148
Internal
Flash
64 KB
512 KB
Internal
SRAM
16 KB
32 KB + 8
KB shared
10-bit ADC
1 x 6-chan
1 x 8-chan
32KHz RTC with Vbat input

Brown Out Detect, Power On Reset
User-code security
Real-time Debugging & Trace
ISP, IAP, Parallel Programmer Support
1 x 6-chan
UARTs
2 x 16C550 2 x 16C550
(one with auto
CTS/RTS plus
fractional baud
rate divisor)
Tiny Packages: LQFP64 (10 x 10 x 1.4 mm),

HVQFN64 (9 x 9 x 0.85 mm)
CONFIDENTIAL
LPC214x - USB Features

USB 2.0 Full Speed Device
Supports 32 physical (16 logical ) endpoints
Supports Control, Interrupt, Bulk and Isochronous endpoints
2kB of endpoint RAM for communication only (not general purpose)

8kB block of general purpose SRAM usable by USB DMA (LPC2148
only)
USB controller has dedicated PLL (functionally same as other PLL)
USB registers are accessed via the VPB bus, but the 8kB block is
accessible via the AHB bus
Customer can choose between the UP_LED (Good LinkTM) OR the
CONNECT (Soft ConnectTM) functionality
CONFIDENTIAL
Extending the success to LPC214x

LPC213x Features:
Fast Embedded Flash: Up to 512K Bytes of nearly 60 MHz zero wait
state execution from 128-bitx2 wide Flash with Memory Acceleration
Single-voltage supply: on-chip DC-DC converter takes a single 3.3V supply with
POR and BOD capabilities
Many standard peripherals: Real-time-clock with power domain, SPI, I2C, UARTS,
Timers
LPC214x Adds:
USB 2.0 Full-speed 12 Mbits/sec with full USB standard compliance and DMA
Fast I/O Capability; speeds up Software controlled I/O by 3.5X, up to 15Mhz
port-pin toggling frequency
2 10-bit ADCs and a 10-bit DAC with individual result registers
Enhanced UART with hardware handshake plus fractional baud rate divider. ->
crystal frequency can be set to a independent value of to the baud rate generator
clock
CONFIDENTIAL
2 10-bit Analog-to-Digital Converters with:

400 Kbits/Sec Sampling frequency with 8 Channels
Each Channel has its own Result Register thus reducing CPU Interrupt
Overhead by a factor of 8
ADCs can Operate in Burst Mode with autonomous signal acquisition
ADCs can be synchronized (e.g. for simultaneous current & voltage
measurement) and triggered by an input pin or Timer match
ADC Inputs
ADC Clock
(CLKS Bits)
Select Multiple Channels

ADCR (7:0)
1-8
Input Scan
(SEL Bits)
ADDR0
n-bit ADC
(n Clocks/Conv)
ADDR1
ADDR7
CONFIDENTIAL
NXP USB versus Competition

USB Standard
Philips
Atmel SAM7S64
ST STR71X
16
Control,
Interrupt,Bulk,
Isochronous
Control,
Interrupt,Bulk,
Isochronous
Control,
Interrupt,Bulk,
Isochronous
Control,
Interrupt,Bulk,
Isochronous
Max. Control Buffer size.
64 bytes
64 bytes
64 bytes
64 bytes
Max. Interrupt Buffer Size
64 bytes
64 bytes
64 bytes
64 bytes
Max. Bulk Buffer Size
64 bytes
64 bytes
64 bytes
64 bytes
1023 bytes
1023 bytes
64 bytes
512 bytes
Yes
No
No
Bi-directional* Endpoints
supported
16 max/device
Modes Supported
Max. Isoch. Buffer Size

DMA Capability
* Separate input/output
CONFIDENTIAL
LPC2880/8 Family for

MP3 player and audio management best fit
LPC2880/88 Blocks
ROM
ROM
Controller
Controller
ARM Local Bus
PLLPLLUSB
USB
RTC
Osc
TDO
TDI
SEL
AHB Bus
HS
HSUSB
USB
With
With
DMA
DMA
GP
GPDMA
DMA
Controller
Controller
Watchdog
Watchdog
Timer
Timer
AHB
AHBto
toAPB
APB
Bridges
Bridges0,
0,1,
1,2,
2,33
(1)
LPC2888 only
CONFIDENTIAL
Stereo audio out
Stereo audio in
16bit
16bit
PWM
PWM CODEC
CODEC
PWM1 - 6
MAT1.0-3
Timer1
Timer1
CAP1.0-3
MAT0.0-3
Timer0
Timer0
CAP0.0-3
MCLK
SD/MMC
SD/MMC
card
card
MD[3:0]
RTS, CTS
2x
UART
UART
With
With
IrDA
IrDA
Txd, Rxd
SPI
SPI
IC
MOSI
LCD
LCD
SSEL
I22C
MISO
GPIO
GPIO
85x
85x
LCD Bus
ADC
ADC
10-bits
10-bits
GPIO
4 Inputs
DATO, BCKO,
DCLKO,WSO
IS
IS
In/Out
In/Out
TCK
Real
Real Time
Time
Clock
Clock
SDA
RTCX1
RTCX2
DATI
ARM
ARM 7TDMI-S
7TDMI-S
8KB
8KB Cache
Cache
SCL
X1
X2
BCKI, WSI
E-ICE
System
SystemFunctions
Functions
BO,
BO,
PLLPOR
sys
POR
RST
Vectored
Vectored
Interrupt
Interrupt
Controller
Controller
External Static Memory

Controller
(SDRAM/Flash/SRAM)
AHB Bus
Internal
Internal Flash
Flash
Controller
Controller
SCK
SRAM
SRAM
Controller
Controller
TMS
1MB
64k
TRST
Boot
Boot
ROM
ROM
FLASH
FLASH
(1)
Local Bus
SRAM
SRAM
180 pins
LPC2800 Family
Advanced and Flexible Memory Capability:
On-chip: 1Mbyte of Flash, 64KB of RAM, and 32KB of ROM
External Memory Controller for SDRAM, NOR and NAND Flash, and SRAM
8KBytes of Cache for enhanced performance from external memory
LPC2800 Peripherals:
480 Mbits/sec High-Speed USB device with on-chip PHY
Multi-Media Card, I2S, and LCD controller interfaces
General Purpose DMA
ATA interface
LPC2800 Power Supply sub-systems:
On-chip High-efficiency Switching regulator and Linear Regulators allow:
Operation from single AA(A) Battery cell (0.9 to 1.6V)
Operation from 5V USB input
CONFIDENTIAL
LPC2800 Key Features (1)

On-chip 1Mbyte of flash on LPC2888 (0Kbyte on LPC2880), 64Kbyte RAM, 8
Kbytes cache
Boot ROM allow execution of Flash Code, external code, or flash programming
via USB
External Memory Controller for SDRAM, NOR and NAND flash and SRAM.
8Kbyte of cache for enhanced performance from external memory.
480 Mbits/sec High-Speed USB with on-chip PHY
LCD Interface glue logic
8 channels General Purpose DMA, (can be connected to the LCD interface too)
SD/MMC Card Interface
10Bit A/D converter + 16 Bit A/D and DA converters with amplification and gain
control
UART with fractional baud rate generator, IrDA IIC and IIS interfaces
CONFIDENTIAL
LPC2800 Key Features (2)

Innovative Event Router allows interrupt, power-up- and clock start
capabilities from up to 107 sources. Each signal can act as an interrupt
source, or a clock enable or reset source for the LPC2880/88 modules
Advanced clock generation: CPU clock can be obtain from the RCT
32Khz clock now
Integrated DC/DC converter can generate all required voltages from a
single battery or from USB power
CONFIDENTIAL
LPC2300/24000 Families
32-bit ARM7 Products
512 KB
Flash
ARM7TDMI-S
Internal
SRAM
Controller
Internal
Flash
Controller
16 KB
SRAM
ARM7 Local Bus
MII
or
RMII
AHB2
Ethernet
MAC with
DMA
16 KB
SRAM
AHB
Bridge
AHB
Bridge
AHB to
Master
Port AHB Bridge
APB
Divider
Slave
Port
RST
Xtal2
Xtal1
Trace
Signals
TDO
TDI
TCK
Test/Debug Interface
Emulation Trace
Module
64 KB
SRAM
TMS
TRST
Block Diagram LPC23xx/24xx (1/2)
PLL
System
Functions
System
Clock
Internal RC
Oscillator
Vectored
Interrupt
Controller
External
Memory
Controller
GP DMA
Controller
USB with
4KB RAM
& DMA
A[23:0],
D[31:0],
etc.
AHB1
D+, D-,
etc.
AHB to
APB Bridge
APB
CONFIDENTIAL
Block Diagram LPC23xx/24xx (2/2)

APB
EINT3:0
4 x 4 x CAP
4 x 4 x MAT
External Interrupts
Capture / Compare
Timers 0, 1, 2, 3
2 x 6 x PWM
PWM0, 1
P0,1,...
General Purpose I/O
Ain7:0
A/D Converter
Vbat
Power Domain 2
X1
X2
RTC
Oscillator
SPI, *SSP0 Interface

(no DMA on SPI)
2 x 4 x CAP
2 x 4 x MAT
Aout
*I2S Interface
*SSP1 Interface
SCK0
MOSI0
MISO0
FS/SSEL0
SCK1
MOSI1
MISO1
FS/SSEL1
MCICLK, MCIPWR
*SD/MMC Card
Interface
MCICMD, MCIDAT3:0
UART0, 2, 3
TxD0,2,3
RxD0,2,3
D/A Converter
TxD1
2 KB Battery RAM
Real Time Clock
RXCLK, TXCLK
RXWS,TXWS
RXSDA,TXSDA
RxD1
DTR, RTS
DSR, CTS, DCD, RI
UART1
Alarm
Watchdog Timer
CAN Channels 1, 2
RX2, 1
TX2, 1
System Control
I2C Interfaces 0, 1, 2
SCL0, 1, 2
SDA0, 1, 2
* : Peripherals supported by the GP DMA Controller
CONFIDENTIAL
Features: Core
72 MHz ARM7TDMI
Advanced Vectored Interrupt Controller (32 vectors, 16 priorities)
Single 3.3V power supply (3.0V to 3.6V).
On-chip DC/DC converter for internal 1.8V
4 reduced power modes, Idle, Sleep, Power Down, and Deep Power Down.
Processor wakeup from Power Down mode via any interrupt able to operate during
Power Down mode (includes external & GPIO interrupts, RTC, Ethernet wakeup).
On-chip Power On Reset, and Brownout detect

with separate thresholds for interrupt and forced reset.
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
4 MHz internal RC oscillator that is the default system clock.
On-chip PLL allows CPU operation up to the maximum CPU rate without the
need for a high frequency crystal. May be run from the main oscillator, the
internal RC oscillator, or the RTC oscillator.
CONFIDENTIAL
System Architecture Issues

Challenges to preventing bottlenecks:
Ethernet requires support of 2 concurrent 100Mbits/sec data streams with
up to 1500 byte packets
USB & Ethernet Streams are asynchronous and must both be supported
including Isochronous mode USB (1024 byte data bursts)
CAN, SPI, SSP, I2C, SDIO, I2S, UARTs, Timers, PWMs, ADC, DAC, etc,
must also be supported but these are all lower bandwidth with smaller
packet sizes than Ethernet & USB (increases MCU core involvement)
CPU, Ethernet, and USB clock domains (72, 25/50, and 48 MHz) are all
separate and need to communicate through memory
Multi-ported memory is expensive, complex, and not desirable
CONFIDENTIAL
42
The Goals of the LPC2300 Family

Preventing overflow, underflow, and contention:
Manage multiple Asynchronous high-speed channels with no channel
performance bottlenecks
Provide Ethernet, USB, CAN, UART, SPI, I2S, and I2C channels
Offer a one chip system for high performance and low power at a low cost
Include industry-leading Embedded Flash operating at SRAM speeds combined
with ECC (error correction) for the best performance and power, security and
reliability
Develop a large derivative family in different packages and with different
capabilities and memory configurations at different price points, but allowing for
easy transitions between family members (preserve code re-use)
CONFIDENTIAL
43
Building the LPC2300 CPU & Memory

ARM7TDMI-S Processor 72 MHz
Up to 512 KB Flash on-chip Flash
zero wait-state (execute code from Flash or SRAM)

128-bit wide bus with patented Memory Accelerator Module (MAM)
8-bits Error Correction Code (ECC) for every 128-bit word
Automotive qualified Flash process for high reliability
Up to 58 KB on-chip Static RAM (all portions accessible by CPU and

DMA)
8 KB 32 KB SRAM exclusively for CPU
16 KB for Ethernet buffering
8 KB for USB device (code or data)
2 KB for RTC is for data only
Additional 4 KB USB FIFO buffer
Advanced Vectored Interrupt Controller (VIC) 32 IRQ sources

Emulation Trace Module supports real-time trace
Low power - 4 reduced power modes including Deep Power Down
Start with the best embedded Flash in the market

CONFIDENTIAL
44
Bus Bandwidth required for Industrial network

SDRAM/SRAM/NOR interface
Ethernet Connection to
Backbone and
Remote Networks
Micro
with
Embedded
Flash
USB and SDIO for storage and

peripherals
Local CAN Device Cluster
Bus bandwidth usage at 72 MHz

Peripheral
AHB Bus
bandwidth %
Cumulative
AHB
Bandwidth
Ethernet
50
50
USB
54
Ext, DRAM
20
74
SSP
79
I2C(2)
81
CAN (2)
84
UARTS(2)
88
ADC
96
Sensors, Actuators, Drives, Switches etc.
More than 60% usage of bus

bandwidth causes collisions
Loaded system bandwidth at
72Mhz is 96% for application
Conclusion:
1 AHB Bus is not sufficient
Multiple Busses and concurrent
DMA processing is required
CONFIDENTIAL
45
Building the LPC2300 Dual AHB Bus

Two separate but not isolated AHBs
Any bus can still reach any other bus through bridges when needed
512 KB
Flash
Trace
Signals
TDI
TDO
TCK
ARM7TDMI-S
Internal
SRAM
Controller
Internal
Flash
Controller
Emulation Trace
Module
64 KB
SRAM
TMS
TRST
High-bandwidth peripherals on different AHBs will not overwhelm the CPU or

other peripherals
16 KB
SRAM
ARM7 Local Bus
AHB2
16 KB
SRAM
AHB
Bridge
AHB
Bridge
AHB to
Master
Port AHB Bridge
APB
Divider
Vectored
Interrupt
Controller
AHB1
Slave
Port
AHB to
APB Bridge
No communications traffic jams!!

CONFIDENTIAL
46
The LPC2300 Advantage - parallel buses

Concurrent operations become possible:
Ethernet packet reception and transfer to SRAM
CPU Instruction Fetch
USB packet reception and transfer to SRAM
512 KB
Flash
Internal
SRAM
Controller
Internal
Flash
Controller
ARM7TDMI-S
AHB2
Ethernet
RMII
Ethernet
MAC with
DMA
16 KB
SRAM
AHB
Bridge
AHB
Bridge
AHB to
Master
Port AHB Bridge
APB
Divider
Slave
Port
RST
Xtal1
8 KB
SRAM
ARM7 Local Bus
Xtal2
Trace
Signals
TDI
TDO
TCK
Emulation Trace
Module
32 KB
SRAM
TMS
TRST
Dedicating AHB Bus to Ethernet is required to guarantee 100 Mbits/sec Ethernet

throughput without contention with other peripherals
PLL
System
Functions
System
Clock
Internal RC
Oscillator
Vectored
Interrupt
Controller
AHB1
GP DMA
Controller
USB with
4KB RAM
& DMA
D+, D-,
etc.
AHB to
APB Bridge
APB
USB
CONFIDENTIAL
47
Features: I/O Peripherals

160 GPIO pins, all implemented as fast GPIOs, with 64 GPIO interrupts (plus 4
other external interrupts).
10 bit A/D Converter with input multiplexing among 8 pins.
10 bit D/A converter.
Four general purpose Timers with capture inputs, compare outputs, and
external count inputs.
Two linkable PWM / Timer blocks with support for 3 phase motor control with
"dead time". Each PWM has an external count input.
Real Time Clock with separate power pin, alarm output, and 2K SRAM.
Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.
CONFIDENTIAL
Features: Serial Interfaces

Ethernet MAC with associated DMA controller.
These functions reside on an independent AHB bus.
USB Device, Host (OHCI compliant), and OTG block with on-chip
Host/Device PHY and associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem
control I/O, one with IrDA support, all with FIFO.
CAN controller with two channels.
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is
an alternate for the SPI port, sharing its interrupt and pins.
Three I2C Interfaces. The second and third I2C interfaces are
expansion I2Cs with standard port pins rather than special open drain
I2C pins.
I2S (Inter-IC Sound) interface for digital audio input or output.
CONFIDENTIAL
Power Options
Power options:
On-chip DC-DC converter supplies 1.8V power to all internal logic, except
in the RTC power domain.
1.8V power can be supplied from off-chip for some pinouts.
Power reduction modes:

Idle mode.
Power Down mode.
Sleep mode.
Deep Power Down mode.
Power reduction modes are entered via an encoding of the IDL and PD
bits in PCON, plus an additional new power control bit.
CONFIDENTIAL
Idle Mode
CPU is halted, reducing power used by:
The CPU itself.
Memories and their controllers used by the CPU.
Internal buses used by the CPU.
Peripheral clocks and functions continue to run.

All registers and memories retain their state.
Wakeup from any enabled interrupt, or Reset.
CONFIDENTIAL
Sleep Mode
All clocks are stopped to the CPU and peripherals.
If enabled, the main oscillator and PLL are shut down.
All dynamic operation of the device is suspended.
The DC-DC converter remains operational.
The Flash memory remains on, allowing for fast wakeup.

Wakeup from any enabled interrupt that can occur without clocks, or
Reset.
CONFIDENTIAL
Power Down Mode

All clocks are stopped to the CPU and peripherals.
If enabled, the main oscillator and PLL are shut down.
All dynamic operation of the device is suspended.
The DC-DC converter remains operational.
The Flash memory is turned off.

Wakeup from any enabled wakeup source that can occur without
clocks, or Reset.
CONFIDENTIAL
Deep Power Down Mode

Similar to Power Down mode, but the DC-DC converter is turned off.
This is only useful if 1.8V power is supplied externally.
Device state is lost (but, see RTC and Battery RAM).
Wakeup can only be accomplished by a chip reset or an Alarm interrupt

from the RTC.
During Deep PD mode, power may be removed from the entire device,
except for the RTC.
Restoring power causes a POR.
Wakeup requires that external circuitry restores power.

The alarm output of the RTC can signal external circuitry when power
should be restored, or some external means may be used.
CONFIDENTIAL
Wakeup from Power Down or Sleep Mode

External interrupts
(EINT0 through EINT3) and GPIO interrupts
Ethernet wakeup
(portions of the Ethernet block receive clocks from the external PHY)
USB or CAN activity (pin state change)

Brown Out Detect
RTC Alarm
CONFIDENTIAL
Wakeup from Power Down or Sleep Mode

External interrupts
(EINT0 through EINT3) and GPIO interrupts
Ethernet wakeup
(portions of the Ethernet block receive clocks from the external PHY)
USB or CAN activity (pin state change)

Brown Out Detect
RTC Alarm
CONFIDENTIAL
RTC & Battery RAM

APB
RTC Power Domain

Vbat
X1
X2
RTC
Oscillator
2 KB Battery RAM
Real Time Clock
Alarm
CONFIDENTIAL
NicheLite for LPC by Interniche

NicheLite for LPC is a fully featured TCP/IP stack
Requires as little as 12 KB of code.
Support for the following protocols:
Address Resolution Protocol (ARP), Internet Protocol (IP), Internet Control Message Protocol
(ICMP), User Datagram Protocol (UDP), Transmission Control Protocol (TCP), Dynamic Host
Configuration Protocol (DHCP) Client, Domain Name System (DNS) Client, Bootstrap Protocol
(BOOTP), Trivial File Transfer Protocol (TFTP)
Includes NicheTask a cooperative multi-tasking scheduler.

Supports InterNiche's Light Weight API and a Zero-Copy option.
Single Ethernet interface with device drivers optimized for the LPC2300 and LPC2400
Example applications (TFTP Client, TFTP Server, HTTP Listener)
Source code is free to NXP customers

License - Unlimited use with NXP LPC2000 and LPC3000 microcontrollers only
Support from Interniche at sales@interniche.com
CONFIDENTIAL
58
LPC24xx
LPC24xx features beyond those offered in the LPC23xx.
More RAM
Ethernet MII interface (in addition to RMII)
USB Host and OTG functionality
External Memory Interface with additional External Memory Controller circuitry
Additional GPIO
Additional PWM
CONFIDENTIAL
59
LPC24xx
Announcement on the web
Datasheets by email (LogicPG@NXP.com)
2 Devices:
LPC2458: 512KB flash, 98KB SRAM, Ext bus
(16-bit), TFBGA180
LPC2468: 512KB flash, 98KB SRAM, Ext bus
(32-bit), LQFP208 & TFBGA208
Will be available in Q1 2007

LPC24xx Leaflet
CONFIDENTIAL
LPC3000 Family
32-bit ARM9 Products
NXP Standard Microcontroller

The Next Generation ..
LPC3000
CONFIDENTIAL
Block Diagram LPC3180

External
Memory
Interfaces
90nm Process
208 MHz Core freq.
1.2V core operation
3.3V I/O
CPU subsystem
ETB
ETM9
I-Cache
32kB
D-Cache
32kB
VFP9
On-Chip
Memory
ARM926EJ
32KB I- & D- caches
Instr
NAND
Flash
Data
64KB TCM SRAM
Mem
Stick
ROM
SD
Card
64 KB
SRAM
DRAM
control
(Tightly-Coupled Memory)
Up to 1MB SRAM
Bus matrix (Multi-layer AHB)
(On-Chip Memory)
Standard E-ICE
JTAG Interface
6KB ETB
(Embedded Trace Buffer)
256-pin TFBGA package
Interrupt
Controller
DMA
Controller
Timers
Watchdog
I2C A
SysCtrl
Keyscan
PLLs
Power
control
System Functions
I2C B
A/D
RTC
Other
Peripherals
USB
OTG
UART
1-5,7
UART6
IrDA
GPIO
PWM
SPI
Communication
Peripherals
CONFIDENTIAL
Technology Announcement
First ARM9 family-based microcontrollers in 90nm technology
Press release done on Feb 23th during the Embedded World Show Nuremberg:
LPC3000 Family based on 90nm technology industrys first 90nm ARM9* familybased 32-bit microcontroller family.
Based on NXP Nexperia platform using the ARM926EJ-S* core
Features:
Several power management benefits
Peripherals such as integrated USB On-the-Go (OTG) and full USB Open Host
Controller Interface (OHCI) host
Multi-level NAND Flash interface
Operating speed at 200MHz
Standard communication peripherals like up to 7 UARTs, SPI, I2C, USB, real-time
clock, Ethernet - to follow.
Floating point Vector Coprocessor
100mW power consumption @200Mhz with all peripherals switched on
CONFIDENTIAL
Nohaus LPC3000 Evaluation Board

A Single power supply input (5.0V), regulated on board
to provide all the necessary EVB voltages.
User Reset pushbutton switch.
20 Way JTAG/ETB connector.
32M (8M x 32) Bytes of SDRAM.
32M (32M x 8) Bytes of NAND FLASH.
1 - LCD Module with Philips PCF8558 built in.
1 - SD Card connector.
3 - USB connectors (USB A Receptacle Connector for
USB Host; USB B Receptacle Connector for USB Device;
USB Mini AB Receptacle Connector for USB OTG) with
Philips ISP1301.
3 - UART (RS232) physical interface circuits connected
to standard PC style DB9 female connectors.
4 - User input pushbutton switches.
2 - User output LEDs.
http://www.nohau.com/emularm/lpc3000_board.html
CONFIDENTIAL
phyCORE-ARM9/LPC3180
ARM9 with Vector Floating Point Unit
Technical Features
Carrier Board in EURO-card dimensions (100 x 160 mm)
RS-232: 2x female DB-9 connectors support UART5 and UART2
USB (Host/Device/OTG) connectors:
Standard A type connector for USB host functionality, Standard B type connector for USB device functionality
miniAB type connector for OTG functionality
JTAG 2.54mm pitch, 16-pin connector for JTAG debugging interface
SD Card slot
Reset push button, Boot jumper ,2x user buttons
4x user LEDs with jumpers to separate from I/O lines
Battery receptacle for LPC3180 Real-Time Clock and SRAM back-up
Keyboard 2x8 2.54mm pitch connector for keyboard interface
Single Board Computer Module
1x potentiometer connected to one A/D input
PART #: PCM-031
5V. low-voltage socket for power supply connectivity

3V. and 5V. low voltage supplies for external devices and subassemblies
Expansion Bus: address, data, interface and all applicable I/O signals route from implemented phyCORE
module to 2x80-pin Molex connectors, enabling connectivity to Add-On hardware
Memory configuration:
SDRAM: 16 to 64 MB synchronous SDRAM, max. access time of 10ns, 32-bit organization
Flash: 16 to 128 MB NAND-Flash in 8-bit mode
Serial: 1 to 32 KB IC-EEPROM
PART #: PCM-031
Configuration:
208 MHz, 32 MB SDRAM,32 MB Flash, 32 KB EEPROM, USB OTG, JTAG interface
$249.00 Module only
$349.00 basic package : Module + Carrier Board

http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-ARM9LPC3180-Kits.html
Carrier Board
PART #: KPCM-976
CONFIDENTIAL
Tools and support 16/32-bit

ARM7TDMI-S Products
Development Tool Support

EmbeddedICE-RT (JTAG)
Embedded Trace Macrocell (ETM)
Real Time Monitor with Debug Interrupt
Trace
TracePort
Port
Analyser
Analyser
10
JTAG
JTAG
Interface
Interface
Debugger
Trace Tools
E-ICE
(JTAG)
ETM: Embedded
Trace Macrocell
ARM7-S
with RTM
Emulation & Real Time Trace
CONFIDENTIAL
Esacademy Flash Magic

Free Flashmagic Utility from
Esacademy
Features:
Program/Erase Flash
Verify
Blank check
Check ID
Fill Buffer
Save HEX file
Fo more info:
http://www.esacademy.com/
CONFIDENTIAL
Development tools - LPC2100/LPC2200

IAR/NXP board for LPC210x
2x 9-pin D-type Serial communications ports
LEDs can be connected to selected port-pins
3 switches for interrupts, Reset switch
Breakout ports for Logic Analyzer connection
Price projection $149 with 32k compiler
Keil/NXP board for devices with ADC

and optional CAN (LPC2129)
2x 9-pin D-type Serial for serial co. ports
2x 9-pin D-type Serial for CAN
8 status LEDs
Switches for interrupt and Reset
Potentiometer for ADC demos
Price projection $149 with 16k compiler
(no time limit)
CONFIDENTIAL
Ashling ASK-2000 for LPC210x, LPC211x,

LPC212x, LPC22xx
LPC2104, LPC2105, LPC2106,
LPC2114, LPC2119, LPC2124,
LPC2129, LPC2210, LPC2212,
LPC2214, LPC2290, LPC2292 and
LPC2294, LPC213x
Jtag connector available
Price: $295 with LPC2106
Add $90 for LPC2129 or LPC2294
Adapter available for the other
21xx and 22xx derivatives
Emulator integrated in the same
board !
http://www.ashling.com/support/lpc2000/eval_kits.html
CONFIDENTIAL
Keil MCB2130 Evaluation Board LPC2138

2x 9-pin D-type Serial for serial
communications ports
8 status LEDs
Speaker on DAC output
Buttons for interrupts and Reset
Plated-through-hole prototyping matrix
Price: $149 with 16K compiler (no
time limit)
CONFIDENTIAL
IAR KS2103 Evaluation Board

LPC2103 Development board
LPC2103 MCU
Two serial ports
Reset button
In-system programming (ISP) button
Three user-defined buttons
16 fully configurable LEDs
16 character x 2 row LCD screen
Power-on LED
Can be powered via IAR J-Link-KS or
external 9-12V DC power supply (not
included)
Lithium back-up battery holder
20-pin JTAG interface connector
Breakout headers for all pins (suitable for
mounting daughter boards)
20x20 array of plated holes for
prototyping
CONFIDENTIAL
Keil MCB214x Evaluation Board

LPC2148 microcontroller
2x 9-pin D-type Serial for serial
communications ports, power amplifier and
on board loudspeaker
8 status LEDs
Speaker on DAC output
SD Card Interface
Software support for USB
USB Soft Connect feature NOT supported
Price $149.00
CONFIDENTIAL
IAR KS214x Evaluation Board

LCD interface
RS232 ports for UARTs
Push buttons for external interrupts
USB Soft Connect feature
supported
SD card interface for USB
Price $149.00
CONFIDENTIAL
PHYTEC phyCOREARM7/LPC229x
phyCORE-ARM7/LPC229x
PCM-023-SK-2294
10/60 MHz,
1 MB SRAM, 2 MB Flash,
2 KB EEPROM,
SMSC LAN91C111 10/100 Mbit/s
Ethernet,
JTAG interface
$199.00
http://www.phytec.com/sbc/32bit/p
clpc229x.htm
CONFIDENTIAL
MCB23xx Keil for LPC2300 family

Evaluation boards from Keil:
MCB2360 (LPC2364/66/68)
MCB2370 (LPC2378)
Schematic
Code sample on the web
Price: 199$
Two serial interfaces,
a speaker, analog input (via potentiometer),
two CAN interfaces,
LCD, SD card interface
USB, Ethernet,
and eight LEDs make this board a great starting point for your next ARM project.
CONFIDENTIAL
IAR Kick Start Development Kit
for LPC2378
Contains:
LPC2378 development board
IAR J-LINK-KS JTAG debugger with USB connector
IAR Embedded Workbench with a 32KB version of the IAR C/C++ Compiler
IAR PowerPac: 3 tasks (RTOS) and 1 file (Flash File System) evaluation version
20-state version of visualSTATE
lab
i
a
Av
en
e
t th
a
le
Fe
f
do
ry
a
u
br
CONFIDENTIAL
Nohaus LPC2800 evaluation board
SD card Connector
USB connector
LCD Module
16MB SDRAM, 8MB Flash
Headphone jack
Price on Nohaus web site: 995$
http://www.nohau.com/emularm/lpc2800.html
CONFIDENTIAL
ARM Emulators
JTAG emulators
CONFIDENTIAL
Emulator with Trace
http://www.ashling.com/datasheets/armtools.html
Jlink + Trace
CONFIDENTIAL
Debuggers
Pathfinder debugger for
the LP2100
http://www.ashling.com/datasheets/armtools.html
ARM RealView debugger

http://www.arm.com/devtools/ads?OpenDocum
ent&View=defaultBody2.
Seehau debugger ARM

http://www.nohau.com/downloads.html
C-SPY debugger ARM
CONFIDENTIAL
Debuggers
Chameleon Debugger
http://signum.com/Signum.htm?p=ARM.htm
Keil debugger &

simulator Vision3
http://www.keil.com/arm
Universal Debug
Engine (UDE)
MULTI Debugger
CONFIDENTIAL
Integrated Development Environment
RealView
Multi 2000
AsIDE
Vision3
EWARM
CrossWorks
CONFIDENTIAL
Compilers
ARM Compiler
http://www.arm.com/devtools/soft_dev_tools?
OpenDocument.
GHS Compiler
http://www.ghs.com/products/arm_development.html
IAR Compiler
http://www.iar.com/Products/?name=EWARM
GNU GCC
CONFIDENTIAL
ARM RTOS
RTOS Listing and Ported to

Nucleus
Nucleus Tools, Keil

board
CMX
ARM,Keil
Keil ARTX
Keil
COS-II
IAR,Nohau,Keil (appnotes
available online)
FreeRTOS
http://www.freertos.org/
CONFIDENTIAL
RTOS Listing
eCos
Ashling
NicheTask
ThreadX
IAR,ARM
Pumpkin Salvo
Keil
Clinux
See www.uclinux.org
CONFIDENTIAL
RTOS Support
Nucleus from
Accelerated Technology
a Mentor company
ChronOS
from InterNiche
CONFIDENTIAL
ARM Doc and software examples
Free link and tools:

Free GNU C compiler for ARM7 + related manuals
http://www.gnuarm.com/
Free LPC210x software for flash programming at:

http://www.lpc2100.com/
http://www.lpc2000.com/
Link to the ARM processor core documentation directly from ARM site at:
http://www.arm.com/documentation/ARMProcessor_Cores/index.html
NXP ARM selection tools page:

http://www.nxp.com/products/microcontrollers/support/development_tools/tools_by_type/
Yahoo support groups

http://groups.yahoo.com/group/lpc900_users
http://groups.yahoo.com/group/lpc2000/
Free online Introduction to ARM

http://www.techonline.com/community/ed_resource/course/14612/
Free LPC2000 Insider's Guide To The NXP ARM7-Based Microcontrollers
http://www.hitex.co.uk/arm/index.html
CONFIDENTIAL
LPC21xx Driver Support (for free)

Keil (using uVusion + Keil compiler)
USB mem: a Standard Memory Mass Storage driver example

USB audio: an Audio Device driver example
USB HID: a Human Interface Device class driver example
NXP
Virtual COM port: Maps a virtual COM port communication in a USB pipe (see
LPC2000 news group, file section)
MMC driver: MMC memory card driver, application note (see NXP web site,
microcontroller section)
IAR:
USB mouse class driver example

USB MassStorage: Manage a MMC card and a vurtual RAM disk via USB
USB Audio: manage an input and an output audio stream via USB
USB CDC: USB communication device class via virtual COM
CDC = Class Definition for Communication Devices
Rowley :
TCP/IP, uIP stack for the Olimex LPC-E2124 board @ http://www.rowley.co.uk
Free lib: EFSL http://efsl.de (FAT12/16/32 file system with short file names)
Keil and IAR examples dont require any Windows USB class driver. Windows XP
supports all mentioned class drivers. NXP supplies the Virtual COM driver for
Windows XP, IAR supplies the .inf file for the CDC windows driver
CONFIDENTIAL
COMMERCIAL FILE SYSTEM SUPPORT

HCC
Supports fat 16/32
Wear levelling
About 2000 Eur
Keil
Supports Fat 16
8.3 file naming
Part of RTL
IAR
Power PACK
CONFIDENTIAL
USB Masss-storage class drv. and Filesystem relationship

Virtual Drive
Windows FAT16/32
Filesystem APIs
USB Mass storage
class driver
Customer Application
Init_USB()
Defines
device,
interfaces,
endpoints
Open_File()
Read_File()
Write_File()
File system API
File system manager
USB Mass storage

class driver
Write_mem_blk()
Read_mem_blk()
Window low-level
HOST driver
USB HOST
USB device low-level

messages driver
SD, MMC
init
Low Level Memory card driver
USB Device
SD/MMC cards
Ex.:
EFSL,
HCC,
IAR power Pack
Keil RTX FS
CONFIDENTIAL
USB books
USB Design By Example
A pratical Guide to Building I/O devices
John Hyde, Intel University Press
USB complete third edition

Jan Axelson, www.Lvr.com
Lakeview Research
CONFIDENTIAL
ARM-Tools on the NXP website

http://www.semiconductors.NXP.com/products/microcontrollers/support/development_too
ls/tools_by_family/
CONFIDENTIAL
LPC2000 forum
Started by Leon Heller, an engineering consultant from
England: The NXP LPC2100 family of ARM MCUs is
sufficiently different from other ARM variants that I decided
that a forum dedicated to it would be useful.
Direct URL http://groups.yahoo.com/group/lpc2000/
Founded
Nov 17,
2003
Already
about 4000
members!
CONFIDENTIAL
Get the latest Information .......

Product Selection Guide
Datasheets
Production Status
Tools
Application Notes
And much more
http://www.standardics.nxp.com/
products/microcontrollers/
CONFIDENTIAL
Insiders Guide to LPC2000

200 page guide to LPC2000
featuring chapters on:
ARM7 Core
Software Development
System Peripherals
User Peripherals
Keil Tutorial
GNU Tutorial
Perfect for engineers without ARM

experience
http://www.hitex.co.uk/arm/lpc2000book/book_downloadform.html
CONFIDENTIAL
Application examples
CONFIDENTIAL
http://www.jandspromotions.com/philips2005/
CONFIDENTIAL
NXP ARM Design Contest
Magnetometer
Charlie
Ethernet Acquisition
Flash card
NoPC
TAM-TAM
TV-Oscilloscope
Distinctive Excellence
Nuclear Weighing
Measurement
Dual-Axis Level
Sensor
LAURIN
Buckymeter
Duux Babycall
CONFIDENTIAL
Why ARM?
LPC2000 Key Points
ARM7 is an open architecture

Already the preferred 32-bit solution in Automotive, Communication and Industrial
markets.
Same tools for all ARM7 of different manufacturer. Often the same tools can be
used for ARM9/10/11. Customers can save money
ARM is a scalable and uniform architecture. ARM7 is binary code compatible with
ARM9/10. Your customer can chose the right product for its target application
saving time due to the reduced learning curve
Why NXP?
First ARM7TDMI supplier with on-board flash in 0.18 m process, with the largest
ARM7 product portfolio
Memory sizes from 8k up to 1M on-chip flash
Highest flash performance with nearly zero wait states due to internal MAM (Memory
Accelerator Module)
Widest selection of devices and of the integrated peripherals: 4*CAN, 2*ADC, SPI,
I2C)
Lowest pin count and smallest packages available
Price level allows to address mid/high end 16-bit applications, and high end 8 bit
application
CONFIDENTIAL
Hands-On
CONFIDENTIAL
Hands-On Index
Hands-On
1.
Tools Setup
2.
Oscillator / PLL / MAM / GP I/O / Flash
3.
ADC
4.
Interrupts / Timer
5.
UART / CAN
CONFIDENTIAL
Start Keil uVision3

Menu Selection:
Project /
Open Project
Select
Blinky1
Hands-On
Compile Current File
Make Project
Rebuild Project (all)
Open Options Dialog
Start/Stop Debugging
CONFIDENTIAL
Hands-On
Build and Debug
Build Project
Reset
Start Debugging
Run
Halt
Step into
Step over
Performance Analyzer
Signal Analyzer
CONFIDENTIAL
Setup of Logic Analyzer

Logic Analyzer
Setup
Add signal
action
Hands-On
Add New
signal
Here: 10
CONFIDENTIAL
Run Program
View Variables and Registers
Hands-On
Menu:
Peripherals /
GPIO /
Port1
Zoom:
In & Out
CONFIDENTIAL
Hands-On
Run Program on Hardware
Halt
Stop Debugging
Options
Make Settings:
Using JTAG/ULINK
Select Debug Tab
Use
ULINK ARM Debugger
With Flash ISP Utility
Select Utilities Tab

Use External Tool
Modify Command Line
Run Independent
Press Load Button

CONFIDENTIAL
Introduction to the ARM architecture
1.
ARM - The Company
2.
Architecture
3.
Instruction Set
4.
ARM7TDMI-S
5.
Systems
6.
Other ARM cores
7.
NXP Implementation
8.
Q&A
CONFIDENTIAL
ARM Holdings plc. (1)

Established as Advanced RISC Machines Ltd. in 1990 as
a UK based joint venture between Apple Computer, Acorn
Computer Group and VLSI Technology*
Apple and VLSI provided funding
Acorn supplied technology and first 12 engineers
Introduction of ARM6 family in 1991, VLSI initial licensee

In April 1998 listed on the London Stock Exchange and
Nasdaq
*: part of Philips since 1999
CONFIDENTIAL
ARM Holdings plc. (2)

Develops the ARM range of RISC processor cores
Licenses its RISC microprocessor core and SoC IP to a
network of partners; semiconductor and system companies
ARM does not manufacture silicon itself
Also licenses architectural extensions, development tools,
peripheral IP and SoC solutions
ARMs market share of the embedded RISC
microprocessor market is approx. 75% and to date, ARM
Partners have shipped more than one billion ARM corebased microprocessors
CONFIDENTIAL
1.
ARM - The Company
2.
Architecture
3.
Instruction Set
4.
ARM7TDMI-S
5.
Systems
6.
Other ARM cores
7.
NXP Implementation
8.
Q&A
CONFIDENTIAL
Bus Width
ARM7 is a 32-bit architecture
Data pathes and (ARM)
instructions are 32 bits wide
Address Bus
Address Register
Incr.
Von Neumann architecture

instructions and data use the
same 32-bit data bus
Instruction
Decode &
General
Control
Registers
Mult.
There is a subset of 16-bit

instructions (Thumb) optimized
for code density*
Thumb
Decompression
Shifter
ALU
Data Out
Data In
Data Bus
*: from C code
CONFIDENTIAL
Thumb State
Set of instructions re-coded into 16 bits
Improved code density by ~ 30%
saving program memory space
In Thumb state only the program code is 16-bit

wide
after fetching the 16-bit instructions from memory,
they are de-compressed to 32 bit instructions before
they are decoded and executed
all operations are still 32-bit operations
CONFIDENTIAL
Data Types and Alignment

Definitions (Little endian or big endiand are options):
Word
32 bits (four bytes)
Halfword
16 bits (two bytes)
Byte
1
Word
8 bits
1
Word
Halfword
Halfword
Halfword
Halfword
Byte
Byte
Byte
Byte
Byte
Halfword
Word
Byte
Byte
Byte
Halfword
Word
CONFIDENTIAL
Processor Modes
ARM has seven operating modes
1. User
unprivileged mode under which most applications run
2. FIQ
entered, when a high priority (fast) interrupt is raised
3. IRQ
general purpose interrupt handling
4. Supervisor protected mode for the operating system

entered on reset or software interrupt instruction
5. System
privileged mode using the same registers as user mode

(not in ARM architectures 1, 2 and 3)
6. Abort
used to handle memory access violations
7. Undefined
used to handle undefined instructions
CONFIDENTIAL
Registers (1)
An ARM core has 37 registers (32-bits wide)
General purpose registers
1 program counter
30 general purpose registers
Status registers
1 current program status register
5 saved program status registers
These registers are not all accessible at the same time. The processor
state and operating mode determine which registers are available to the
programmer.
CONFIDENTIAL
Registers (II)
Depending on processor mode one of several banks is
accessible. Each mode can access
the program counter r15 (PC)
a particular r13 (stack pointer SP)
a particular r14 (subroutine link register, LR)
a set of r0-r7 registers, and a particular set of r8-r12
the current program status register (CPSR)
Privileged modes (except Sytem mode) can also access

a particular SPSR (saved program status register)
CONFIDENTIAL
Register Overview
FIQ
IRQ
Supervisor
Abort
Undefined
r0
r0
r0
r0
r0
r0
r1
r1
r1
r1
r1
r1
r2
r2
r2
r2
r2
r2
r3
r3
r3
r3
r3
r3
r4
r4
r4
r4
r4
r4
r5
r5
r5
r5
r5
r5
r6
r6
r6
r6
r6
r6
r7
r7
r7
r7
r7
r7
r8
r8_fiq
r8
r8
r8
r8
r9
r9_fiq
r9
r9
r9
r9
r10
r10_fiq
r10
r10
r10
r10
r11
r11_fiq
r11
r11
r11
r11
r12
r12_fiq
r12
r12
r12
r12
r13 (SP)
r13_fiq (SP)
r13_irq (SP)
r13_svc (SP)
r13_abt (SP)
r13_und (SP)
r14 (LR)
r14_fiq (LR)
r14_irq (LR)
r14_svc (LR)
r14_abt (LR)
r14_und (LR)
r15 (PC)
r15 (PC)
r15 (PC)
r15 (PC)
r15 (PC)
r15 (PC)
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR_fiq
SPSR_irq
SPSR_svc
SPSR_abt
SPSR_und
Thumb stae High

registers
Thumb stae Low

registers
User and System
CONFIDENTIAL
Registers in Thumb State

The Thumb state register set is a subset of the ARM state set. The
programmer has direct access to:
eight general registers
r0 - r7
the program counter
PC
a Stack pointer
SP
a Link register
LR
the current program status register
CPSR
In Thumb state, the high registers (r8 - r15) are not part of the standard
register set. The assembly language programmer has limited access to
them, but can use them for fast temporary storage
CONFIDENTIAL
Thumb vs. ARM

r0
r0
r1
r1
r2
r2
Thumb state
r3
r3
Low registers
r4
r4
r5
r5
r6
r6
r7
r7
Thumb state
Thumb
ARM
State
State
r8
r9
r10
r11
High registers
r12
r13 (SP)
r13 (SP)
r14 (LR)
r14 (LR)
r15 (PC)
r15 (PC)
CPSR
CPSR
SPSR
SPSR
CONFIDENTIAL
Program Status Register (1)

31 30 29 28 27
24 23
Condition
code flags
16 15
Reserved
0
mode
Control bits
Condition Code Flags

N: Negative or less than
Z: Zero
C: Carry or borrow or result of the shift operations
V: Overflow
To not disturb reserved bits, a read-modify-write strategy should be applied to
change PSR bits.
CONFIDENTIAL
Program Status Register (2)

31 30 29 28 27
24 23
Condition
code flags
16 15
mode
Mode Bits
I: IRQ interrupts disable
10000
User
F: FIQ interrupts disable
10001
FIQ
10010
IRQ
10011
Supervisor
10111
Abort
11011
Undefined
11111
System
T Bit
Thumb mode (when set)
ARM mode (when cleared)
Control bits
Reserved
Interrupt Disable Bits
CONFIDENTIAL
Program Counter (r15)

When the processor is executing in ARM state
all instructions are 32 bits wide
all instructions must be word aligned
bits [31:2] contain the PC, bits [1:0] are zero
(instructions cannot be halfword or byte aligned)
When the processor is executing in Thumb state

all instructions are 16 bits wide
all instructions must be halfword aligned
bits [31:1] contain the PC, bit [0] is zero
(instructions cannot be byte aligned)
CONFIDENTIAL
Exception
Exceptions result whenever the normal flow of a
program has to be halted temporarily, for example
to service an interrupt from a peripheral. Before
attempting to handle an exception, the
ARM7TDMI-S preserves the current processor
state so that the original program can resume
when the handler routine has finished.
CONFIDENTIAL
Exception Handling
Entering an exception the ARM core
saves the address of the next instruction in the appropriate LR
r15 (PC)
PC + 4 or PC + 8
r14_<mode> (LR)
copies the CPSR into the appropriate SPSR

SPSR_<mode>
CPSR
sets appropriate CPSR bits

interrupt disable bits
mode field bits
CPSR:
if running in Thumb state, enter ARM state*
0
mode
Control bits
forces PC to fetch next instruction from relevant exception vector

*: all exceptions are handled in ARM state!
CONFIDENTIAL
Exception Vectors
Vector Table
0x1C
.
.
.
FIQ
0x18
IRQ
0x14
(Reserved)
0x10
Data Abort
0x0C
Prefetch Abort
0x08
Software Interrupt
0x04
Undefined Instruction
0x00
Reset
CONFIDENTIAL
Multiple Exceptions
Exception priorities
When multiple exceptions arise at the same time, a fixed priority
sytem determines the order in which they are handled
1.
Reset
2.
Data Abort (data memory access cannot be completed)
3.
FIQ
4.
IRQ
5.
Prefetch Abort (instruction memory access cannot be completed)
6.
7.
SWI - Software Interrupt
highest priority
(to enter supervisor mode)
lowest priority
CONFIDENTIAL
Leaving Exception
To leave an exception, the exception handler must
copy SPSR back into CPSR
SPSR_<mode>
CPSR
(automatically restoring also I, F and T)

8
CPSR:
0
mode
Control bits
move contents of current LR minus offset* to PC

r14_<mode> (LR)
PC - offset
r15 (PC)
*: varies according to type of exception: 2, 4 or 8

CONFIDENTIAL
1.
ARM - The Company
2.
Architecture
3.
Instruction Set
4.
ARM7TDMI-S
5.
Systems
6.
Other ARM cores
7.
NXP Implementation
8.
Q&A
CONFIDENTIAL
Instruction Set
All instructions are 32-bits long
Many instructions execute in a single cycle
Instructions are conditionally executed
ARM is a load / store architecture
via registers => RISC
Load or store multiple registers in a single instruction

using <register list>
CONFIDENTIAL
Conditional Execution
Mnemonic
Description
EQ
Equal
NE
Not equal
CS / HS
Carry Set / Unsigned higher or same
CC / LO
Carry Clear / Unsigned lower
MI
Negative
PL
Positive or zero
VS
Overflow
VC
No overflow
HI
Unsigned higher
LS
Unsigned lower or same
GE
Signed greater than or equal
LT
Signed less than
GT
Signed greater than
LE
Signed less than or equal
AL
Always (normally omitted)
CONFIDENTIAL
Instruction Examples
Data processing instructions
SUB
r0, r1, #5
r0 := R1 - 5
ADD
r2, r3, r3, LSL #2
r2 := r3 + (r3, LSL #2)
ADDS
r4, r4, #0x20
r4 := r4 + 32 and set flags
ADDEQ r5, r5, r6
r5 := r5 + r6 if equal
Specific memory access instructions

LDR
r0, [r1, #4]
r0 := [r1 +4]
STRNEB r2, [r3, r4]
[r3 + r4] := r2 Byte operation

if Z = 0; ignores r2[31:8]
LDRSH
r5 := [r6 + 2] Halfword sign-ext.

set bit [31:16] to bit 15
then r6 := r6 + 2
r5, [r6, #2]!
CONFIDENTIAL
Thumb Instruction Subset

Subset of most commonly used 32-bit ARM instructions
2 address format: destination register same as one source registers
Compressed into 16-bit wide code

Improved code density
Decompressed on execution to full 32-bit instructions

transparently
in real-time
no performance loss
ARM code can be combined with Thumb code for maximum

flexibility
CONFIDENTIAL
Thumb Instructions
ARM instruction set
31
Thumb instruction set

0
ARM instruction
Recoding
15
Thumb instruction
ARM instruction
Thumb instruction
ARM instruction
Thumb instruction
ARM instruction
Thumb instruction
ARM instruction
Thumb instruction
ARM instruction
Thumb instruction
ARM instruction
Thumb instruction
CONFIDENTIAL
Thumb Instruction Set (1)

Instruction Types
Branch
Unconditional
2KBytes
Conditional
256Bytes
Branch with Link
4MBytes
(2 Instructions!)
Branch and exchange
change to ARM state
if Rm[0] = 0
Branch and exchange with Link
Data Processing
Subset of ARM data processing instructions
Not conditionally executed (but some update flags)
CONFIDENTIAL
Thumb Instruction Set (2)

Instruction Types
Load and Store
Register plus 5-bit (PC,SP plus 8) immediate addressing
Register plus Register addressing
Load and Store Multiple

Load / Store list of registers
Push / Pop
(ARM equivalent: STMDB SP!, <registers>)
Exception Generating Instructions

SWI
(switch to ARM mode and privileged mode)
Breakpoint
(prefetch abort, with debug monitor)
CONFIDENTIAL
Translation of Thumb Instruction

Example: ADD Rd, Rd, # Constant
Thumb code
15
001
Major op-code
10
Minor op-code
denoting format 3
denoting ADD
move/compare/add/sub/
instruction
with immediate value
Rd
8-bit immediate
Destination and
Immediate
source register
value
31
1110
00
Always condition code
0100
0 Rd 0 Rd
0000 8-bit immediate
ARM code
CONFIDENTIAL
ARM and Thumb Interworking

Switch between ARM state and Thumb state using BX instruction
In ARM state:
BX<condition> Rn
In Thumb state:
BX Rn
Rn
31
n: 0-15
BX
Destination
address
31
ARM / Thumb
selection
0:
ARM state
1:
Thumb state
CONFIDENTIAL
1.
ARM - The Company
2.
Architecture
3.
Instruction Set
4.
ARM7TDMI-S
5.
Systems
6.
Other ARM cores
7.
NXP Implementation
8.
Q&A
CONFIDENTIAL
ARM7TDMI-S
The ARM7TDMI-S is based on ARM7 core
3 stage pipeline
Von Neumann architecture
CPI ~1.9
T:
Thumb instruction set
D:
includes debug extensions
M:
enhanced multiplier (32x8) with instructions for 64-bit results
I:
core has EmbeddedICE logic extensions
S:
fully synthesisable (soft IP)
CONFIDENTIAL
ARM7TDMI-S Core
Address Bus
Address Register
Incr.
Instruction
Decode &
General
Control
Registers
Mult.
Shifter
Thumb
Decompression
ALU
Data Out
Data In
Data Bus
CONFIDENTIAL
3-Stage Instruction Pipeline

ARM
Thumb
PC
PC
PC - 4
PC - 8
PC - 2
PC - 4
Fetch
Decode
Execute
Instruction Fetched from Memory
Thumb only: Thumb instruction

decompressed to ARM instruction
Instruction decoded
Registers read from Register Bank,
Shift and ALU operations
performed, Registers written back
to Register Bank
CONFIDENTIAL
1.
ARM - The Company
2.
Architecture
3.
Instruction Set
4.
ARM7TDMI-S
5.
Systems
6.
Other ARM cores
7.
NXP Implementation
8.
Q&A
CONFIDENTIAL
Example ARM based System
RAM
ARM core
16 bit wide
Interrupt
Controller
Peripherals
I/O
ROM
8 bit wide
RAM
32 bit wide
CONFIDENTIAL
AMBA
Advanced Microcontroller Bus Architecture
on-chip interconnect
established, open specification
framework for SoC designs
enabler for IP reuse
digital glue that binds IP cores together
CONFIDENTIAL
Example AMBA System

ARM core
Keypad
UART
Highbandwidth
Memory
Interface
AHB
APB
Bridge
APB
Timer
Display
High-bandwidth
on-chip RAM
DMA
Bus Master
RTC
I/O
CONFIDENTIAL
AHB and APB / VPB

Advanced High-Performance Bus
high-performance
pipelined
fully-synchronous backplane
multiple bus masters
Advanced Peripheral Bus
VLSI Peripheral Bus
low-power
non-pipelined
simple interface
wait support
(VPB)
CONFIDENTIAL
1.
ARM - The Company
2.
Architecture
3.
Instruction Set
4.
ARM7TDMI-S
5.
Systems
6.
Other ARM cores
7.
NXP Implementation
8.
Q&A
CONFIDENTIAL
Pipeline-Changes for ARM9TDMI

ARM7TDMI
Fetch
Decode
ThumbARM
decompress
Instruction Fetch
ARM decode
Reg. select
Execute
Reg.
read
Shift
ALU
Reg.
write
CPI:
1.9
ARM9TDMI
Fetch
Instruction
Fetch
Decode
ARM or Thumb
instruction decode
Reg.
decode
Reg.
read
Execute
Memory
Shift + ALU
Memory
access
Writeback
Reg.
write
CPI:
1.5
CONFIDENTIAL
Development of the ARM Architecture

Halfword and
signed
halfword /
byte support
System
mode
Thumb
instruction set
3
Early ARM
architectures
T: Thumb
4
SA-110
SA-1110
4T
Improved
ARM/Thumb
Interworking
Jazelle
5T
CLZ
Instruction
Saturated maths
DSP multiplyaccumulate
instructions
Java
bytecode
execution
5TE
ARM9EJ-S
ARM7EJ-S
ARM7TDMI
ARM9TDMI
ARM1020E
ARM9E-S
ARM720T
ARM940T
X-Scale
ARM966ES
E: DSP-extensions
:ISA (Instruction Set Architecture)
5TEJ
S: synthesizable
ARM926EJ
-S
J: Java
: Core Architecture
CONFIDENTIAL
ARM Technology Roadmap

0.12
Performance MIPS (Dhry 2.1)
0.15
0.18
400
0.35
4.8mm2
0.35
2.1mm2
0.6
4.8mm2
0.18mm
ARM 9E
ARM 9...
100
0.18
< 0.5mm2
0.25
1.0mm2
ARM 11
(ARM 10)
0.25
0.25
2.4mm2
0.15
70-150 DSP MIPS

Harvard
5 Stage Pipeline
Von Neumann
3 Stage Pipeline
ARM 7 Thumb Family

1996
1997
1998
1999
2000
2001
2002
CONFIDENTIAL
1.
ARM - The Company
2.
Architecture
3.
Instruction Set
4.
ARM7TDMI-S
5.
Systems
6.
Other ARM cores
7.
NXP Implementation
CONFIDENTIAL
LPC2xxx minimum peripherals set

Some common features
ARM7TDMI-S core with E-ICE RTM / ETM
Operation up to 60MHz
32-bit timers
2
(4 capture and 4 compare channels each)
PWM
(6 outputs)
RTC
Watchdog
2 UARTs (16C550)
IC (400kb/s)
CONFIDENTIAL
NXP Implementation
1.
Memory Addressing
2.
System Control Block
3.
Memory Accelerator Module (MAM)
4.
General Purpose I/O / Pin Connect Block
5.
Vectored Interrupt Controller
6.
Integrated Peripherals
Timer 0 / Timer 1, UART 0 / UART 1, IC, SPI, PWM, RTC,
Watchdog, ADC, USB, CAN, Ethernet, SD, IIS, GPDMA
CONFIDENTIAL
LPC2000 Memory Map

4.0 GB
3.75 GB
3.5 GB
AHB Peripherals
VPB Peripherals
0xFFFF FFFF
0xF000 0000
0xEFFF FFFF
0xE000 0000
Memory blocks not
drawn to scale!
Reserved for External Memory
3.0 GB
2.0 GB
0x8000 0000
Boot Block (re-mapped from On-Chip Flash)
0x7FFF E000
8 KB On-Chip Static RAM, USB
0x7FE0 0000
16 KB On-Chip Static RAM, ETHERNET
0x7FD0 0000
RAM on AHB
Reserved for On-Chip Memory
16 / 32 / 64 KB On-Chip Static RAM
1.0 GB
0x4000 nnnn*
0x4000 0000
0x3FFF FFFF
RAM on local bus

-> fast access !
0.0 GB
8KM ... 1MB On-Chip Non-Volatile Memory
0x000m FFFF
0x0000 0000
CONFIDENTIAL
Flash Memory Organization

The boot block always
resides in the top of Flash
and contains the boot loader
512k
LPC2100, 128k
8K Boot Block
0x01 FFFF
Sector 14 8K
Sector 9 64K
Sector 13 8K
Sector 8 64K
Sector 12 8K
Sector 2 8k
Sector 7 8K
Sector 2 8k
Sector 1 8K
Sector 1 8K
Sector 0 8K
0x0
Sector 0 8K
12K Boot Block
Sector 26
Sector 22
Active Exception Vectors

Active interrupt vectors could
0x3F
be from Flash, SRAM or boot
0x00
block. On reset the boot block
vectors are always mapped to
0x0
LPC2100, 256k
8K Boot Block
Sector 16 8K
Sector 10 8k
LPC213X
4K
0x07 CFFF
4k
Sector 21 32K
Sector 15 32k
256k
0x03 FFFF
128k
64k
32k
0x0
0x07 FFFF
Sector 14 32K
Sector 11 32k
Sector 10 32K
0x03 FFFF
0x01 FFFF
Sector 9 32K
Sector 8 32K
Sector 7 4K
...
Sector 1 4K
Sector 0 4K
0x00 FFFF
0x00 7FFF
0x0
CONFIDENTIAL
SRAM: 8, 16, 32 or 64 KB
0x4000FFFF
64KB SRAM
0x40007FFF
32KB SRAM
0x40003FFF
16KB SRAM
RAM Int Vect
RAM Int Vect
RAM Int Vect
8KB SRAM
RAM Int Vect
0x40001FFF
0x4000003F
0x40000000
CONFIDENTIAL
1.
Memory Addressing
2.
3.
4.
5.
6.
Watchdog, Ethernet, SD, IIS, GPDMA
CONFIDENTIAL
System Control
Includes a number of important system features
Power Control
Memory mapping configuration
Oscillator
PLL
VPB (VLSI Pheriperal Bus) divider
Reset (active low)
Wakeup Timer
External Interrupts
CONFIDENTIAL
Power Control 1
Power Control Register
[PCON 0xE01FC0C0]
R/W
PCON[0]
IDL
Idle mode - processor clock

stopped, on-chip peripherals remain
active, interrupts cause wakeup
PCON[1]
PD
Power Down mode - oscillator and

on-chip clocks stopped, wakeup by
external interrupt
20 uA at room
temperature,
50 uA with single
voltage supply
For example 5 mA with most

peripherals powered down
Biggest factors:
temperature, clock rates
Peripheral Clock Divider: 20%
CONFIDENTIAL
Power Control 2
When disabled, peripherals are switched off to conserve power
Power Control for
Peripherals Register
[PCONP 0xE01FC0C4]
PCONP 1
PCTIM0
Enable Timer0
PCONP 2
PCTIM1
Enable Timer1
PCONP 3
PCURT0
Enable UART0
PCONP 4
PCURT1
Enable UART1
PCONP 5
PCPWM0 Enable PWM0
PCONP 7
PCI2C
Enable I2C
PCONP 8
PCSPI
Enable SPI
PCONP 9
PCRTC
Enable RTC
R/W
Each peripheral
typically below 1mA
......
CONFIDENTIAL
Power Control (3)
Power Control for Peripherals Register cont'd

...
PCONP 8
PCSP0
Enable SPI0
PCONP 9
PCRTC
Enable RTC
PCONP 10
PCSPI1
Enable SPI1
PCONP 11
PCEMC
Enable External Memory Controller
PCONP 12
PCAD
Enable A/D-Converter
PCONP 13
PCCAN1
Enable CAN Controller 1
PCONP 14
PCCAN2
PCONP 15
PCCAN3
PCONP 16
PCCAN4
Acceptance Filter
enabled with any
CAN Controller
CAN peripheral
typically below 2mA
CONFIDENTIAL
Boot Block
The uppermost Flash sector contains the Boot Loader
controls physical interface for programming and erasing the Flash
supports ISP (In System Programming) mode for initial
programming of customer code
supports In-Application Programming in a running system under
the control of customer software
buffers an entire Flash line (512 bytes) at once to keep
programming time to a minimum
The Boot Loader is automatically run following reset

checks for a Valid User Program key to prevent running code on
incorrectly programmed devices
CONFIDENTIAL
Flash Memory IAP Programming

IAP: In Application Programming
Bootloader contains flash programming routines
Erase Sectors
Write blocks (of 512 bytes)
Re-write to blocks possible, if bits are cleared in 32 byte groups
(see hands-on example)
Common entry point for IAP calls: 0x7ffffff1
During calls, all interrupts must be disabled

Note: hands-on example only disabled IRQ, not FIQ
CONFIDENTIAL
BOOT PROCESS FLOWCHART

LPC23/24 only
CONFIDENTIAL
Exception Vectors
Vector Table
0x1C
.
.
.
FIQ
0x18
IRQ
0x14
(Reserved)
0x10
Data Abort
0x0C
Prefetch Abort
0x08
Software Interrupt
0x04
0x00
Reset
Valid user program key:

Must contain a value that
ensures that the checksum
of all vectors is zero
CONFIDENTIAL
Memory Mapping Control 1

Re-mapping of Exception Vectors
always appear to begin at 0x0000 0000
but can be mapped from different sources:
User Flash
Exception Vectors are not re-mapped and reside in Flash
On-chip Flash Memory
0x0000 003F
0x0000 0000
CONFIDENTIAL
Memory Mapping Control (2)

Boot Loader
Always executed after reset. Exception Vectors re-mapped from Boot Block
User RAM
Exception Vectors are re-mapped from RAM
Off-chip Memory
0x8000 0000
On-chip User RAM

0x4000 0000
Boot Loader
On-chip User Flash Memory
0x0000 003F
0x0000 0000
CONFIDENTIAL
Memory Mapping Control (3)

Re-mapping of Boot Block
mapped from top of Flash to top of on-chip memory space
2.0 GB
On-chip User RAM
Boot Loader
On-chip User Flash Memory
0x0000 003F
0x0000 0000
CONFIDENTIAL
Memory Mapping Overview

AHB Peripherals
0xFFFF FFFF
4.0 GB
VPB Peripherals
Reserved for External Memory
Exception Vector
re-mapping
Boot Block (re-mapped from On-Chip Flash)
0x7FFF FFFF
2.0 GB
Boot Block
re-mapping
16/32/64 KB On-Chip Static RAM
8KB Boot Block

0x3F
128 KB On-Chip Non-Volatile Memory
0x0000 0000
0x00
CONFIDENTIAL
Memory Mapping Control Register

Memory Mapping Control [MEMMAP 0xE01FC040]
MEMMAP 1:0
MAP 1:0
R/W
00: Boot Loader Mode

01: User Flash Mode (no re-mapping)
10: User RAM Mode
11: External Memory
Selects the memory being mapped to address zero
CONFIDENTIAL
Phase Locked Loop (1)

10 to 25 MHz input clock frequency
Output frequency from 10 MHz up to the max. CPU rate
(LPC2xxx: 60MHz)
Programmable frequency multiplication

PLL bypassed on reset
PLL lock indicator can be used as an interrupt to connect the
PLL once it is locked
PLL programming requires a special feed sequence (like the
watchdog) for safety
CONFIDENTIAL
Phase Locked Loop (for old families LPC21xx and LPC22xx)
156 to 320 MHz

Fosc * 2 * M * P
FOSC
XTAL1
Oscillator
Phase
Detector
Current
Controlled
Oscillator
10 to 60 MHz
Fosc * M
FCCO
cclk
2P
Divider
Value
10 to 25 MHz
1 to 30 MHz
without PLL
P:=1..8
Multiplier Value
Default: 4
VPB pclk
Divider
1/2/4
M:=1..32
CONFIDENTIAL
Phase Locked Loop (3)

cclk:
processor clock frequency
Fosc:
crystal oscillator or input frequency
Fcco:
PLL CCO-frequency
10 ... 60-70
MHz
10 ... 25
MHz
156 ... 320
MHz
Fcco
2P
cclk = M FOSC
cclk =
FCCO = cclk 2 P
Fcco= Fosc M 2 P
Example: FOSC = 10 MHz (crystal controlled)

M =
cclk
Fosc
Select suitable value for P:
60 MHz
10 MHz
Target: cclk = 60 MHz

= 6
FCCO = 60 MHz 2 P = 240 MHz
(P = 2)
CONFIDENTIAL
PLL Registers (1)

PLL Control Register
[PLLCON 0xE01FC080]
PLLCON0
PLLE
PLL Enable
PLLCON1
PLLC
PLL Connect
PLL Configuration Register [PLLCFG 0xE01FC084]

PLLCFG 4:0
MSEL 4:0
PLL Multiplier value "M" (M-1)
PLLCFG 6:5
PSEL 1:0
PLL Divider value "P"
R/W
R/W
00: 1
01: 2
10: 4
11: 8
CONFIDENTIAL
PLL Registers (2)

PLL Feed Register
PLLFEED 7:0
PLLFEED
PLL Status Register
[PLLFEED 0xE01FC08C]
WO
Consecutive writes 0xAA then 0x55
[PLLSTAT 0xE01FC088]
PLLSTAT 4:0
MSEL 4:0
Readback for Multplier value "M" (M-1)
PLLSTAT 1:0
PSEL 1:0
Readback for Divider value "P" (1,2,4,8)
PLLSTAT 8
PLLE
Readback for PLL Enable bit
PLLSTAT 9
PLLC
Readback for PLL Connect bit *
PLLSTAT10
PLOCK
Reflects PLL Lock status
RO
* Cleared when Power Down mode activated
CONFIDENTIAL
VPB Divider Register

VPB Divider Register
VPBDIV 1:0
VPBDIV
[VPBDIV 0xE01FC100]
cclk / pclk ratio
R/W
00: 4
01: 1
10: 2
CONFIDENTIAL
1.
Memory Addressing
2.
3.
4.

Pin Connect Block / External Memory Controller
5.
6.
Watchdog, ADC, CAN
CONFIDENTIAL
On-chip Memory with 0-wait States

ARM7TDMI-S is a 1-clock core
CPI of ~1.9, but many instructions execute in 1 cycle
CPU requires one instruction per clock cycle
For highest performance
32 bits needed with every clock

Memory access time < 17ns @ 60MHz
CONFIDENTIAL
Memory Accelerator Module

CPU performance limited by Flash access time (<50 ns)
ARM needs 32 bits every clock for 1 clock instructions
Without MAM operation possible up to 20MHz
Flash Architecture
Flash is split into two blocks of 128 bits each
128 bits are accessed at once
Separate Branch Trail Buffer holds 128 bits of history of each block
=> 4-times speed improvement for linear code; branches will cause a
variable delay, depending on target address
Additional Data Buffer for data accesses to Flash
CONFIDENTIAL
Memory Accelerator Module

Address Bus
Core
Bus Interface
ARM7
Flash Memory
Bank 1
Flash Memory
Bank 2
128 bit
128 bit
Prefetch Buffer 1
Local Bus
Prefetch Buffer 2
Branch Trail Buffer 1
Branch Trail Buffer 2
128 bit (2x)
128 bit (2x)

Data Buffer
Selection
Data Bus (32 / 16 bit)
CONFIDENTIAL
MAM Registers
MAM Control Register
MAMCR 1:0
MAM mode
control
[MAMCR 0xE01FC000]
R/W
00: MAM functions disabled

01: MAM functions partially enabled *
10: MAM functions fully enabled
11: reserved
MAM Timing Register

MAMTIM 2:0
MAM Fetch
Cycle timing
* Only sequencial code via MAM
[MAMTIM 0xE01FC004]
R/W
000: reserved
001: MAM fetch is 1 clock cycle
...
111: MAM fetch is 7 clock cycles
CONFIDENTIAL
Hands-On Index
1.
Tools Setup
2.
PLL / MAM / GP I/O / Flash
3.
ADC
4.
Interrupts / Timer
5.
UART / CAN
Hands-On
CONFIDENTIAL
PLL and MAM Setup with

Keil uVision, Project Blinky1
Hands-On
The PLL and MAM settings are part of the

startup code
Settings can be
made using a
convenient
input mask
Exercise:
Setup the PLL
to 60Mhz
CONFIDENTIAL
MAM Setup
Enabling the MAM for
60Mhz clock and 50ns
Flash
Setup MAM
Fully Enable
MAM Timing 3
3 * 17ns = 51ns
Hands-On
Explanation of MAM
Register values
Partially Enable:
Code fetches only
Fully enable:
Code and data fetches
MAM Timing
Number of clock cycles
used for one flash
memory access
CONFIDENTIAL
Verify
PLL and MAM Settings
Hands-On
Open disassembly window and single

step through while loop in function wait
Every loop needs 6 cycles:
3 instructions at 1 CPI
1 instruction (branch) at 3 CPI
In Simulation == In Hardware if MAM is full enabled

If the define LOOP_DELAY is 1.000.000
6.000.000 cycles are realized in the delay()
action incremented every 100ms at 60Mhz
CONFIDENTIAL
Flash IAP
Hands-On
Project FlashSWInt
Load and single step
Watch memory at 0x8000, ASCII mode
Exercise:
Change program to use address 0x10200
for storing the string
CONFIDENTIAL
1.
Memory Addressing
2.
3.
4.
5.
6.
Watchdog, ADC, CAN
CONFIDENTIAL
General Purpose I/O (1)

Pins available for GPIO:
LPC21/22
48-pin devices:
32
64-pin devices:
46
144 pin devices:
76 (max.)
112
(with external memory)

(w/o external memory)
LPC23/24
Up to 160 GPIO pins, all implemented as fast GPIOs, with 64 GPIO interrupts
(plus 4 other external interrupts).
Shared with
Alternate functions of all peripherals
Data/address bus and strobe signals for external memories
CONFIDENTIAL
General Purpose I/O (2)

Direction control of individual bits
Separate set and clear registers
Pin value and output register can be read separately
Slew rate controlled outputs (10 ns)
5 registers used to control I/Os
CONFIDENTIAL
General Purpose I/O 2

Register
IOPIN
The current state of the port pins is read from this register
IOSET
Writing "1" sets pins high, writing "0" has no effect
IOCLR
Writing "1" sets pins low and clears corresponding bits in IOSET
IODIR
Port pin direction: 0 = INPUT
PINSEL0/1
1 = OUTPUT
Selects function of pins (Pin Connect Block)
CONFIDENTIAL
Conventional GPIO Implementation Drawbacks
Conventional ARM GPIO is implemented on the APB

peripheral bus
Toggling speed of the GPIO is limited due to the 3-stage
pipeline, AHB bridge and the APB bus
CONFIDENTIAL
Understanding the slow port behavior

It takes 5 clocks to execute a port write
Total time from instruction fetch to port change is 7 clocks
Maximum achievable period is 14 clocks (cclk/14) = (60/14) = 4.28MHz
When cpu_clken_I is low indicates core is stalled
CONFIDENTIAL
Block diagram of new port configuration
CONFIDENTIAL
10
Improving Speed
GPIO registers are now interfaced directly to the
ARM7 Local bus
Ports can now toggle every 2 clocks giving a clock
period of cclk/4= 15Mhz
This is a 3.5x speed increase
Enables faster soft peripherals
CONFIDENTIAL
Results of change (speed of writes)

Port output
Fetching
Writing
Decoding
E5803000
Executing
E5802000
Fetching
E580500
Decoding
Nothing
Fetching
Writing
Decoding
E5804000
Executing
E5803000
Executing
E5803000
Fetching
E580500
Fetching
E580500
Decoding
Nothing
Fetching
Writing
Decoding
E5805000
Decoding
Nothing
Executing
E5804000
Executing
E5804000
Executing
E5805000
CONFIDENTIAL
Fast GPIO
Special features
GPIO registers accessed via ARM local bus in addition
to conventional peripheral bus access
Mask registers allow treating sets of port pins as a
group, leaving other bits unchanged
Local bus GPIO registers are now byte addressable
Entire port value can be written in one instruction using
the IOPIN register
CONFIDENTIAL
Mask Register- Advantages

Provides the capability to the user to separate the GPIO pins into
groups
Any modifications to the FIOSET,FIOCLR and FIOPIN is only effected if
the corresponding bits in the FIOMASK are set
Using Mask registers
Individual I/O pins can be addressed separately
CONFIDENTIAL
Pin Connect Block (1)

Many on-chip functions can use I/O pins
Number of I/O-pins is limited
I/Os can be configured to adapt various functions

Configuration done by Pin Connect Block
PINSEL0/1/2
PIN
GPIO
UART
Timer/Counter
reserved
CONFIDENTIAL

Pin Function Select Registers
PINSEL0 and PINSEL1
Configuration of P0
Assign P0.0 ... P0.31 to GPIO or an alternate function (1 of max.
3)
PINSEL2
(not available in 48-pin devices)
Configuration of P1 (64/144-pin devices) and P2, P3 (144-pin devices)

Select availability of debug and trace ports on Port1 pins
Controls use of address/data bus and strobe pins
(144-pin
devices)
Selection of additional ADC-inputs
(144-pin devices)
CONFIDENTIAL

Example:
...
Pin Function Select Register 0 [PINSEL0 - 0xE002C000)] R/W

...
PINSEL0 21:20
...
P0.10
...
00: GPIO Port 0.10

01: RTS (UART1)
10: Capture 1.0 (Timer 1)
11: reserved
...
...
...
CONFIDENTIAL
External Memory Controller* (1)

Supports static memory devices (RAM, ROM, external I/O)
Up to 4 independent banks, each up to 16M Bytes
Programmable
Bus turnaround (idle) cycles (1 to 16)
Read and write WAIT states (up to 32)
Write protection
Burst mode operation
External data width: 8, 16, or 32 bits
*: LPC2000 144-pin devices only, LPC2378, LPC24xx
CONFIDENTIAL

Available signals
Pin name
Type
Description
D [31:0]
Input / Output
External memory data lines
A [23:0]
Output
External memory address lines
OE
Output
Output Enable (active low)
BLS [3:0]
Output
Byte Lane Select (active low)
WE
Output
Write Enable (active low)
CS [3:0]
Output
Chip Select (active low)
*: 144-pin devices only

CONFIDENTIAL

Selection of external data bus width
(144-pin devices only)
Determined by state of pins Boot0 and Boot1 during Reset
P2.27 / D27 / Boot1 P2.26 / D26 / Boot0
Boot from
8-bit memory on CS0
16-bit memory on CS0
32-bit memory on CS0
Internal Flash memory

CONFIDENTIAL

Size of external memory
Number of external address lines defined by
PINSEL2 27:25
Remaining port pins available as GPIO

111
110
101
100
011
010
001
000
decoded to CS0 ... CS3

31 30 29 28 27 26 25
24 23
20 19
16 15
12 11
CONFIDENTIAL
GPIO Exercise
Hands-On
Exercise:
Modify the example
to use a macro or function
for LEDs
Optional Exercise:
Invent a display pattern
indicating seconds and
125ms
Hint:
Examples:
SET_LEDS(byte)
LEDs are on
Port 1, bits 16-23
Walking LED, or
Bar indicator
CONFIDENTIAL
1.
Memory Addressing
2.
3.
4.
General Purpose I/O / Pin Connect Block / Memory

Controller
5.
6.
Watchdog
CONFIDENTIAL

ARM PrimeCell
32 interrupt request inputs
16/32 IRQ interrupts can be auto-vectored (in the LPC23/24)
single instruction vectoring to ISR
dynamic software priority assignment
32 FIQ non-vectored interrupts

32 Software interrupts
CONFIDENTIAL
FIQ
IntEnable
O
R
0:4
En Channel
5
FIQ
High Prio
...
32
FIQ
FIQ
En Channel
IRQ
IntSelect
32
VectorCntl
IRQStatus
O
R
IntEnableClear
SoftIntClear
SoftInt
32
interrupt
RawInterrupt
Timer
Interrupt
Source
FIQStatus
VICVectorAddr 0
C
P
U
16/32 (LPC23/24)
VICVectorAddr 15/31
0:4
VICDefVectAddr
Low Prio
Known FIXED ADDRESS

VICVectAdd
VICVectorAddr
VICVectorAdd 0
D[0..31]
IRQ
D[ ]
CONFIDENTIAL
IRQ Interrupts
Vectored
Vectored
Interrupt
Interrupt
Controller
Controller
Timer
Timer
(Overflow)
(Overflow)
Interrupt
FIQ
ARM-Core
IRQ
Channel
Channel#4
#4
VIC
Vector
Address
Channel
Channel#16
#16
Exception
Vector
Table
Main
0x1C
0x18
0x14
...
LDR PC, [PC,#-0FF0] (VICVectADDR): address of

service routine
Timer
-ISR
CONFIDENTIAL
VIC - Vectored Interrupts

Interrupt 4
VICVectAddr4
Load PC with Vector Address
VICVectAddr
ISR
CONFIDENTIAL
VIC - Non-Vectored Interrupts

Interrupt
ISR
VICDefVectAddr
ISR
CODE
VICVectAddr
ISR
ISR
ISR
ISR
Load PC with Common

Vector Address
CONFIDENTIAL
VIC - FIQ Interrupt

FIQs have higher priority than IRQs
Serviced first
FIQs disable IRQs
FIQ Vector is last in vector table (allows handler to be run
sequentially from that address)
FIQ mode has 5 extra banked registers, r8-12 (interrupt
handlers must always preserve non-banked registers)
CONFIDENTIAL
VIC FIQ (Fast Interrupt)
Interrupt
FIQ ISR
in Flash
Load PC with Vector

Address
FIQ ISR
in RAM
VectorAddress = 0x1C
ISR
CONFIDENTIAL
Interrupt Prioritizing with Nesting

IRQ Service Routine of lower priority:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Push SPSR to LR and on stack

Switch to System Mode (write CPSR, enable IRQ)
Push system mode link register on stack
Execute real service routine
Pop system mode link register from stack
Switch back to IRQ mode
Pop SPSR to LR and restore SPSR
Clear IRQ source
Reset VIC
For Keil compiler, see knowledgebase at www.keil.com
CONFIDENTIAL
Hands-On Index
1.
Tools Setup
2.
Oscillator / PLL / MAM / GP I/O
3.
ADC
4.
Interrupts / Timer
5.
UART / CAN
Hands-On
CONFIDENTIAL
Project: BlinkyIRQ
Hands-On
Load Project
BlinkyIRQ
Build and Debug
Simulation
Use Logic Analyzer
gTimCnt
loop
Peripheral window
Vectored Int. Contr.
CONFIDENTIAL
Hands-On
Exercise:
Timer & Interrupt
Add timer 1 interrupt to
BlinkyIRQ
Interrupt all 333us
Use Vector 1
In ISR, display some LED
pattern on port 1.20 to 1.23
every 333ms
Test and debug in simulator

using:
Performance Analyzer
Signal Analyzer
Peripheral GPIO window
Peripheral Timer window
Peripheral VIC window
Test program on hardware
CONFIDENTIAL
Interrupts
1.
Hands-On
Tools Installation
Emulator/Debugger:
Compiler:
Flash Tool:
Hardware:
Emul-ARM Evaluation System

Embedded Workbench
Flash ISP Utility
LPC2106 Target Board
(Nohau)
(IAR)
(NXP)
(Nohau)
2.
Oscillator / PLL
3.
Memory Acellerator Module / General Purpose I/O
4.
Interrupts
a. Single Interrupt
b. Nested Interrupts
5.
6.
UART
RTC
CONFIDENTIAL
Single Interrupts (1)
Hands-On
IAR Embedded Workbench

Load workspace Chapter 4a
File -> Open Workspace -> Chapter 4a_single_Interrupt ->
Chapter_4a.eww
Select project Training

Target
Debug
Make
OK?
Correct error in Timer.c
(= run from RAM!)
(User Manual !)
Try again
CONFIDENTIAL
Hands-On
Start Seehau
Run project
(Tools -> Seehau)

(RUN -> Go or Button)
What does Blinkie do in this case?

Browse through source codes
Blinkie_Main.c
Timer.c
CONFIDENTIAL
Hands-On

VectorTabDebug.s
(Assembler!)
Exception Program Vector Table

Reset
ldr
pc,=?cstartup
SUPERVISOR mode
Undefined ldr
pc,=0x0000024 UNDEFINED mode
SWI
ldr
pc,=0x0000028 SUPERVISOR mode
Prefetch
ldr
pc,=0x000002c ABORT mode
Data
ldr
pc,=0x0000030 ABORT mode
nop
reserved
IRQ
ldr
pc,[pc,#-0xff0]
IRQ mode
Load contents of the ...
FIQ
ldr
pc,=0x1C
IRQ mode
... VICVectAddr. register into PC
CONFIDENTIAL
Single Interrupts Solution
Hands-On
Timer.c
T0_MCR= 0x03;
//Interrupt on Match0, reset timer on match
Function
LEDs are changed whenever variable TimerIsUp=1
This variable is
set by Timer 0 interrupt routine after Timer 0 match
cleared by main routine before LEDs are changed
CONFIDENTIAL
Hands-On
Nested Interrupts (1)
IAR Embedded Workbench

Load workspace Chapter 4b
File -> Open Workspace -> Chapter 4b_single_Interrupt ->
Chapter_4b.eww
Select project Training

Target Debug
Make
OK?
(= run from RAM!)
CONFIDENTIAL
Start Seehau
Run project
Press SW4
Release SW4
Hands-On
(Tools -> Seehau)
What does Blinkie do in this case?
CONFIDENTIAL
Nested Interrupts
Solution 1
Hands-On
Two interrupt sources

Timer 0 IR:
blinks LEDs
External IR 2 (SW4): stay in ISR until SW4 released

Priorities
External Interrupt > Timer
SW4 blocks Timer 0
(LEDs control)
Timer0_ISR()
Main()
VICVectAddr1
ExtInt_ISR()
VICVectAddr0
SW2, SW3 change direction (polled in main program)

CONFIDENTIAL
Hands-On

Blinkie_main.c
ExtInt.c
InitExtInt2()
Timer.c
InitTimer0()
VectorTabDebug now initializes SP for different

modes
CONFIDENTIAL
Hands-On
!
Nested IR-Handler now save status and reenable further interrupts before entering ISR
nested interrupts possible!
Main()
Nested IR handler
Timer IRS routine
VICVectAddr0
Nested IR handler
Ext. Int. ISR
VICVectAddr1
CONFIDENTIAL
Hands-On
Browse through source codes (cont'd)

NestedIrqHandler.s
Timer 0 nested
save work registers
External Interrupt 2 nested

save work registers
ExtInt2-pin to GPIO
reset IRQ source
reset IRQ-source
switch to System mode, interrupts enabled switch to System mode, interrupts enabled
branch to distinct ISR
branch to distinct ISR
switch to IRQ mode, IRQ disabled
switch to IRQ mode, IRQ disabled

re-enable ExtInt2
reset VIC
reset VIC
restore work registers
restore work registers
CONFIDENTIAL
Hands-On

Change priorities:
External Interrupt < Timer
Edit Timer.c and ExtInt.c:

VICVectAddrn VICVectCntlm
InitTimer0()
is
InitExtInt2()
is
InitTimer0()
new
InitExtInt2()
new
Note: lower value (n, m) is higher priority!
CONFIDENTIAL
Hands-On
Make
OK?
Start Seehau
Run project
(Tools -> Seehau)

What does Blinkie do now?
CONFIDENTIAL
Nested Interrupts
Solution 2
Priorities
Hands-On
External Interrupt < Timer

Blinkie continues, even while SW4 is pressed!
LED5 toggles to indicate recognition of External Interrupt
Two interrupt sources

Timer 0 IR:
blinks LEDs
External IR 2 (SW4): stay in ISR until SW4 released

(but can be interrupted!)
SW2, SW3 change direction (polled in main program)
CONFIDENTIAL
Nested Interrupts
Solution 2
Hands-On
Timer0_ISR()
VICVectAddr0
Main()
ExtInt_ISR()
VICVectAddr1
CONFIDENTIAL
Flag(s)
Block
Watchdog Interrupt (WDINT)
Reserved for software interrupts only
ARM Core
Embedded ICE, DbgCommRx
ARM Core
Embedded ICE, DbgCommTx
Timer 0
Match 0 -2 (MR0, MR1, MR2, MR3)

Capture 0 - 2 (CR0, CR1, CR2)
Timer 1
Match 0 -3 (MR0, MR1, MR2, MR3)

Capture 0 - 3 (CR0, CR1, CR2, CR3)
UART 0
Rx Line Status (RLS)
WDT
-
VIC
IR Sources
LPC2104
LPC2105
LPC2106
VIC IR Source #
Transmit Holding Register empty (THRE)

Rx Data Available (RDA)
Character Time-out Indicator (CTI)
UART 1
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)

Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
PWM 0
Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
I2C
SI (state change)
SPI
SPIF, MODF
10
reserved
11
PLL
PLL Lock (PLOCK)
12
RTC
RTCCIF (Counter Increment), RTCALF (Alarm)
13
System Control
External Interrupt 0 (EINT0)
14
System Control
15
System Control
16
CONFIDENTIAL
Flag(s)
Block
add'l
VIC
IR Sources
LPC2114/24
LPC2119*/29*
LPC2194**
LPC2210/12/14LPC2
290**/92**
LPC2294***
VIC IR
Source #
...
...
17
A/D Converter
18
* CAN
ORed CAN Acceptance Filters
19
* CAN
CAN 1 Transmitter
20
* CAN
CAN 1 Receiver
21
** CAN
CAN 2 Transmitter
22
** CAN
CAN 2 Receiver
23
*** CAN
CAN 3 Transmitter
24
*** CAN
CAN 3 Receiver
25
*** CAN
CAN 4 Transmitter
26
*** CAN
CAN 4 Receiver
27
...
System
Control
A/D
plus more flags for UART0, Timer1,

Capture 0 - 3 (CR0, CR1, CR2, CR3)
CONFIDENTIAL
VIC Interrupt Latency

Some instructions take multiple cycles to execute and
cannot be interrupted
The longest STM and LDM instructions take 20 cycles
Subsets can be reduced to 7 cycles
FIQ: 12 (25) cycles, 200ns (416ns) @ 60MHz

First Vectored IRQ (assuming no FIQ pending):
26 (39) cycles, 433ns (650ns) @ 60MHz
Default IRQ Vector (assuming no other IRQ pending):
42 (55) cycles, 700ns (916ns) @ 60MHz
CONFIDENTIAL
1.
Memory Addressing
2.
3.
4.
5.
6.
Watchdog
CONFIDENTIAL
RTC
CONFIDENTIAL
Real Time Clock
Only for
LPC213x,4x
LPC23,LPC24
PCLK
RTC
oscillator
Clock Divider
(prescaler)
MUX
Clock
generator
The Counter
Increment can
cause an
interrupt
Time
Counters
Alarm
Registers
Comparators
Interrupt Generator
CONFIDENTIAL
Real Time Clock

Full Clock/Calendar function with alarms
generates its own 32.768 kHz reference clock from any crystal
frequency
counts seconds, minutes, hours, day of month, month, year, day of
week and day of year
can generate an interrupt or set an alarm flag for any combination
of the counters
CONFIDENTIAL
Power consumption of RTC (LPC213x)

Core
RTC
Current
consumption from
Vbat
Power down
Power down
20-30A
Power down
Running from
Vbat
20-30 A
Active
(pclk=15MHz)
Running
around 80 A
CONFIDENTIAL
IAP programming
CONFIDENTIAL
4 ways of programming the LPC2000 Flash
In-Application Programming (IAP)

In-System Programming
(ISP via NXP Boot Loader, UART0)
In-System Programming
(through LPC HW macro cells/
and custom software protocol)
Parallel programmer
CONFIDENTIAL

FLASH MEMORY
ISP: In-System programming is programming or reprogramming the on-chip flash
memory, using the boot loader software and a serial port. This can be done when
the part resides in the end-user board.
IAP: In-Application programming is performing erase and write operation on the
on-chip flash memory, as directed by the end-user application code.
User-code security : Code read protection is enabled by programming the flash address
location 0x1FC (User flash sector 0) with value 0x87654321 (2271560481 Decimal).
Disabled:
JTAG debug port
External memory boot
Following ISP commands:

Read Memory
Write to RAM
Go
Copy RAM to Flash
CONFIDENTIAL
ADC
CONFIDENTIAL
A/D Converter
Features
10 bit successive approximation analog to digital converter
Multiplexed inputs
4 pins
(64-pin devices)
8 pins
(144-pin devices)
Power down mode

Measurement range 0V ... 3V
Minimum 10 bit conversion time: 2.44 S
Burst conversion mode for single or multiple inputs
Optional conversion on transition on input pin or Timer Match signal
Programmable divider to generate required 4.5MHz from VPB clock
CONFIDENTIAL
A/D Converter Burst mode

CLKS: bit 17, 18, 19 of ADCR select the number of
clocks used per conversion and the accuracy
000b: 11 clocks, 10 bits

CONFIDENTIAL
ADC LPC213X, LPC214X
Separate result register for each channel

Reduces the interrupt overhead by a factor of 8
Measurement range of 0 V to 3 V
Separate voltage pins for analogue 3V supply (V3A) and

analogue ground (VSSA)
CONFIDENTIAL
ADC Software Controlled Mode

All conversions are 10-bit and take 11 clocks
4.5Mhz Maximum Clock
Allows conversion to start on an external edge
ADC Inputs
7 6 5 4 3 2 1 0
ADDR0
ADDR1
Select Single Channel
ADCR (7:0)
10-bit ADC
(11 Clocks/Conv)
ADDR7
V3A
VSSA
CONFIDENTIAL
ADC Burst Mode

Result accuracy and speed are programmable
Input selected by the SEL bits are scanned
ADC Inputs
ADC Clock
(CLKS Bits)
Select Multiple Channels

ADCR (7:0)
1-8
Input Scan
(SEL Bits)
ADDR0
n-bit ADC
(n Clocks/Conv)
ADDR1
ADDR7
CONFIDENTIAL
DAC
CONFIDENTIAL

DAC (10-bit)
This peripheral is available in the LPC2138 only. The D/A converter enables
the LPC2138 to generate variable analog output.
10 bit digital to analog converter
Resistor string architecture
Buffered output
Power down mode
Selectable speed vs. power
CONFIDENTIAL
LPC213x DAC
Digital-to-Analog Converter (DAC)
10-bit resolution DAC with a buffered output

Last output value is held as long as DAC is on
Output from Zero Volt to Reference Voltage

In 1024 steps
Selectable Conversion speed vs. power

Settling time 1us, up to 350uA
Settling time 2.5us, up to 700uA
Selective power down
CONFIDENTIAL
Hands-On Index
1.
Tools Setup
2.
3.
ADC
4.
Interrupts / Timer
5.
UART / CAN
Hands-On
CONFIDENTIAL
Project: BlinkyADC
Hands-On
Load Project
BlinkyADC
Build and Debug
Simulation
Use Logic Analyzer
Peripheral windows
GPIO P1
ADC -> modify voltage
Run on hardware
Verify change of AD values
with potentiometer
CONFIDENTIAL
UART
CONFIDENTIAL
Serial Communication Interfaces

Two UARTs
I2C
SPI
10100101
10110110
01111000
001
000
00
10
11
01
01
CAN
SSP
0
1010010110110110
CONFIDENTIAL
UART0 / UART1
UART 0
Interface
UART 1
Interface
TxD0
RxD0
TxD1
CTS
DTR
RxD1
DCD
RI
RTS
DTR
Modem
Interface
signals
Maximum possible speed of the UART

3.75 Mbits/sec
CONFIDENTIAL
UART0 / UART1
Register locations conform to 550 industry standard UART
Built-in Baud Rate Generator
16-bit baud rate generator clock divisor made from 2 8-bit divisor
registers: DLM (MSB), DLL (LSB)
Required baud rate: pclk / (16 x Divisor*)
(* if the Divisor is 0x0000, it is treated as 0x0001.)
Fractional baud rate generator (LPC214x, LPC2101-2-3)
Error Detection
Parity, Framing and Overrun Errors detected

Break Interrupt detection
CONFIDENTIAL
UART0 / UART1 (cont.)

16 byte Receive and Transmit FIFOs
Receive FIFO trigger points at 1, 4, 8, and 14 bytes
Break signal can be transmitted
Word Length Select: 5, 6, 7 or 8-bit characters

Stop Bit Select: 1 or 2 stop bits
Parity Select: Odd or Even parity
Supports 6 modem control signals
CTS, RTS, DCD, DSR, DTR and RI functions are selectable
Note:
On 48-pin devices UART 0 has Tx and Rx pins only
CONFIDENTIAL
IIC
CONFIDENTIAL
I2C Bus Interface(s)
I2C
Interface1
2nd I2C
interface
on LPC213x
I2C
Interface2
SDA
SCL
SDA
SCL
Maximum possible speed of the I2C
400Kbits/sec
CONFIDENTIAL
I2C Bus
Fast-I2C compliant bus interface
configurable as Master, Slave, or both
multi-master bus
bi-directional data transfer between masters and slaves
up to 400kb/s
arbitration between simultaneously transmitting masters without
corruption of serial data on the bus
serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
programmable clock rate
CONFIDENTIAL
SPI Interface
MISO
SPI
Interface
MOSI
SPICLK
SS
Maximum possible speed of the SPI

7.5 Mbits/sec
CONFIDENTIAL
SPI Bus
Compliant with Serial Peripheral Interface (SPI)
specification
Combined SPI master and slave function
Maximum data bit rate of 1/8 of the peripheral clock rate
Programmable clock polarity and phase for data
transmit/receive operations
No. of SPI channels:
1
(48-pin devices)
(64/144-pin devices)
CONFIDENTIAL
SSP
CONFIDENTIAL
Serial Synchronous Port (SSP) Interface
MISO1
SSP
Interface
MOSI1
SCK1
SSEL1
Maximum possible speed of the SSP

30 Mbits/sec
CONFIDENTIAL
SSP Interface
Compatible with Motorola SPI, 4-wire TI SSI and
National Semiconductor Microwire bus
Supports multiple slaves and master on the bus but
at any point of time only one master and slave can
communicate
8-Frame FIFOs for both Transmit and Receive
Frame sizes can be from 4 bits to 16 bits
CONFIDENTIAL
USB
CONFIDENTIAL
USB 2.0
Since USB is a standard doesnt that make all
microcontrollers with USB the same?
NO!!
Architectural choices and implementation details make a big
difference in performance and ease of use.
The LPC2148 is a high performance USB device.
CONFIDENTIAL
LPC2148 key high performance

USB features
Flexible endpoint architecture
Supports all 32 USB endpoints
Large data FIFO

Can double buffer full isochronous packets
Flexible DMA capability

USB Buffer is present on the AHB bus
CONFIDENTIAL
Introduction to USB
An Auto-configuring Plug-and-play
Serial Bus
HOST/HUB
PC
Single Master, Half-duplex, Timemultiplexed bus; Tiered Star

topology
HUB
Phone
Monitor
HUB
Kbd
All data communication is initiated

and regulated by the Master; peerto-peer not allowed
Speaker
Pen
Mic
Mouse
USB 2.0 is the latest version of USB

(downward compatible)
CONFIDENTIAL
USB- A Brief History

USB 1.1
Approved on 11/23/99
by the USB Core team
12 Mbps bus
Full-speed (12 Mbps)
Low-speed (1.5 Mbps)
Standard A connector
and standard B
connector
USB 2.0
OTG
Original USB 2.0
Supplements the 2.0
specification released
specification
on April 27, 2000
Connects peripherals
480 Mbps bus
directly to each other
High-speed (480 Mbps)
New mini-A connector

and mini-AB
receptacle
Full-speed (12 Mbps)

Low-speed (1.5 Mbps)
Backward compatible
with USB 1.1
New mini-B connector
CONFIDENTIAL
USB Connections and Terminations

F.S./L.S. USB
Transceiver
R2
D+
D+
R1
Twisted Pair Shielded
(45 ohms Outputs) D-
ZO = 90 ohms15%
5 Meters Max.
R1
Host or
Hub Port
F.S./L.S. USB
Transceiver
D+
(45ohms Outputs)
D-
sb.org
www.usb.org
D- (45 ohms Outputs)
Hub Port 0
or
Full Speed Function
D+
R1
Host or
Hub Port
R1 = 15K ohm5%
R2 = 1.5K ohm5%
Untwisted, Unshielded
3 Meters Max.
R1
R1 = 15K ohms5%
R2 = 1.5K ohms5%
www.usb.org
www.usb.org
F.S. USB
Transceiver
R2
L.S. USB
Transceiver
D- (45 ohms Outputs)
Low Speed Function
www.usb.org
www.us
CONFIDENTIAL
Device Layers
Function
Represents capability delivered by
the device, The primary usage function,
like mouse, audio output, printer, hub, etc.
Function
USB Logical Device
Defines common view of device by host

Manages high-level protocol
Typically controlled by system software
May have multiple functions with multiple endpoints
USB Bus Interface

Physical interface to wire
Manages low-level protocol
USB
USB Logical
Logical
Device
Device
USB Bus
Interface
CONFIDENTIAL
Device Abstractions
End Point
Ultimate data source or sink at the device end
Unique address, unidirectional, transfer characteristics
Each endpoint is unidirectional and has a transfer type associated with its
peripheral
Pipe
Association of endpoint with host SW owner
Interface
Collection of pipes
Map to a capability
Owned by exactly 1 software client
More that 1 interface can be defined in a device
CONFIDENTIAL
Endpoints
Up to 32 (16 pairs) endpoints can reside within a device
All USB transfers are targeted to/from a device endpoint
An endpoint is a buffer used to transmit or receive data
Each endpoint has a direction and an address

The direction is from the hosts perspective
OUT transactions are to the device
IN transactions are from the device
A Control endpoint contains an IN and OUT endpoint

Endpoint 0 is always the Control endpoint
CONFIDENTIAL
Interfaces
Made of 0 or more pipes
Has a client owner
Accesses individual pipes
Shares default pipe
More dynamically configured than devices
CONFIDENTIAL
Pipes
Connect host memory buffer to endpoint FIFO
Stream Type
No USB imposed data format
Unidirectional
Message Type
USB imposed data format
Bidirectional
CONFIDENTIAL
Detailed Host / Device View

Host
Function
Client SW
Interface x
manages an interface
Buffers
Pipe Bundle
to an interface
No USB
Format
manages devices
Default Pipe
to Endpoint Zero
Unspecified
USB Bus
Endpoint 0
- Required, shared
- Configuration access
- Capability control
Endpoint
Zero
Data Per
Endpoint
No USB
Format
SIE
a collection of
endpoints
USB
Framed
Data
USB Bus
Interface
Host
Interface
Controller USB Framed
Data
Transactions
a collection of
Interfaces
USB Device
USB System
Data
Interface
Specific
Device
SIE
USB Wire
Pipe, represents connection

abstraction between two horizontal layers
Data transport mechanism
USB-relevant format of transported data
CONFIDENTIAL
Client Software <-> Function

Host
Host
Client
Client
Software
Software
Buffers
Buffers
Data
Data Flows
Flows
Pipes
Pipes
Endpoints
Endpoints
USB
USB Device
Device
Interface
Interface
CONFIDENTIAL
Communications Layers
Physical
Packets
Transactions
3 phases (token, data, handshake)
Token phase has token packet sent by host
Always present
Packet ID (PID) identifies transaction type
Other phases have 0 or more packets
Transfers
CONFIDENTIAL
Transfers to Transactions
Interface
Interface
Interface
Interface
Pipe
Pipe
Pipe
Device
Device
Driver
Driver
User
User
Params
Params
Interface
Interface
Pipe
Pipe
Pipe
Device
Device
Driver
Driver
Device
Device
Driver
Driver
Client
Client SW
SW
Device
Device
Description
Description
Service
Service
Description
Description
Transfer
Transfer Manager
Manager
Transaction
Transaction
List
List
Requirements,
Limitations
USB
USB System
System SW
SW
and
and
Host
Host Controller
Controller
Transaction
Schedule
Transaction
Schedule
Executor
Executor
Token
Token
Token
Token
Token
Token
Universal Serial Bus
CONFIDENTIAL
USB Protocol Breakdown

Transfer Types
Control
Interrupt
Bulk
Isochronous
Transfer
Transaction
Token Packet
PID
Transaction
Data Packet
Body
CRC
Transaction Types
OUT
IN
SOF (Start of Frame)
SETUP
Handshake Packet
PID Packet IDentifier (16 types)
Body Depended on Packet type
CRC Cyclical Redundancy Check
used for error checking
CONFIDENTIAL
Frames
Full / Low Speed Frame Size (1 ms)

1 ms
Control
Isochronous
Interrupt
Bulk
1 ms
1 ms
SOF packets
marks each
frame tick
CONFIDENTIAL
Data Transfer Types Comparison

Usage
Control
Interrupt
Bulk
Isochronous
Max Data bytes/msec

in low-speed mode
24 bytes (three 8-byte

transactions)
0.8 bytes (8-bytes per 10

msec)
no support
no support
Max Data bytes/msec

in full-speed mode
Error Correction
Guarantee rate of
delivery
Guranteed time
between transfers
Typical uses
832 (thirteen 64-byte

transactions/frame)
yes
64 (one 64-byte
transaction/frame)
yes
1216 (nineteen 64-byte

transactions/frame)
yes
1023 (one 1023-byte

transaction/frame)
no
no
no
no
yes
no
Configuration
yes
Mouse, keyboard
no
Printer, scanner
yes
Audio, video
Note:
frame = 1msec @FS
CONFIDENTIAL
USB Frame Model
Slot
Frame = 1ms
Stereo Audio
Low Speed
BULK
Stereo Audio
BULK
Stereo Audio
BULK
Stereo Audio
BULK
Stereo Audio
BULK
Stereo Audio
BULK
Stereo Audio
BULK
Stereo Audio
BULK
Scanner
Stereo Audio
Interrupt,
Control,
Low Speed
Rx Line
Tx Line
Rx Voice
Tx Voice
SOF
Stereo Audio
BULK
Low Speed
BULK
(not to scale)
CONFIDENTIAL
Transactions
Transactions are always initiated by the Host and therefore thought of
from the Hosts perspective
A Transaction consist of multiple packets and begin when the host
sends one of four Token Packets
OUT notifies the DC that data is being send out from the Host
IN requests that DC send data in to the Host
SOF signals the Start of Frame
SOF signals the Start of Frame
A Data Packet follows the token packet

The Transaction ends with Handshake Packet to report the Status of
the Transaction.
CONFIDENTIAL
Packet Formats
SOF Packet
8 bits
11 bits
PID
FRAME NUMBER
8 bits
Token Packet
Data Packet
PID
5 bits
7 bits
4 bits
ADDR
ENDP
CRC5
5 bits
CRC5
8 bits
0 1023 bytes
16 bits
PID
PAYLOAD
CRC16
8 bits
Handshake Packet
PID
CONFIDENTIAL
Endpoints in LPC2148
Maximum of 32 (16 logical) endpoints
Selectable Double Buffering for Bulk and
Isochronous Data Transfer
Any combinations of Endpoints allowed
Maximum buffer size supported for all endpoints
types
CONFIDENTIAL
USB 2.0 in LPC2148

Fully Compliant with USB 2.0 Spec
Supports 32 physical endpoints
Scalable realization of Endpoints during run time
Double buffering supported for Bulk and Isochronous
Endpoints
Supports DMA transfer on all non-control endpoints
CONFIDENTIAL
USB 2.0 in LPC2148

Supports Control, Bulk, Interrupt and Isochronous endpoints
Supports SoftConnect feature
Supports Good link LED indicator
Flexible clock architecture
Remote wakeup
CONFIDENTIAL
LPC2148 USB Block Diagram

AHB Bus
Using the DMA, the

USB Logic has direct
access to memory
8K AHB
Memory
VPB Bus
DMA
Engine
ATX
PADS
USB Logic
Register
Interface
Endpoint ram
access control
Serial Interface Engine

(SIE)
Force SE0
TX D
OE
D+
D-
RX D
2K FIFO
Receivers
CONFIDENTIAL
Transfer Modes
Slave Transfer Mode
DMA Transfer Mode
CONFIDENTIAL
Slave Mode Transfer

USB Block acts like a slave
It can only issue interrupts to the CPU
Control EP uses this mode of transfer exclusively
CONFIDENTIAL
DMA Mode Transfer

USB Block acts like a Master
Will transfer data directly from the 8K SRAM to the
EP_RAM and vice versa.
For Isochronous transfers, the DMA transfer is
synchronized to the frame interrupt
CONFIDENTIAL
Soft Connect and Good Link LED

Soft Connect
Can connect/re-connect to the host through software
No need to unplug and plug the cable back again
Good Link LED

Needs a shared GPIO pin
Shows indication on a LED if connection is established
CONFIDENTIAL
LPC2148 connections
3.3 volt system power
Vusb bus sense
Good Link
LPC2148
Soft connect_n
Logic level p
channel FET
Philips BSH203
1.5k
ATX
Pad
DD+
D-
Vusb supply
33
33
D+
CONFIDENTIAL
LPC2148 Clock Architecture
LPC2148 clocks
XTAL
Main
PLL
cclk
VPB
divider
USB
PLL
pclk
VPB clock must be 16 MHz

minimum for the USB vpb interface
USB clk
CONFIDENTIAL
CAN
CONFIDENTIAL
NXP LPC2000 Series CAN Controller

Extended Full CAN Controller
2 or 4 CAN interfaces
3 priority controlled transmit buffers per channel
Global filter and buffer system with up to 1024 filters
CAN
Bus
Bus Interface
Bus Interface
CAN
Bus
Status/Control
Registers
CAN
Protocol
Controller
CAN
Protocol
Controller
Transmit
Transmit
Buffer
1
BufferTransmit
2
Buffer 3
Global Acceptance
Filter Table with up
to 1024 filters;
buffered in
Full CAN mode
Host
Interface
Host CPU
Transmit
Transmit
Buffer
1
BufferTransmit
2
Buffer 3
CONFIDENTIAL
LPC CAN controller and SJA1000

Each CAN Controller has a register structure
similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those
devices have been combined in 32 bit words to
allow simultaneous access in the ARM
environment. The main operational difference is
that the recognition of received Identifiers, known
in CAN terminology as Acceptance Filtering, has
been removed from the CAN controllers and
centralized in a global Acceptance Filter.
CONFIDENTIAL
CAN Bus Baud Rate and Bus Length

Up to 1Mbps @ 40m bus length (120 feet)
OR
Up to 1000m bus length (3000 feet) @ 50 kbps
1000
500
Bus lines
assumed to be
an electrical
medium
(e.g.twisted
pair)
200
Bit Rate
[kbps]
100
50
20
10
5
0
10
40 100
200
1000
10,000
CAN Bus Length [m]

CONFIDENTIAL
CAN Bus (1)

CAN (Controller Area Network) features
Serial communications protocol
Efficiently supports distributed real-time control
Very high level of security
Application domain: high speed networks to low cost multiplex wiring
LPC2xxx with CAN have 2 or 4 CAN channels

Can be used as gateway, switch or router among CAN buses
Industrial or automotive applications
CONFIDENTIAL
CAN Bus (2)

Data rates to 1 Mbit/s on each bus
32-bit register and RAM access
Compatible with CAN specification 2.0B, ISO 11898-1
Global Acceptance Filter recognizes 11- and 29-bit Rx
Identifiers for all CAN buses
Acceptance Filter can provide FullCAN-style automatic
reception for selected Standard Identifiers
No. of CAN channels
2 on LPC2119, LPC2129, LPC2290, LPC2292
4 on LPC2194, LPC2294
CONFIDENTIAL
CAN Bus (3)

Acceptance Filtering
Recognition of received Identifiers (Acceptance Filtering) removed
from CAN controllers - now centralized in a global Acceptance
Filter
In a 2KB RAM (512 x 32) software maintains 1 ... 5 tables of
Identifiers RAM can hold up to 1024 Standard Identifiers or 512
Extended Identifiers, or a mixture of both types
CONFIDENTIAL
TIMERS
PWMs
RTC
WATCH-DOG
CONFIDENTIAL
Timer 0 and 1
32-bit Timer
32-bit Capture Registers and Capture Pins
Four on each timer
(48-pin devices three on Timer 0 and four on Timer 1)
Capture event can optionally trigger an interrupt
32-bit Match Registers and Match Pins

Four on each timer
(48-pin devices three on Timer 0 and four on Timer 1)
Interrupt, timer reset or timer halt on match

Match output can toggle, go high, go low or do nothing
CONFIDENTIAL
Timer Capture
Control
Capture Control Register
Capture Input 0
Interrupt Register
Capture Input 1
Timer Control Register
Capture Input 3*
Load
Capture Register 1
Capture Register 2
ENABLE
Capture Register 0
RESET
Capture Input 2
32-bit Timer/Counter
Capture Register 3*
Interrupt
*: not available in 48-pin devices
32-bit Pre-Scaler
PCLK
CONFIDENTIAL
Timer Compare
Match Control Register
Control
Match Output 0
Match Output 1
Match Output 2
External Match Register

Interrupt Register
Match Register 0
Match Register 1
Match Register 3
Interrupt
Timer=MR3
*: not available in
48-pin devices
Timer=MR2
Timer=MR1
Timer=MR0
=
=
=
=
ENABLE
Match Register 2
Timer Control Register

RESET
Match Output 3*
32-bit Timer/Counter
32-bit Pre-Scaler
PCLK
CONFIDENTIAL
Pulse Width Modulator

Dedicated 32-bit PWM timer
similar functionality to Timer0 / Timer1
Three additional match registers for a total of 7

all PWM outputs have the same rate, which is programmable
allows up to 6 single edge controlled or 3 double edge controlled
PWM outputs in any combination
single edge controlled PWM outputs all go high at the beginning of
each cycle and low at a programmed time
double edge controlled PWM outputs can be programmed to be
either positive going or negative going pulses, with edges at any
location in the cycle
CONFIDENTIAL
Pulse Width Modulator

Match Register 0
Match
Latch Enable 0
Shadow Register 0
=
Interrupt
Control
R EN
S
PWM1
Enable
R EN
PWM2
Enable
32-bit Timer Counter

32-bit Pre-Scaler
PCLK
R EN
PWM6
Enable
CONFIDENTIAL
Single-Edge Controlled PWM

PWM outputs all go high at the beginning of each cycle and
go low on a Match
Match Register 0 Value
Compare (Match) Value z
Compare (Match) Value y
Compare (Match) Value x
0000 0000h
er
m
i
T ue
l
Va
PWMx
PWMy
PWMz
CONFIDENTIAL
Double-Edge Controlled PWM

Double edge controlled PWM outputs can have either edge
occur at any position within a cycle
Match Register 0 Value (100)
(PWM Period)
MR5=65 (PWM5)
MR3=53, MR4=27 (PWM4)
MR1=41, MR2=78 (PWM2)
0000 0000h
PWM2
r
Time
e
Valu
PWM4
PWM5
(single-edge)
CONFIDENTIAL
Hands-On Index
1.
Tools Setup
2.
3.
ADC
4.
Interrupts / Timer
5.
UART / CAN
Hands-On
CONFIDENTIAL
Project: SerialRTC
Hands-On
Load Project
SerialRTC
Build and Debug
Simulation
Use Serial Window #2
Target Hardware
Use terminal program
set to 9600bps
CONFIDENTIAL
Watchdog Timer
Once activated, the Watchdog will reset the entire chip if it is
not fed regularly
Feed is accomplished by a specific sequence of data writes
Watchdog flag allows software to tell that a watchdog reset
has occurred
Selectable overflow time (s ... minutes)
Debug Mode generates an interrupt instead of a reset
Secure: watchdog cannot be turned off once it is enabled
Watchdog Timer value can be read in one cycle
CONFIDENTIAL
Watchdog Timer
PCLK
/4
32-bit Down Counter

UNDERFLOW
WDFEED
Watchdog Timer
Constant
Current Timer Count

(WDTC)
WDMOD Register
Sticky bits!
(cleared by WDT
underflow or ext.
reset)
WDEN
WDTOF
WDINT
WDRESET
RESET
INTERRUPT
CONFIDENTIAL
NXP LPC2300/2400
Selected Peripherals
Clock tree
CONFIDENTIAL
Clocking (only for LPC23/24 families)

USB
Clock
Divider
1-24MHz
Main
Oscillator
PLL
system
clock select
4MHz
Internal
R/C
Oscillator
wdclk
pllclk
Fcco
CPU
Clock
Divider
Bypass
Synchronizer
usbclk
(48 MHz)
USB Block
cclk
ARM7TDMI-S
Ethernet
Block
25 or
50 MHz
External
Ethernet
PHY
Other AHB
Peripherals
Watchdog
Timer
Perpipheral
Clock
Generator
watchdog
clock select
pclk
APB
Peripherals
RTC
Prescaler
32.768kHz
rtcclk
RTC
Oscillator
Real Time
Clock
RTC clock
select
CONFIDENTIAL
PLL details on LPC23/24
CCK or CCLK/2 or CCLK/4
1..128
Fosc: 32Khz 50Mhz
Fcco = 275-550 Mhz
M = 132768
N = 1..256
CONFIDENTIAL
LPC23/24 clocking
The LPC2300 has three clock sources
External oscillator 1Mhz 24 Mhz
External watch crystal 32.756 Khz
Internal RC oscillator approx 4 Mhz
The LPC2300 has three clock sources Fcco = (2 x M x Fin)/N

Were 32Khz < Fin < 50Mhz
Were 275Mhz < Fcco < 550Mhz
Also Fcco must be kept to a minimum to reduce power consumption
The USB peripheral requires a precise 48Mhz clock source
CONFIDENTIAL
NXP LPC2300/2400
Selected Peripherals
LPC2300 Peripherals SD/MMC
CONFIDENTIAL

Conformance to Multimedia Card Specification v2.11.
Conformance to Secure Digital Memory Card Physical Layer
Specification, v0.96.
Use as a multimedia card bus or a secure digital memory card bus
host. It can be connected to several multimedia cards, or a single
secure digital memory card.
DMA supported through the General Purpose DMA Controller.
CONFIDENTIAL
Multimedia Card Interface

MCICLK
Control
Unit
APB Bus
APB
Interface
Adapter
Registers
MCIPWR
Command
Path
Data Path
MCICMD
MCIDATA [3:0]
FIFO
CONFIDENTIAL
LPC2300 Peripherals BASIC TRAINING
SD/MMC/SDIO
CONFIDENTIAL 331

SD/MMC memory card interface (LPC2368 & LPC2378)
Conformance to Multimedia Card Specification v2.11.
Conformance to Secure Digital Memory Card Physical Layer
Specification, v0.96.
Use as a multimedia card bus or a secure digital memory card bus host.
It can be connected to several (~4 based on I/O pin loading) multimedia
cards, or a single secure digital memory card.
DMA supported through the General Purpose DMA Controller.
OR
CONFIDENTIAL 332
LPC2300 Peripherals SD/MMC BASIC TRAINING

SD Secure Digital (LPC23xx = 25Mbit/s)
Developed as improvement on MMC

Up to 128 Gbyte per card
Low speed up to 400Kbit/s
High speed up to 100Mbit/s
MMC Multi-Media Card (LPC23xx 20Mbit/s)
1, 4, or 8 bits per interface

Up to 8Gbyte per card
Slightly thinner than SD cards
Pin-compatible with SD cards
SDIO small devices that use the SD physical format

for other functions beyond storage
GPS, WiFi, BlueTooth, Modems, FM Radio, RFID,
Barcode, etc., etc.
Additional interconnect functionality required
May require interrupt line (SD interface does not provide)
http://en.wikipedia.org/wiki/Secure_Digital_card
CONFIDENTIAL 333
I2S Features
The I2S input and output can each operate independently in both master and
slave mode.
Capable of handling 8, 16, and 32 bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range (in practice) from 16-48 kHz.
Word Select period in master mode is configurable (separately for I2S input
and I2S output).
Transmit and receive functions each have an 8 byte data FIFO.
Programmable FIFO level interrupts.
Two DMA requests, controlled by programmable FIFO levels.
Controls include reset, stop and mute options separately for I2S input and I2S
output.
CONFIDENTIAL
I2S Diagrams
SCK: serial clock
Transmitter
(master)
WS: word select

SD: serial data
SCK: serial clock
Receiver
(slave)
Transmitter
(slave)
WS: word select

SD: serial data
Receiver
(master)
Controller
(master)
SCK
Transmitter
(slave)
WS
SD
Receiver
(slave)
SCK
WS
MSB
SD
Word n-1
Right Channel
LSB
Word n
Left Channel
MSB
Word n+1
Right Channel
CONFIDENTIAL
NXP LPC2300/2400
Ethernet
CONFIDENTIAL
External Memory Controller, ARM PrimeCellTM

SDR SDRAM memory support.
Asynchronous static device support including RAM, ROM, and Flash.
Low transaction latency.
Read and write buffers reduce latency and improve performance.
8-bit, 16-bit, and 32-bit wide static memory support.
Static memory features include:
Asynchronous page mode read.

Programmable wait states.
Bus turnaround delay.
Output enable, and write enable delays.
Extended wait.
Four chip selects each for SDRAM and static devices.

Power-saving modes dynamically control CKE and CLKOUT.
Support for dynamic memory self-refresh mode.
Supports 2K, 4K, and 8K row address synchronous memory parts.
Typically 512, 256, and 128 MB parts with 4, 8, 16, or 32 bits per device.
Separate reset domains allow for auto-refresh through chip reset.

CONFIDENTIAL
External Memory Controller Block Diagram

EMC
A[23:0]
D[31:0]
Shared
Signals
AHB Bus
WEn
AHB slave
register
interface
AHB slave
memory
interface
OEn
Data
Buffers
Memory
controller
state
machine
BLSn[3:0]
Pad
Interface
Static
Memory
Signals
CSn[3:0]
DYCSn[3:0]
CASn
RASn
CLKOUT[1:0]
Dynamic
Memory
Signals
CKE[3:0]
DQM[3:0]
CONFIDENTIAL
Advanced Vectored Interrupt Controller,

Standard ARM PrimeCellTM
Mapped to AHB address space for fast access.
Supports 32 vectored IRQ interrupts.
16 programmable interrupt priority levels.
Fixed hardware priority within each programmable priority level.
Any input can be assigned as an FIQ interrupt.
Software interrupt generation.
CONFIDENTIAL

Interrupt Request, Masking, and Selection
SoftIntClear
[31:0]
IntEnableClear
[31:0]
SoftInt
[31:0]
IntEnable
[31:0]
Status Registers and FIQ Generation

VICINT
SOURCE
[31:0]
FIQStatus
[31:0]
IRQStatus
[31:0]
RawIntr
[31:0]
FIQ
FIQStatus
[31:0]
IRQStatus
[31:0]
IntSelect
[31:0]
Prioritization and Vector Generation

Vectored Interrupt 0
IRQStatus
[0]
SW PriorityM ask [31:0]

D
SW PriorityM ask [0]

HW PriorityMask [0]
VectPriority0
[4:0]
IRQStatus
[1]
SW PriorityM ask
[31:0]
HW PriorityM ask [31:0]
Priority
Masking
Logic
VectAddr0
[31:0]
VectIRQ0
Vect Addr0
[31:0]
VectIRQ1
IRQ
Priority
Logic
Vector Select
for highest priority
interrupt
Vect Addr1
[31:0]
VectAddr
[31:0]
IRQStatus
[31]
Vect
AddrOut
VectIRQ31
Vect Addr31
[31:0]
CONFIDENTIAL
DMA (1)
Two DMA channels, each with a four-word FIFO.
16 peripheral DMA request lines. Some of these are connected to peripheral
functions that support DMA: the SD/MMC, two SSP, and I2S interfaces.
One 32-bit AHB bus master interface.
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
CONFIDENTIAL
DMA (2)
Scatter or gather DMA is supported through the use of linked lists.
Hardware DMA channel priority: channel 0 is higher priority than channel 1.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size.
8, 16, and 32-bit wide transactions.
Big-endian and little-endian support. Little-endian is the default.
An interrupt can be generated on a DMA completion or error.
CONFIDENTIAL
GPIO Interrupts
APB
Bus
GPIO
Pin
Write 1 to
GPIOIntClr
1
APB
Bus
GPIOIntStat
R Register
(Read Only)
Rising Edge
Enable Register
(GPIOIntEnR)
GPIOIntStatus
Register
Port Int
D Q
Pin
Int
Port
Wakeup
Other Port Ints

plus one existing
interrupt
Wakeup
D Q
Falling Edge
Enable Register
(GPIOIntEnF)
VIC
Interrupt
GPIOIntStatF
Register
(Read Only)
Replicated for each

related GPIO pin
Other
Pin Ints
GPIOWake
(from IntWake
Register)
Replicated for each

related GPIO port
Other Port
Wakeups
Once per chip
CONFIDENTIAL
512 KB
Flash
ARM7TDMI-S
Internal
SRAM
Controller
Internal
Flash
Controller
16 KB
SRAM
ARM7 Local Bus
MII
or
RMII
AHB2
Ethernet
MAC with
DMA
16 KB
SRAM
AHB
Bridge
AHB
Bridge
AHB to
Master
Port AHB Bridge
APB
Divider
Slave
Port
RST
Xtal2
Xtal1
Trace
Signals
TDO
TDI
TCK
Emulation Trace
Module
64 KB
SRAM
TMS
TRST
Ethernet MAC System Connections
PLL
System
Functions
System
Clock
Internal RC
Oscillator
Vectored
Interrupt
Controller
External
Memory
Controller
GP DMA
Controller
USB with
4KB RAM
& DMA
A[23:0],
D[31:0],
etc.
AHB1
D+, D-,
etc.
AHB to
APB Bridge
APB
CONFIDENTIAL
Transmit
DMA
Transmit
Retry
Receive
DMA
Receive
Buffer
RMII
MII or
RMII
MII
Ethernet PHY
Transmit
Flow
Control
RMII adapter
Host
Registers
Ethernet MAC
DMA
Interface
(AHB master)
Bus
Interface
Register
Interface
(AHB slave)
Bus Interface
AHB Bus
Ethernet Block Diagram
MIIM
Receive
Filter
Ethernet Block
CONFIDENTIAL
Ethernet Basic Features

General:
10/100MBps Ethernet MAC
PHY interface, including MII and RMII (on LPC2300 RMII only)
List of recommended devices in datasheet
Internal scatter/gather DMA controller

Semi-dedicated 16K byte on-chip RAM
Can access other memory areas (including off-chip)
except the Flash and main SRAM
CONFIDENTIAL
Ethernet Features: Standards

Ethernet standards supported:
Supports 10 or 100 Mbps PHY devices including 10Base-T, 100Base-TX,
100 Base-FX, and 100Base-T4.
Fully compliant with IEEE standard 802.3.
Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
Flexible transmit and receive frame options.
VLAN frame support.
CONFIDENTIAL
Ethernet Features: Memory Transfers

Memory management:
Independent transmit and receive buffers memory mapped to shared
SRAM.
DMA managers with scatter/gather DMA and arrays of frame descriptors.
Memory traffic optimized by buffering and pre-fetching.
CONFIDENTIAL
Ethernet Advanced Features

Receive filtering.
Multicast and broadcast frame support for both transmit and receive.
Optional automatic FCS insertion (CRC) for transmit.
Selectable automatic transmit frame padding.
Over-length frame support for both transmit and receive allows any
length frames.
Promiscuous receive mode.
Automatic collision backoff and frame retransmission.
Includes power management by clock switching.
Wake-on-LAN power management support allows system wake-up:
using the receive filters or a magic frame detection filter.
CONFIDENTIAL
Ethernet Features: Physical Layer

Physical interface:
Attachment of external PHY chip through standard Media Independent
Interface (MII) or standard Reduced MII (RMII) interface, software
selectable.
PHY register access is available via the Media Independent Interface
Management (MIIM) interface.
NOTE: LPC23xx has RMII only
CONFIDENTIAL
PHY Interface MIIM

(Media Independent Interface Management)
MIIM Pin
# of Pins
Function
MDC
Clock
MDIO
Combined data input, data output, and data output

enable. The protocol defines how and when the
direction changes.
Total:
CONFIDENTIAL
PHY Interface MII

(Media Independent Interface)
MII Pin
# of Pins
Function
TX_EN
Transmit data enable
TXD[3:0]
Transmit data output
TX_ER
Transmit error
TX_CLK
Transmitter clock
COL
Collision
CRS
Carrier sense
RX_DV
Receive data valid
RXD[3:0]
Receive data input
RX_ER
Receive error
RX_CLK
Receiver clock
Total:
16
CONFIDENTIAL
PHY Interface RMII

(Reduced Media Independent Interface)
RMII Pin
# of Pins
Function
TX_EN
Transmit data enable
TXD[1:0]
Transmit data output
RXD[1:0]
Receive data input
CRS_DV
Carrier sense / Data valid
RX_ER
Receive error (optional, depending on application)
REF_CLK
Reference clock input
Total:
CONFIDENTIAL
CAN Interface incompatibilities within

LPC2000 derivatives
To conserve power, CAN peripherals are powered down after reset on
the latest derivatives
Code must manually enable the power for the CAN interfaces used
When using the filter tables, the numbering of CAN interfaces might vary
In some implementations CAN interfaces are numbered 1 and 2
In some implementations CAN interfaces are numbered 0 and 1
CONFIDENTIAL
Other Peripherals
USB with Device, Host, and OTG.
UARTs (4), one with modem control, one with IrDA.
CAN (2 channels).
SD / MMC Card Interface.
SPI (1) & SSP (2). SPI shares pins with SSP0.
Timers (4), each with capture/compare.
Watchdog Timer.
DAC output.
CONFIDENTIAL
Thank You!

1 Day Arm 20071088

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Standard Microcontroller

1-day ARM Training

Standard Microcontroller Cores

NXP Embedded Flash Process Roadmap

0.18 0.16 0.14

Process Feature Size

NXP Standard Microcontrollers

History - NXP a leader in ARM

NXP offers the most experience

NXP is a long-term ARM licensee

ARM vs. other 32/16-bit Emb. Architectures

Source: SEMICO Research, Q4 2002

ARM : Leading solution for Industrial / Automotive,

Subject/Department, Author, MMMM dd, yyyy

Million USD Revenues of ARM Holdings PLC

M Unit Shipment of ARM based products

Shipments of all ARM products

ARMs partners shipped 1,662 Mpcs in 2005 (+31%)

ARM7TDMI-S NXP Choice

T- Thumb architecture extension

D- Core has debug extensions

16/32-bit ARM7 LPC2000

1.8V and 3.3 V

UART(2), I2C, USB

LPC2214 /01 Flash Security

100 - 144 pins

Flash Security SPI(2), RTC

Timing/features/packages of non released parts may

Roadmap 32-bit portfolio

LPC2366 Ethernet (RMII)

Feature and performance improvements

/00 Versions Status

Reset.1 bug fixed

/01 Versions Status

All bugs corrected excepted core.1

LPC2104/5/6 Block Diagram

VLSI Peripheral Bus (VPB)

ARM Local Bus

VLSI Peripheral Bus (VPB)

ARM Local Bus

VLSI Peripheral Bus (VPB)

ARM Local Bus

LPC2220 Flashless 72 MHz

VLSI Peripheral Bus (VPB)

LPC213x Block Diagram

VLSI Peripheral Bus (VPB)

LPC213x Series Overview

ISP, IAP, Parallel Programmer Support

LPC213x Series Overview

3.3V Single-Voltage Supply

Brown Out Detection (BOD @ 2-stage monitoring of the voltage)

Power On Reset (POR)

LPC213x Series Overview

LPC213x Series Overview

LPC2142/44/46/48 Block Diagram

AMBA AHB Bus

Has 1.8V Regulator. Only 3V input needed

VLSI Peripheral Bus (VPB)

Subject/Department, Author, MMMM dd, yyyy

LPC214x Series Overview

3.5 times faster than older I/O!

3.3V Single-Voltage Supply

32KHz RTC with Vbat input