Gengyus Reference Model

Need to design something of this type or even this might work out for our project.

Cache Interface
Signal:

Dir:

Description:

clk

in

clock

rst_n

in

Active low reset

addr[13:0]

in

Address. Lowest 2-bits not used (4-words/line)

wr_data[63:0]

in

Data to be written to cache line

wdirty

in

Hold high while writing to mark a line as dirty

we

in

Write enable to write a line to the cache

re

in

Read enable

rd_data[63:0]

out

Cache line read out

tag_out[7:0]

out

Tag bits for the cache line. Need this when evicting line
from cache

hit

out

Hit means the tag bits matched and the line was valid

dirty

out

Cache line has been modified. Need to write back.

toggle

in

Used to maintain LRU for 2-way set associative data cache,

will be discussed in the following bonus part

a) Unified Memory Interface

Signal:

Dir:

Description:

clk

in

Clock

rst_n

in

Active low reset

addr[13:0]

in

Address. Lowest 2-bits not used (4-word access)

re

in

Read enable

we

in

Write enable

wdata[63:0]

in

Data to write to 4-word line

rd_data[63:0]

out

64-bit line read

rdy

out

Indicates operation (read/ write) is complete this cycle

Mem_hierachy.v will have the state machine that will implement the state machine.
In this state Machine we will try to access the cache.v and unified_memory.v.