Switching Characteristics

Analytical Delay Model

Derivation of fall time (tf)
In saturation,
Idsn (Isat,nmos)=IC (CL discharging current)

dV
2
n VGS Vtn C L
2
dt
n
dVout
2

VDD Vtn CL
2
dt
2CL
dt
dVout
2
n VDD Vtn
0.9VDD
2C L
tf1
dVout
2 V V
n VDD Vtn DD tn
2C L
tf1
Vout V0.DD9VDDVtn
2
n VDD Vtn
2C L
tf1
0.9VDD VDD Vtn
2
n VDD Vtn
2C L Vtn 0.1VDD
tf1
2
n VDD Vtn
When nMOS is operating in linear region,
Idsn (nMOS current in linear region)=IC (CL discharging current)

V2
dV
n VGS Vtn VDS DS C L
2
dt

dt

CL

dVout
2

Vout
n VDD Vtn Vout 2

CL
tf 2
dVout
2

Vout
n VDD Vtn Vout
2VDD Vtn

V DD Vtn
CL
dVout
tf 2
2

0
.
1
V
Vout
n VDD Vtn DD
Vout
2VDD Vtn
Now, let us take
CL
A
n VDD Vtn
Vout=x
2 VDD Vtn =R

Then, t f 2 A

V DD Vtn

0.1V DD

dx
x2
x
R

Rdx
Rx x 2
Rdx
A
x( R x)
VDD Vtn 1
1
A

dx

0.1VDD
x R x
A

Aln x ln( R x)0.DD1VDDtn

V

VDD Vtn

Aln
R x 0.1VDD

VDD Vtn
0.1VDD
A ln
A ln

R (VDD Vtn ) (VDD Vtn )

2(VDD Vtn ) 0.1VDD

VDD
A ln 1 A ln

20(VDD Vtn ) VDD

20VDD 20Vtn VDD
A ln

VDD

19VDD 20Vtn
A ln

VDD

t f 2

CL

n VDD

19VDD 20Vtn
ln

Vtn
VDD

Now, tf = tf1+tf2
19VDD 20Vtn
2C V 0.1VDD
CL
L tn

ln

2
n VDD Vtn
VDD
n VDD Vtn

2CL Vtn
0.1VDD
V
CL
V
DD

ln 19 20 tn
2

V
DD

V
n 1 tn
VDD

n 1 tn V V DD2
VDD

DD

Vtn
n
VDD
2C n 0.1VDD
CL
L

ln 19 20n
2 2
n 1 n VDD
n 1 n V DD

Taking,

tf

n 0.1 1

2C L
ln 19 20n

nVDD 1 n 1 n 2

For approximation,
CL
2 n 0.1 1
tf
ln 19 20n

1 n 1 n 2
nVDD
k

CL
nVDD

Where k=3 to 4 for values of VDD=3 to 5V and Vtn=0.5 to1V.