Switching characteristics

Analytical Delay Model

Mohammad Shafquatul Islam

Switching characteristics
Switching speed of CMOS gate is limited by time taken to charge or
discharge load capacitance CL
Input transition results in an output transition
Either charges CL to VDD or discharges CL to VSS
Define some terms:
Rise time, tr= time for waveform to rise from 10% to 90% of its
steady-state value
Fall time, tf= time for waveform to fall from 90% to 10% of its
steady-state value
Delay time, td= time difference between input transition (50%) and
50% output level. This is the time taken for a logic transition to pass
from input to output

Switching characteristics

Analytical delay model- Fall time

The trajectory of n-transistor operating point as input voltage Vin(t)
changes from 0V to VDD
Initially n-device cut-off and CL charged to VDD : X1
Application of step voltage (VGS= VDD) at input changes operating point to
X2
Onwards, trajectory moves VGS= VDD characteristic curve towards X3 at
origin

Fall time

Fall time tf consists of two intervals:

tf1= period for which capacitor voltage V0 drops from 0.9VDD to (VDD- Vtn)
tf2= period for which capacitor voltage V0 drops from (VDD- Vtn) to 0.1VDD
Equivalent circuits:

Fall time
From previous, while in saturation:

Integrating from t= t1, Vout=0.9VDD to t= t2, Vout= (VDD-Vtn):

Fall time
When n-device in linear region, discharge current is no longer constant
tf2 to discharge capacitor voltage from (VDD-Vtn) to 0.1VDD :

The complete term for fall time, tf :

tf can be further approximated as

Fall time

where k= 3 to 4 for values of VDD=3 to 5V and Vtn= 0.1 to 1V

Directly proportional to load capacitance - minimize load capacitance for highspeed circuits
Inversely proportional to supply voltage lowering supply reduces speed
Inversely proportional to - width increased, delay decreases

Rise time
Due to symmetry of CMOS circuit, similarly rise time can, tr:

For equally sized n- and p-transistors, where n= 2p

 Fall time faster than rise time due to different carrier mobilities (n=2p)
For same rise and fall time for an inverter, we need:

So, channel width for p-device must be increased to approximately 2 to 3

times of n-device:

Delay time
Delay is approximately given by