Thit k h thng s vi Altera FPGA dng Verilog HDL

Vi s pht trin cng ngh bn dn, s phc tp ca cc mch s ngy cng gia tng n mc
ngi thit k mch khng th thc hin cc thit k ca mnh m khng c s tr gip ca cc
cng c t ng thit k in t (CAD) hin i. Phng php lun thit k cho cc h thng s
v mch tch hp s chuyn t thit k logic truyn thng v dng gin (schematic) n
ngn ng m t phn cng (Hardware Description Language HDL) v phng php tng hp.
Verilog HDL l mt trong hai ngn ng m t phn cng c s dng ph bin nht hin nay.
Hu ht cc cng ty v thit k vi mch Vit Nam u s dng ngn ng ny v tnh n gin,
gn gi, hiu qu v d s dng ca n.

Kha hc s cp n vic s dng Verilog HDL trong tng hp mc cao ca cc thit k h

thng s. Kha hc cng hng n ngn ng Verilog HDL cng nh cch s dng n m t,
m phng v tng hp nhiu module s khc nhau. Cc vn tng hp v lp trnh Verilog
HDL cho cc h t hp v h tun t bao gm c my trng thi (Finite State Machine FSM)
cng s c tho lun. Ngi hc khng ch hc ngn ng thng qua lp trnh, m phng, tng
hp cc thit k thc t m cn tng hp v kim tra cc thit k vi cc gi phn mm chuyn
dng v FPGA.
Khong thi gian 32 tit ca kha hc s bao gm cc bi ging v ngn ng Verilog HDL, cc
bi th nghim v lp trnh, tng hp v m phng cc thit k, cng vi mt ti m sinh
vin s c hng dn thc hin mt thit k hon chnh t vic m t bng Verilog HDL,

tng hp, m phng v ci t n trn FPGA. Sau khi hon tt kha hc hc vin c th t tin
thc hin cc ti thc t cng nh cc n m hc v lun vn tt nghip sau ny.
1) Ai nn tham gia kha hc
- Sinh vin mun dng Verilog HDL thit k cc h thng s hoc mun nm c kin
thc v Verilog HDL v tng hp mc cao.
- Sinh vin mun dng Verilog thit k mt CPU hon chnh v ci t ln FPGA.
2) Nhng iu bn s t c sau kha hc ny
- Cu trc c bn ca Altera FPGA.
- C bn v Verilog HDL.
- Cch thc lp trnh Verilog HDL tng hp c (synthesis).
- Thit k cc h thng s vi Verilog HDL.
- Bit cch thit lp cc rng buc v thi gian cho Altera FPGA (UCF)
- Thit k c cc thnh phn c bn: b cng/tr, b m, b nhn trn FPGA
- Thit k c cc thnh phn nng cao nh my trng thi (finite state machine), b nh
trn FPGA.
- Thit k mt CPU n gin bng cch vn dng cc thit k thc hin cc ngy
trc v ci t trn Altera FPGA.
- c cp chng ch tham gia kha hc??
3) Kin thc cn bit trc tham gia kha hc (Prerequisites)
- K thut s

4) cng
Ngy 1:
C bn v Verilog
- Cc kiu d liu
- Cc ton t, ton hng
- M t module
- M t cu trc v php gn ng thi
(continuos assignment)
- M hnh hnh vi
- Pht biu blocking v non-blocking
- Vector v mng
Cu trc iu khin
- Cu trc iu kin
- Cu trc vng lp
Ngy 2
Verilog cho mch t hp
- Cch vit Verilog to ra mch t hp.
- MUX, Decoder v Encoder
- B so snh v kim tra chn l
- ALU n gin, bus v b m ba trng
thi
Hm (function) v tc v (task)
B nh:
- M hnh ROM, RAM
- Khi to b nh
Gii thiu v mch tun t: D Flipflop
Ngy 3
Verilog cho mch tun t
- Cch vit verilog to ra mch tun t
- Thanh ghi, thanh ghi dch v tp thanh
ghi.
- B nh
- B m
My trng thi:
- My trng thi Moore
- My trng thi Mealy
S dng Megafunction ca Altera
Ngy 4 (Thit k CPU n gin)
Thit k mt CPU n gin
- S khi ca CPU
- Thit k khi datapath (tp thanh ghi,
alu, b nh)

Chng trnh kim tra (testbench)

Cu trc v c im ca FPGA
- Kin trc v c im ca FPGA
- Ti nguyn FPGA
- FPGA vs CPLD
Lab 1: Thit k v m phng b cng ton
phn (full adder)
Lab 2: Thit k v ci t b cng/tr 4 bit trn
FPGA DE2 board.
Lab 3: Thit k b nhn 4-bit v ci t trn
FPGA
Lab 4: Thit k b MUX 8 1.
Lab 5: Thit k v ci t b gii m led 7
on anode chung.
Lab 6: Thit k v ci t ALU n gin hin
th kt qu ln led 7 on
Lab 7: Thit k b nh (s dng LPM)
Lab 8: Thit k counter

Lab 9: Thit k v ci t b pht hin cnh

ln v cnh xung ca mt tn hiu ng vo
Lab 10: Thit k v ci t b pht hin mt
chui s ng vo
Lab 11: Thit k tp thanh ghi
Lab 12: Thit k giao tip SRAM

Thit k khi control unit

Kt ni h thng, kim tra v ci t trn
FPGA DE2 board.

Hng son ti liu:

-

Tp trung cho sinh vin lm nhiu lab kim chng l thuyt va hc (30 l thuyt ri
lm 1 bi lab). Cc lab nu trong cng c th c chia nh ra thnh nhiu lab
nh hn.

Cc bi lab c son di dng: Sinh vin c cho sn sn ca bi lab, do sinh

vin ch phi vit thm cc on cn thiu thc hin yu cu ca m bi lab nu ra
(nhm tit kim thi gian)

Ngi son c th tham kho 10 bi lab ca Altera (c bit l t lab 6 10) lm

phong ph thm ni dung bi ging.

Laboratory Exercises (Altera)

Lab 1 - Switches, Lights, and Multiplexers

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Lab 2 - Numbers and Displays

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Lab 3 - Latches, Flip-flops, and Registers

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Lab 4 - Counters

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Lab 5 - Timers and Real-Time Clock

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Lab 6 - Adders, Subtractors, and Multipliers

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The purpose of this exercise is to examine arithmetic circuits that

add, subtract, and multiply numbers. Each type of circuit will be
implemented in two ways: rst by writing Verilog code that
describes the required function-ality, and second by making use of
predened subcircuits from Alteras library of parameterized
modules (LPMs).
The results produced for various implementations will be compared,
both in terms of the circuit structure and its speed of operation.
Lab 7 - Finite State Machines
We wish to implement a nite state machine (FSM) that recognizes
two specic sequences of applied input sym-bols, namely four
consecutive 1s or four consecutive 0s. There is an input w and an
output z.
We want to design a modulo-10 counter-like circuit that behaves as

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follows. It is reset to 0 by the Reset input. It has two inputs, w1 and

w0, which control its counting operation. If w1w0 =00, the count
remains the same. If w1w0 =01, the count is incremented by 1. If
w1w0 =10, the count is incremented by 2. If w1w0 =11, the count
is decremented by 1. All changes take place on the active edge of a
Clock input.
Design a circuit that should scroll the word "HELLO" such that the
letters move from right to left in intervals of about one second
Lab 8 - Memory Blocks

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A tutorial to use memory in a certain design, we will consider two

different ways of implementing this memory: using dedicated
memory blocks in an FPGA device, and using a separate memory
chip
Lab 9 - A Simple Processor

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Design a simple processor that contains a number of 16-bit

registers, a multiplexer, an adder/subtracter unit, a counter, and a
control unit.
mv Rx,Ry ; Rx [Ry]
mvi Rx,#D ; Rx D
add Rx,Ry ; Rx [Rx]+[Ry
sub Rx,Ry Rx [Rx] [Ry
Lab 10 - An Enhanced Processor:
Three more instructions are added to simple processor:

ld Rx,[Ry] Rx [[Ry]]
st Rx,[Ry] [Ry] [Rx]
mvnz Rx,Ry if G != 0, Rx [Ry]

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