Page 1

CU LC B NGHIN CU KHOA HC KHOA IN-IN T

H BCH KHOA TP. H CH MINH

Page 2

CAPTURE
Capture l 1 chc nng ca timer c dng o thi gian
s kin , tnh tc v o thi gian.
S capture block ph thuc s lng CCR m n c. Nh
MSP430G2553 TIMERA0 c 3 capture CCR0,CCR1,CCR2
Tn hiu vo ca capture c chn t external pin hay
internal signal bng software.

CAPTURE
Bit CCI c gn vi Input ca Capture.
Capture xy ra khi input ca n c tn hiu kch cnh ln hay xung. Lc :
- Gi tr TAxCCRy = TARx
-CCIFG Interrupt Flag c bt.

CAPTURE

CAPTURE
Ban u khi cha c event xy ra, capture nm trng thi u : No Capture Taken.
Khi c event, th capture chuyn qua trng thi Capture Taken, lc ny gi tr thanh
ghi TARx c lu vo thanh ghi TAxCCRy, c c bt.
Ti y s xy ra 2 trng hp :
- Thanh ghi TAxCCRy c c, h thng chuyn qua trng thi Read Taken
Capture. Nu c capture mi ngay lc ny, th quay v trng thi Capture Taken,
ngc li quay v trng thi No Capture Taken.
- Thanh ghi TAxCCRy cha c c nhng 1 event mi li xy ra, lc ny s
chuyn qua trng thi : Second Capture Taken, gi tr capture c b mt, thay vo gi
tr mi ca event ny, ng thi bit COV c bt ln bo overflow. thot ra khi
trng thi ny, ta phi reset bit COV bng software, khi s quay v trng thi No
Capture Taken.

CAPTURE

CAPTURE
TAxCCTL :
CM (bit 15 v bit 14 ca thanh ghi TAxCCTL) : c dng chn mode cho Capture :
- CM_0 : khng capture ( compare mode)
- CM_1 : capture cnh ln ca input
- CM_2 : capture cnh xung ca input
- CM_3 : capture cnh ln v xung ca input
CCISx : chn source cho chn capture l loit A hay B. Vic chn loi A hay B n s cho ng
vo tng ng vi pin ca MSP c cp trn datasheet. Thng thng ta chn A.
-CCISxA : chn loi A
-CCISxB : chn loi B
- Vcc : chn ngun ni Vcc
-GND : chn ngun ni GND
SCS : ng b clock timer vi gi tr capture v, TI ngh bt bit ny khi capture
CAP : bit quy nh b CCRx chc nng Capture hay Compare

C O M PA R E ( t t )
Ngoi chc nng so snh khi TARx m ti gi tr ca TACCRx, th
thc thi ngt, ta cn c th to xung PWM t nhng ng OUT ca
CCRx vi chu kz v duty cycle ty {.

C O M PA R E
TAxCCTL :

TAxCCTL :

C O M PA R E

CCIE : cho pho ngt khi gi tr TIMER n ti gi tr CCRx tng ng compare mode,
hoc capture c thc thi
OUTMODx : trong ch Compare Mode, ta c th xut tn hiu ra theo mt quy lut
cho trc ca MSP, da vo gi tr ca CCR0,CCR1,CCR2 v Mode ca ng ra nh trong bng sau :

C O M PA R E
V d nh trong OUTMOD 7 : khi timer n ti gi tr TACCR1 th ng ra b
reset. V khi timer m ti TACCR0, ng ra c set ln

TAxCCTL :
** : Cc OUTMOD 2,3,6,7 khng s dng cho OUT0 c.
**Vi OUTMOD 0, ng ra c gi tr ph thuc OUT bit trong TAxCCRL
** Cc OUTx s chu nh hng ca TACCRx . (Xem thm example code)

** Khi thc hin OUTMODE, th phi config I/O pin thnh OUT pin(Xem
datasheet bit c th)
** Tt c cc mode ca Timer u c th s dng chc nng OUT ny, gi tr
ng ra thay i theo OUTMODE khi TARx = TACCRx (TACCRx t trc)
T ng ra , ta c th to c cc xung PWM, c dutycycle thay i c
=> iu khin cc thit b s dng ngun DC nh LED, ng c,.

* Tham kho thm ti a ch :

http://www.diendanti.com/showthread.php?108-MSP430-TUT-6.T%E1%BA%A1o-xung-PWM

Example
y l chng trnh minh ha cho vic setup timer cng nh khai bo cc ngt :
#include <msp430g2553.h>
void Timera0_init();
void Port_init();
void Timera0_init()
{
TA0CTL = TASSEL_2 + MC_1 ;

//Src Clock : SMCLK(1Mhz), UpMode

//** TIMER n ln 1 vi mi 1us
TA0CCTL1 = CCIE+ OUTMOD_7; //Enable ngt CCR1, cho php OUT1 xut ra MODE7
TA0CCR0 = 100;
// Vi MODE 3, CCR0 s l gi tr chu kz xung PWM : 100us ~ 10Khz
TA0CCR1 = 50;
// CCR1 l thi gian Ton ca PWM, trong khong thi gian ny OUT1=1
}
void Port_init()
{
P1DIR |= BIT2;
// 1.2 Output
P1OUT = 0xFF
P1SEL|= BIT2; // Chnh chc nng I/O thnh ng OUT, chn 1.2 l ng ra ca OUT1 theo nh trong
//datasheet ca MSP430
}

Example
void main (void)
{
WDTCTL = WDTPW + WDTHOLD;
Port_init();
Timera0_init();
_BIS_SR(LPM0_bits + GIE);

}
** Ng ra outmode t ng xut xung nu nh config ng, ta khng cn thc thi ngt trong v d ny. Trong thc
t, do c enable bit CCIE, nn khi TARx n ti gi tr ca TACCR1 ta vn c th thc thi ngt nh bi trc-Ngt
CCR1