Bi tp ln kin trc my tnh

2013

TRNG I HC BCH KHOA H NI

VIN IN T VIN THNG

====o0o====

BO CO

BI TP LN KIN TRC MY TNH

TI:

THIT K MIPS 32 BIT

STT

H v tn

MSSV

Lp

Nguyn Quang Hiu

20101516

T1

Phm Trng ng

20101026

T1

L c Vng

20102591

T1

L Hng Nhung

20101969

T4

H Ni, 12/2013
TRNG I HC BCH KHOA H NI
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Bi tp ln kin trc my tnh

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Mc Lc
A.Li m u ....................................................................................................................... 3
B. Ni dung thc hin.......................................................................................................... 4
I. Tng quan v MIPS ...................................................................................................... 4
1.c im k thut ....................................................................................................... 4
2. Lch s dng x l MIPS .......................................................................................... 5
3. Cc dng vi x l thng mi MIPS sn xut ..................................................... 5
4. Kin trc b lnh....................................................................................................... 6
5. Phn loi MIPS ......................................................................................................... 7
6. u nhc, im ca MIPS ....................................................................................... 8
7. ng dng .................................................................................................................. 9
II.Ni dung thc hin ....................................................................................................... 9
1.Yu cu thc hin ...................................................................................................... 9
2.S khi .................................................................................................................. 9
3.Gii quyt xung t.................................................................................................. 16
III.Kt qu ...................................................................................................................... 25
1. S testbench ....................................................................................................... 25
2. Test code, kim th xung t.................................................................................. 25
3. Cc phng n gii quyt m rng: ....................................................................... 27
4. Hng pht trin: .................................................................................................... 28
C.Kt lun .......................................................................................................................... 29

Bi tp ln kin trc my tnh

2013

A.Li m u
Trong qu trnh pht trin ca cng ngh my tnh, con ngi ch to ra hng
ngn loi my tnh khc nhau. Rt nhiu trong s nhng my tnh ny b qun lng i,
ch mt s t cn c nhc li cho n ngy nay. l cc my tnh vi nhng tng
thit k v nguyn l hot ng c o to nn mt tm nh hng ln n cc my tnh
th h sau n. Vic tm hiu v kin trc my tnh gip chng ta c nhng kin thc c
bn hiu nguyn l v cu to ca my, to tin pht trin to ra nhng th h
my tnh ti u hn trong tng lai. Kin trc MIPS c s dng rng ri trong cc
dng my tnh ha silicon, cc h thng nhng, cc thit b in t..Chnh bi vy,
nhm chng em quyt nh lm ti thc hin thit k MIPS 32bit vi chc nng
c bn.
Do trnh cng nh kin thc cn hn ch nn bi tp ln chc chn cn nhiu
sai st, mong c gp kin thc v k nng mn hc ngy cng hon thin hn.

Bi tp ln kin trc my tnh

2013

B. Ni dung thc hin

I. Tng quan v MIPS
MIPS (Microprocessor without Interlocked Pipeline Stages)
L kin trc b tp lnh RISC pht trin bi MIPS Technologies. Ban u kin trc MIPS
l 32bit, v sau l phin bn 64 bit. Nhiu sa i ca MIPS, bao gm MIPS I, MIPS
II, MIPSIII, MIPSIV, MIPSV, MIPS32 v MIPS64.
Phin bn hin ti l MIPS32 v MIPS64.
Cng c mt vi tu chn m rng, baogm MIPS-3D (1 tp lnh n gin cc cu lnh
SIMD v du chm ng thc hin cc tc v v ha 3D), MIPS16e (kh nng nn
vi lnh tit kim khng gian b nh) v MIPS MT (MultirTheading) kin trc a
lung mi c b xung cho h thng.

1.c im k thut
Nm 1981, mt nhm cc nh nghin cu thuc i hc Stanford do John L. Hennessy ng
u bt u mt cng trnh nghin cuv b x l MIP u tin. Khi nim c bn l
nhm tng t xut hiu nng thng qua s dng mt ng ng lnh
(pipelineinstructions), mt cng ngh c bit n t lu nhng li kh pht trin.
Thng thng mt ng ng s m rng vic chy mt cu lnh thnh vi bc, bt u
thc hin bc mt ca cu lnhtrc khi cu lnh trc hon thnh. Trong khi , thit
k truyn thng yu cu phi i cho n khi mt cu lnh hon thnh mi c chy
cu lnh tip theo.Thit k theo pipeline lm gim ng k thi gian dnh ca CPU khi
thc hin lin tip cc cu lnh.
Mc d thit k ny loi tr mt s cu lnh hu dng, ng k nht nh l cc lnh
nhn v chia yu cu nhiu bc, nhng n cho thy hiu sut tng th ca h thng tng

Bi tp ln kin trc my tnh

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ln r rt bi v cc vi x l c th chy xung nhp ln hn rt nhiu. Tuy nhin vic loi

b cc cu lnh trn li khng c cc nh thit k thi by gi ng h. Rt nhiu kin
cho rng thit k kiu ng ng lnh s khng tn ti c ,nu ch thay mt lnh nhn
phc tp bng nhiu lnh cng n gin th lm sao h thng c th nhanh hn c. Tuy
nhin cho thy tc thuc v thit k ng ng,ch khng phi theo cu lnh

2. Lch s dng x l MIPS

Nm 1984, Hennessy ri trng i hc Stanford thnh lp cng ty MIPS Computer
System.H cho ra i thit k u tin l R2000 vo nm 1985, sau pht trin R3000
vo nm 1998. Nhng CPU 32 bit ny tn ti trong sut nhng nm 1980, v c s
dng ch yu trong cc dng my ch SGI.
Nm 1991 MIPS cho ra i b vi x l 64 bit u tin R4000.Tuy nhin MIPS gp kh
khn trong ti chnh trong khi tung sn phm ny ra th trng. Thit k ny rt quan
trng i vi SGI-mt trong nhng khch hng ca MIPS lc by gi, v th SGI mua
li cng ty vo nm 1992 bo v thit k khng b mt i. T MIPS tr thnh mt
cng ty con ca SGI v c bit n bi tn MIPS Technologies

3. Cc dng vi x l thng mi MIPS sn xut

- R2000 : Xut hin trn th trng vo nm 1985, c b sung thm nhiu cu lnh
mi, c th c khi to ch big-endian hay little-endian, c 32 thanh ghi 32bit
, mt trong s m nhim vic x cc ngoi l v by , trong nhng khng c thanh
ghi m iu kin. R2000 cng h tr ti 4 b x l khi 3 b cn li s dng cho mc ch
khc.
- R3000 :b xung thm 32kB cho b nh Cache (v sm c a ln 64kB) cho cc
lnh v d liu, km theo l c ch Cache coherency h tr cho nhiu b x l.R3000
cng bao gm MMU tnh nng ph bin ca h CPUs k nguyn ny

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- R4000 :c a ra nm 1991,m rng tp lnh MIPS h tr y kin trc 64bit,

chuyn FTU vo main to ra mt h thng chip n l, x l vi tc ln n
100Mhz
- R8000 :Ra i nm 1994,l thit k MIPS siu v hng (superscala) u tin,cho php
x l 2 ALU v 2 php tnh nh mi chu k.Thit k ny h tr ti 6 chip v 4MB cache
m rng
- R10000 :Ra i nm 1995,l thit k chip n l,chy vi tc cao hn R8000,c
32kb cache chnh cho cu lnh v d liu
- Ngoi ra cn c R6000,R1 6000,R1 6000A

4. Kin trc b lnh

4.1. Nguyn tc thit k b lnh MIPS
Tnh n gin quan trng hn tnh quy tc (Simplicity favors regularity)
Ch th kch thc c nh(32 bit)
t nh dng ch th (3 loi nh dng)
M lnh v tr c nh(6 bit u)
Nh hn th nhanh hn
S ch th gii hn
S thanh ghi gii hn
S ch a ch gii hn
Tng tc cc trng hp thng dng
Cc ton hng s hc ly t thanh ghi (my tnh da trn c ch load-store)
Cc ch th c th cha ton hng trc tip
Thit k tt i hi s tha hip
3 loi nh dng ch th

4.2. Mt s lnh trong MIPS

MIPS ch cn h tr 32 thanh ghi l , nh s t $0-$31

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Mi thanh ghi c kch thc 32bit(4 byte). n gin v d dng trong vic truy xut
b nh, tt c cc lnh u c chiu di 32 bit.
MIPS h tr cc nhm lnh x l d liu:
- Lnh s hc
- Lnh lun l
- Lnh np lu d liu
Ngoi cc lnh x l d liu, my tnh cn phi h tr cc lnh iu khin qu trnh thc
thi cc lnh
4.3. Nguyn tc lu d liu trong b nh
MIPS lu d liu trong b nh theo nguyn tc Alignment Restriction, ngha l cc i
tng lu trong b nh phi bt u ti a ch l bi s ca kch thc i tng.
Nh vy, t nh phi bt u ti a ch l bi s ca 4.
MIPS lu tr d liu trong b nh theo nguyn tc Big Endian, ngha l i vi gi tr c
kch thc ln hn 1 byte th byte s lu ti a ch thp.

5. Phn loi MIPS

n xung nhp: Thit k, x l 1 lnh trong vng 1 chu k.
o u im:
n gin v d hiu
o Nhc im:
S dng chu k ng h khng hiu qu chu k ng h c t theo lnh
chm nht.
Cc lnh phc tp nh lnh nhn du phy ng: Tn din tch thit k v cn
nhn i mt s khi chc nng (VD. b cng) v chng khng th c chia
s trong cng 1 chu k ng h
a xung nhp:Chia lnh thnh cc pha thc hin: IF, ID, EX, MEM, WB. Mi pha thc
hin trong 1 chu k xung nhp.
o u im:

Bi tp ln kin trc my tnh

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Thi gian thc hin (= s pha) ca mi lnh c iu chnh ty thuc phc

tp ca lnh.
Cc khi chc nng c chia s gia cc pha khc nhau ca lnh do mt khi
chc nng c th khng cn trong ton b cc pha thc hin ca lnh
o Nhc im:
Cc lnh thc hin lin tip nhau.
Lnh trc c thc hin xong mi n lnh sau v vy xut hin khong thi
gian ri gia cc khu.
Pipeline
o u im:
K thut pipeline c a ra tn dng nhng thi gian ri gia cc khu.
K thut pipeline s lm tng tc vi x l.

6. u nhc, im ca MIPS
u im:
B x l truy xut thanh ghi nhanh nht (hn 1 t ln trong 1 giy) v thanh ghi
l mt thnh phn phn cng thng nm chung mch vi b x l.
CPU khng phi i thc hin cc tin trnh n m thc hin cng lc
nhiu tin trnh, do chu k ca tin trnh c thng sut
Khng gian b nh ca my c gii phng nhiu hn do kh nng nn vi
lnh lm chng trnh nh hn
Khuyt im:
Do thanh ghi l mt thnh phn phn cng nn s lng c nh v hn ch.
Do , s dng phi kho lo v phc tp

Bi tp ln kin trc my tnh

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7. ng dng
Thit k MIPS c s dng rng ri trong cc dng my tnh ha silicon,cc h
thng nhng nh TiVo th h 2,cc thit b s dng h iu hnh Windows CE,Cisco
routes v cc my chi game console nh Nitendo 64,Sonyplaystation

II.Ni dung thc hin

1.Yu cu thc hin
MIPS 32 bit thc hin cc lnh c bn +, -, and, or, not, lw, sw, beq.
Thc hin bng ngn ng m t phn cng Verilog HDL.
Gii quyt c cc xung t c bn trong MIPS pipeline.

2.S khi
2.1 S khi tng qut:

y l khi x l chnh ca Mips 32 bit.

o u vo :
Instr[31:0] : M lnh c ly t b nh lnh
ReadData[31:0] : D liu c c ra t b nh d liu.
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o u ra :
MemWrite : Tn hiu iu khin pht ra yu cu ghi vo b nh d liu.
ALUOut[31:0] : D liu sau khi tnh ton t b ALU
WriteData[31:0] : D liu c ghi vo b nh d liu.
PC[31:0] : Tn hiu PC i vo b nh lnh.
2.2 Thit k chi tit:
Sau y em xin lit k vai tr ca mt s khi quan trng ca b vxl MIPS
a) Khi Control Unit :

L khi sinh ra cc tn hiu iu khin cho con Mips khi c lnh ca bn ngoi a
vo di dng m lnh.
u vo : Op[5:0] , Funct[ 5:0] ly t m lnh.
Zero ly t u ra ca khi ALU
u ra : Cc tn hiu iu khin cc khi khc l :
+) Tn hiu a d liu t b nh ra thanh ghi Memtoreg
+) Tn hiu Regwrite, Memwrite
+) Tn hiu chn ALUSrc, PCSrc, RegDst,
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+) Tn hiu ALUControl
b) Khi Register File :

L khi thanh ghi ca con Mips. u vo s l a ch ca cc thanh ghi a vo t

m lnh v d liu quay v thanh ghi t giai on WB. u ra s l d liu nm
trong thanh ghi m a ch lnh tr ti.
u vo : +) RegwriteW : tn hiu cho php c m lnh tng ng vo
thanh ghi qua WB
+) M lnh tng ng ca Rs, Rt : InstrD[25:21], InstrD[20:16]
+) D liu tr v WriteRegW[4:0] v tn hiu kt qu ResultW
u ra : D liu c c trong 2 thanh ghi m m lnh truy cp ti a ch ca n
Readdata1, Readdata2
c) Khi ALU : L khi phc v nhim v tnh ton.
u vo : +) Tn hiu chn loi tnh ton : cng, tr, nhn, chia : ALUControl c
sinh ra t ControlUnit
+) D liu c c t 2 thanh ghi trong tp thanh ghi Register file
Readdata1, Readdata2 32 bit
u ra: +) D liu ra sau khi c tnh ton ALUOut 32 bit.
+) Tn hiu Zero s dng trong lnh r nhnh beq, bne.
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d) Khi SignExt :

Khi c s dng vi nhim v chuyn i d liu dch t 16 bit trong m lnh

thnh 32 bit thc hin cho nhim v tnh ton.
u vo : D liu dch c ly trong 16 bit cui ca m lnh Instr[15:0]
u ra : D liu dich c chuyn thnh 32 bit bng cch ly 16 bit u bng bit th 16
v 16 bit cui l Instr[15:0]. y[31:0] = [16(Instr[15]), Instr[15:0]].
T cc khi trn v mt s khi logic c bn khc ta xy dng c b MIPS a
xung nhp nh hnh v

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a xung nhp ta chia lnh thnh 5 giai on IF, ID, EX, MEM, WB. Mi giai on c
thc hin trong mt chu k. Trong s gm c cc khi chnh nh l khi Control Unit,
khi Register File, khi ALU, khi SignExt.

2.3.

S khi Pipelined.
T MIPS a xung nhp chng ta tin hnh pipeline b vi x l bng cch thm

vo cc thanh ghi trng thi IFID, IDEX, EXMEM, MEMWB, PC. Cc thanh ghi s thc
hin nhim v chuyn tip d liu gia cc khu

a) Stage IFID : Thanh ghi gia 2 giai on IF v ID. Thanh ghi gm 64 bit d liu bao gm
32 bit tn hiu iu khin control signals, 32 bit tn hiu d liu ca PC
u vo : +) Tn hiu clock v reset
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+) Tn hiu iu chnh thanh ghi ghi hoc dng ghi bao gm IF_Flush,
ID_stall
+) D liu sau khi qua giai on IF : [32:0]IF_Instruction , [32:0]IF_PCAdd4
u ra : +) D liu chun b vo giai on ID : [32:0]ID_Instruction, [32:0]ID_PCAdd4
b) Stage IDEX stage : Thanh ghi gia 2 giai on ID v EX. Thanh ghi chuyn tip 118 bit
d liu bao gm 64 bit d liu ca 2 thanh ghi, 32 bit d liu dch, 15 bit m lnh ca Rs,
Rt, Rd v 7 bit lu tn hiu iu khin.
u vo : +) Tn hiu clock,reset.
+) Tn hiu iu khin c lu li ID_RegWrite, ID_MemtoReg,
ID_MemWrite, ID_ALUControl[2:0], ID_ALUSrc,ID_ RegDst.
+) D liu 32 bit c t 2 thanh ghi SrcA, SrcB, d liu dch 32 bit
SignExtlmm.
+) Bit trong m lnh th hin Rs, Rt, Rd 5 bit.
+) Tn hiu x l xung t FlushE.
u ra : +) Tn hiu iu khin c ly ra cho giai on tnh ton EX_RegWrite,
EX_MemtoReg, EX_MemWrite, EX_ALUControl[2:0], EX_ALUSrc, EX_RegDst.
+) D liu 32 bit c t 2 thanh ghi SrcA, SrcB, d liu dch 32 bit SignExtlmm
cho giai on EX.
+) Bit trong m lnh th hin Rs, Rt, Rd 5 bit.
c) Stage EXMEM stage : Thanh ghi gia 2 giai on EX v MEM. Thanh ghi chuyn tip 72
bit d liu bao gm 32 bit d liu ra t khi ALU, 32 bit d liu ghi vo b nh, 5 bit
m lnh quay tr li thanh ghi v 3 bit lu tn hiu iu khin.
u vo : +) Tn hiu clock, reset.
+) Tn hiu iu khin c lu li EX_RegWrite, EX_MemtoReg,
EX_MemWrite.
+) D liu 32 bit ly ra t b tnh ton ALU v d liu 32 bit dng lu tr
vo b nh EX_WriteDataa

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+) Bit m lnh quay tr li tp thanh ghi 5 bit

u ra : +) Tn hiu iu khin cng vic ghi v c trong b nh.
+) D liu 32 bit lu tr vo b nh M_WriteData, d liu 32 bit t b ALU
M_ALUOut
+) Bit m lnh quay tr li tp thanh ghi 5 bit.
d) Stage MEMWB : Thanh ghi gia 2 giai on MEM v WB. Thanh ghi chuyn tip 71 bit
d liu bao gm 32 bit d liu c c ra t b nh, 32 bit d liu tnh ton t b ALU
quay tr li tp thanh ghi, 5 bit m lnh quay v thanh ghi v 2 bit lu tn hiu iu khin.
u vo : +) Tn hiu clock, reset.
+) Tn hiu iu khin M_RegWrite, M_MemtoReg.
+) Tn hiu d liu 32 bit c ra t b nh M_ReadData v d liu kt qu t b
ALU 32 bit M_ALU_Result.
+) Bit m lnh quay v thanh ghi 5 bit.
u ra : +) Tn hiu iu khin M_RegWrite, M_MemtoReg.
+) Tn hiu d liu 32 bit c ra t b nh M_ReadData v d liu kt qu t b
ALU 32 bit WB_ALU_Result.
+) Bit m lnh quay v thanh ghi.
e) Stage PC : Thanh ghi lu tr gi tr ca PC cho lnh tip theo. Thanh ghi PC l thanh ghi
32 bit lu gi tr ca tn hiu PC.
u vo : +) Tn hiu clock,reset
+) Tn hiu PC 32bit.
+) Tn hiu x l xung t StallF
u ra : +) Tn hiu ra PCF 32 bit a vo IMEM( Instruction Memory).
f) Khi Hazard : Dng x l xung t gp phi trong con Mips pipelined. Khi xy ra cc
hin tng xung t th s c tn hiu bo xung t v khi Hazard v t y s pht cc
tn hiu iu khin cc thanh ghi sao cho x l c cc xung t xy ra.
u vo : +) Cc bit m lnh ca cc thanh ghi [4:0] rsD, rtD, rsE, rtE.

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+) Bit m lnh tr v thanh ghi [4:0] WriteRegE, WriteRegM, WriteRegW.

+) Cc tn hiu iu khin BranchD, MemtoRegE, MemtoRegM, RegWriteM,
RegWriteW,

RegWriteM.

u ra : +) Cc tn hiu iu khin cc thanh ghi x l xung t StallF, StallD,

ForwardAD, ForwardBD, FlushE, [1:0] ForwardAE, [1:0] ForwardBE.

3.Gii quyt xung t

3.1. Cc loi xung t v phng php khc phc:
3.1.1. Xung t cu trc
a) t vn
Xung t cu trc xy ra khi 2 lnh cng c gng s dng 1 ngun ti cng 1 thi im.
V d nh ti 1 thi im c 2 lnh c gng ghi v c d liu t tp thanh ghi th ti thi
im xung t xy ra.
b) Hng gii quyt
C 2 phng php c th khc phc c dng xung t ny
- Thc hin ch
- Ghi chu k ln v tin hnh c chu k xung
Trong bi ny ta la chn phng php th 2 v mang li hiu nng cao hn

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3.1.2. Xung t d liu:

a) t vn
Xung t d liu xy ra khi ton hng ngun ca lnh cha kp thi c cp nht
nhng cu lnh pha trc

V d c on lnh sau:
I1:

add $s0, $s2, $s3

I2:

and $t0, $s0, $s1

I3:

or $t1, $s4, $s0

I4:

sub $t2, $s0, $s5

I1
I2
I3
I4

IF

ID

EX

MEM

WB

IF

ID

EX

MEM

WB

IF

ID

EX

MEM

WB

IF

ID

EX

MEM

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on m hp ng trn xy ra xung t khi $s0 c s dng lnh I2 nhng cha

c cp nht gi tr $s0 tnh c lnh I1. Bi $s0 ch c th c cp nht khu
WB ca I1 (Sau chu k th 5) nhng thc hin c lnh I2 theo s trn th cn kt
qu cp nht khu ID (Chu k th 3)
Tng t lnh I3 cng s gp xung t nh lnh I2 do kt qu $s0 cha c cp
nht. n lnh I4 mun WB ca I1 v ID ca I4 cng din ra, vy kp cp nht c
kt qu $s0 th cn phi c v ghi trong cng chu k
b) Hng gii quyt
Gii quyt xung t d liu bng phng php chuyn tip
Phng php chuyn tip l phng php chuyn tip kt qu t khu MEM hoc WB v
khu EX. thc hin phng php ny ta thm b dn knh vo trc b ALU. Tn
hiu iu khin la chn ngun ton hng cho b dn knh s c tnh ton bi khi
Hazard Detection. B dn knh s chuyn tip kt qu t khu (MEM hoc WB) nu
khu tha mn nhng iu kin sau:
-

Lnh khu thc hin hnh ng vit vo thanh ghi

Ton hng ch khu trng vi ton hng ngun khu EX

Nu c khu MEM v WB u c ton hng ch trng ton hng ngun EX

th u tin la chn chuyn tip t khu MEM v kt qu tnh ton khu MEM l
khu c cp nht gn nht

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3.1.3. Xung t c b nh d liu:

a) t vn
Xung t b nh d liu xy ra khi ton hng ch cha kp c cp nht d liu
t b nh ra thc hin cu lnh tip theo.
V d xt on lnh
I1: lw $s0, 40($0)
I2: and $t0, $s0, $s1
I3: or $t1, $s4, $s0
I4: sub $t2, $s0, $s5

I1
I2
I3
I4

IF

ID

EX

MEM

WB

IF

ID

EX

MEM

WB

IF

ID

EX

MEM

WB

IF

ID

EX

MEM

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Lnh lw khng th hon thnh vic c xong d liu cho n chu k 4, vy gi tr

ca $s0 cha th c cp nht.
b) Hng gii quyt
Vy c th gii quyt c xung t trong trng hp ny chng ta c th thc
hin phng php ch.

Bng cch i 1 chu k nh trn hnh v, d liu ca $s0 c th c

chuyn tip cp nht c gi tr ca $s0 kp np vo khu EX ca lnh I2. n
chu k th 5 th $s0 kp thi c cp nht.
thc hin c vic ch ta tin hnh thm tn hiu Stall vo cc thanh
ghi pipeline( PC v IF/ID). Ban u cc thanh ghi cp nht gi tr u ra mi khi
c sn ln clock, khi Stall xy ra cc thanh ghi pipeline gi nguyn gi tr.
Ngoi ra, ng thi vi tin hnh Stall IF/ID v PC, ta cn tin hnh xa thanh
ghi E trnh vic d liu s b chuyn tip mt cch lin tc lm sai lch kt qu
tnh ton.
3.1.4. Xung t iu khin
a) t vn
Xung t v iu khin xy ra khi thc hin cc lnh r nhnh. Khi 1 lnh
r nhnh xy ra, n s k bit lnh tip theo phi np l lnh no bi ti thi im
np lnh cha xc nh c kt qu ca lnh r nhnh .
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C 2 phng php chng xung t trong trng hp ny

o Lm chm r nhnh: Tin hnh ch cho n khi ht xung t
o D on r nhnh: Tin hnh np cc lnh k tip, n khi c kt qu ca
lnh r nhnh bt u xt xem r nhnh ng hay sai. Nu ng th tip tc
thc hin, nu sai thc hin xa ht kt qu tnh ton ca cc lnh sai.
b) Hng gii quyt
Trong ni dung bi ta tin hnh theo phng php d on r nhnh v
phng php ny cho hiu nng cao hn

Theo hnh v trn, nu d on r nhnh sai s phi xa i 3 lnh lm gim hiu

nng ca MIPS. tng hiu nng ca phng php ny, ta tin hnh d on r nhnh
sm, nu r nhnh c sai cng ch phi xa i 1 lnh, ci thin hiu nng cho MIPS.

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tin hnh r nhnh sm, ta thm 1 b so snh vo u ra ca tp thanh ghi. Vy

kt qu ca php r nhnh s c sau khu ID ch khng phi ch n khu MEM theo
phng php thng thng

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Thc hin phng php so snh sm dn n 1 xung t khc khi m ton hng
ngun lnh r nhnh li trng vi ton hng ch nhng lnh pha trc m cha kp
ghi vo thanh ghi. Nu kt qu ca ton hng ang khu MEM, ta tin hnh phng
php chuyn tip d liu t khu MEM v mi khi pht hin c xung t. Cc b dn
knh s tip tc c s dng trong trng hp ny . B dn knh s c iu khin
bng tn hiu ForwardAD v ForwardBD ly t khi Hazard Detection. Biu thc logic
ca chng c cho di y:
ForwardAD = (rsD != 0) AND (rsD == WriteRegM) AND RegWriteM
ForwardBD =(rtD != 0) AND (rtD == WriteRegM) AND RegWriteM

Nu gp phi trng hp pha trc r nhnh l cu lnh lw hoc kt qu ton

hng vn ang ch khu EX th khi ta phi ch 1 chu k kt qu tnh ton c
sn sng. Di y l biu thc logic
StallF = StallD = FlushE = lwstall OR branchstall
branchstall = BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR
BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD)

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Bi tp ln kin trc my tnh

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Sau 3 tin trnh gii quyt xung t ta thu c s cui c dng nh hnh v
di

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Bi tp ln kin trc my tnh

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III.Kt qu
1. S testbench

Hnh 3:S TESTBENCH ca b vi s l MIPS

2. Test code, kim th xung t

Np file memfile.dat cha m lnh dng hexa vo testbench v thc hin bi MIPS.
Kt qu thc hin chng trnh nh sau:
main: addi $2, $0, 5
addi $3, $0, 12
addi $7, $3, _9
or $4, $7, $2
and $5, $3, $4
add $5, $5, $4
beq $5, $7, end
slt $4, $3, $4
beq $4, $0, around
addi $5, $0, 0
around: slt $4, $7, $2
add $7, $4, $5
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sub $7, $7, $2

sw $7, 68($3)
lw $2, 80($0)
addi $2, $0, 1
end: sw $2, 84($0)

Ta tnh c s chu k/lnh:

CPI = 20/16

Ta vo register file xem kt qu thc hin.Kt qu hin th trn trnh m phng ng

vi kt qu mong i khi gii quyt c xung t.
Kt qu:
Gii quyt c bn dng xung t c bn:
-Xung t cu trc
-Xung t c b nh d liu
-Xung t d liu
-Xung t iu khin
Bng cch s dung 3 phng php gii quyt xung t l :
- Forwarding

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- Stall
- Branch Pridiction

3. Cc phng n gii quyt m rng:

Thut ton Tomasulo c a ra vo nm 1967 bi Robert Tomasulo lm vic
cho hang IBM. tng ca thut ton l s dng a ch Tag v bit trng thi nh du
cc thanh ghi, qua bit c thanh ghi ang bn hay ri s dng cho ph hp.
nh biu (Schedualing): S dng cc vector trng thi v bng t ch
(reservation table) dnh du cc trng thi ca cc tng pipeline.T xc nh c
s chu k cn a d liu vo trnh xung t.
Cc k thut pipelining mi:
Superpipelining: (Siu ng dn)
-c s dng trong dng VXL MIPS R4000.
-Tng s tng Pipeline t 5 ln 8 tng.
-Thi gian x l n lnh: T superpiplining = t + (n - 1) * t /8
Tc vi x l tng ng k so vi k thut Pipeline 5 tng, nhng cng v s
tng tng m kh nng xy ra xung t cng cao hn

Cc VXL hin i bt u t d.ng Pen IV s dng k thut ng dn

i (Dual Pipelining) tng tc ln gp nhiu ln so vi k thut
Pipeline thng thng.

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C th ly v d n gin khi ta tnh ton php tnh 14 * 47 + 5122, nu l k thut

pipeline thng thng vn phi mt 3 bc l tnh 5122, sau tnh 14 * 27, ri cui
cng cng 2 kt qu li. Nhng vi k thut ng dn i, 2 php tnh 5122 v 14 *
47 c thc hin cng 1 lc trn 2 pipeline khc nhau => gim c 1 cng on thc
hin tnh ton.

4. Hng pht trin:

-Thit k thm lnh cho b x l MIPS
-Thm tn hiu ready cho b nh c v ghi
-M rng gii quyt hazard.
-Thm b nhn v b chia cho MIPS
-Ti u ha din tch MIPS
-p dng cc k thut mi vo thit k MIPS

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C.Kt lun
Sau k hc va qua, nhm em hon thnh bi tp ln vi ti thit k MIPS
32 bit thc hin c nhng lnh c bn. ti thit k MIPS l ti mang tnh thc t
cao, gip chng em thm hiu v cu trc ca b vi s l MIPS, h tr cho vic hc mn
kin trc my tnh.
Qu trnh thc hin bi tp ln gip chng em tch ly thm c nhiu kinh
nghim thit k phn cng.Rn luyn t duy phn cng ,thm hiu r v b vi x l rt
thng dng trn th trng. c bit hn c, qu trnh ny cng gip chng em rn luyn
k nng lm vic nhm hiu qu.
Chng em xin gi li cm n chn thnh n c gio T Th Kim Hu gip
chng em hon thnh ti ny.

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