EE-313 LAB #4

ALTERA QUARTUS II DESIGN SOFTWARE

JK FLIP-FLOP USING VHDL

Name: _______________________________

1. Purpose:

Section:_______________

Date:__________

Review Altera Quartus II Design Software to simulate the JK Flip-Flop for a hardware
description language (VHDL). Review implementation of logic design in a fieldprogrammable logic array. Introduce designing a flip-flop in VHDL. Introduce
implementation of said flip-flop using a FPGA and its clock signal.

2. Equipment: Desktop with Altera Software

Altera PLD Board
Altera Quartus II Quick Reference
3. Procedure
a. Consider the two VHDL examples below provided by your text. Using VHDL design a JK
Flip-Flop that has asynchronous active low reset and set functions, and that is trigger by the
leading edge of a clock for the J and K synchronous operations.
b. Simulate your VHDL design three separate times and demonstrate to Maj Caldwell your
implementation on the Altera board:
i. Asynchronous input reset.
ii. Asynchronous input set.
iii. JK inputs count 00 to 11.

EE313

Lab #4

Spring 09
1

4. Deliverables
a.

Create an entry in your lab notebook as per the course guidelines, with a copy of your
VHDL code and its simulations.

b.

Your lab report will be written in the following format:

i.
ii.
iii.
iv.
v.

EE313

Lab #4

Purpose
Equipment
Procedure
Results
Conclusion

Spring 09
2