APPENDIX A

SAMPLE VHDL TEMPLATES

A.l

GENERAL VHDL CONSTRUCTS

A.1.1

Overall code structure

Listing A.l

Overall code structure

l i b r a r y ieee;
use ieee. std-logic-1164. a l l ;
use i e e e .numeric-std. a l l ;
5--

10

15

entity declaration
e n t i t y bin-counter i s
-- o p t i o n a l
generic declaration
g e n e r i c ( N : integer : = 8) ;
-- p o r t
declaration
port(
clk, reset: in std-logic;
-- c l o c k & r e s e t
load, en, syn-clr: in std-logic;
__ i n p u t c o n t r o l
d: i n std-logic-vector"-1
downto 0 ) ; -- i n p u t d a t a
max-tick; out std-logic;
-_ o u t p u t s t a t u s
q : o u t s t d - l o g i c - v e c t o r ( N - 1 downto 0 ) -- o u t p u t d a t a
);

end b i n - c o u n t e r ;
FPGA Protovping by VHDL Examples. By Pong P.Chu
Copyright @ 2008 John Wiley & Sons, Inc.

419

420

SAMPLE VHDL TEMPLATES

__ a r c h i t e c t u r e
20

25

body
a r c h i t e c t u r e demo-arch of bin-counter i s
-- c o n s t a n t
declaration
c o n s t a n t M A X : integer : = ( 2 * * N - 1 ) ;
_- i n t e r n a l s i g n a l d e c l a r a t i o n
s i g n a l r - r e g : u n s i g n e d ( N - 1 downto 0 ) ;
s i g n a l r-next : u n s i g n e d ( N - 1 downto 0 ) ;
begin

__
_-

component i n s t a n t i a t i o n

--

no i n s t a n t i a t i o n

__

30

in

t h i s code

--- memory e l e m e n t s
__
-- r e g i s t e r

35

p r o c e s s (clk,reset)
begin
i f (reset=l) then
r - r e g <= ( o t h e r s = > O ) ;
e l s i f ( c l k e v e n t and c l k = l ) t h e n
r - r e g <= r - n e x t ;
end i f ;
end p r o c e s s ;

40

-__ c o m b i n a t i o n a l

45

__

circuits

next-state logic
r-next <= ( o t h e r s = > O ) when s y n - c l r = l e l s e
unsigned(d)
when l o a d = 1 e l s e
r-reg + 1
when en = 1
else
r-reg ;
_- o u t p u t l o g i c
q <= s t d - l o g i c - v e c t o r ( r - r e g ) ;
m a x - t i c k <= 1 when r - r e g = M A X e l s e > O ;
end d e m o - a r c h ;
--

so

55

A.1.2

Component instantiation
Listing A.2 Component instantiation template

l i b r a r y ieee;
use ieee.std-logic-ll64.all;
e n t i t y counter-inst i s
port (
clk, reset: in
std-logic;
load16, en16, syn-clrl6 : i n std-logic;
d : i n s t d - l o g i c - v e c t o r ( 1 5 downto 0 ) ;
max-tick8, max-tickl6: out std-logic;

COMBINATIONALCIRCUITS

1;

10

421

q : out std-logic-vector (15 downto 0 )

end counter-inst;

I5

20

25

architecture st ructur e-ar ch of counter - inst is

begin
-- i n s t a n t i a t i o n o f 1 6 - b i t c o u n t e r , a l l p o r t s u s e d
counter-16-unit: entity w o r k . b i n - c o u n t e r ( d e m o - a r c h )
generic m a p ( N = > 16 )
port map(clk=>clk, reset=>reset ,
load=>loadl6, en=>enl6, syn-clr=>syn-clrl6,
d = > d , max_tick=>max_tick16, q=>q);
__ i n s t a n t i a t i o n o f f r e e - r u n n i n g 8 - b i t c o u n t e r
__ w i t h o n l y t h e m a x - t i c k s i g n a l
counter-8-unit : entity work. bin-counter
port map(clk=>clk, reset=>reset ,
l o a d = > O , e n = > l , syn-clr=>O,
d = > 0 0 0 0 0 0 0 0 , max_tick=>max_tick8, q=>open);
end structure-arch;

A.2

COMBINATIONAL CIRCUITS

A.2.1

Arithmetic operations
Listing A.3

Arithmetic operations

library ieee;
use ieee. std-logic-1164. a l l ;
use ieee.numeric-std. all ;
entity arith-demo is
port(
a , b: in std-logic-vector(7 downto 0 ) ;
diff , inc: out std-logic-vector ( 7 downto 0 )
);

end arith-demo ;
10

architecture arch of arith-demo is

signal a u , b u , diffu: unsigned(7
begin

downto 0);

_ _ ---------___------------------------------____________________-----------------------

15

---

convert inputs to unsigned/signed

and t h e n c o n v e r t t h e r e s u l t back

internally

__ _________---____________________________--____-----_______---------------------------

20

25

au <= unsigned(a1;
bu <= unsigned(b);
diffu <= au - bu when (au > bu) else
bu - au;
diff <= s t d - l o g i c - v e c t o r ( d i f f u ) ;
-- c o n v e r t

multiple

times

in a statement

422

SAMPLE VHDL TEMPLATES

inc <= std-logic-vector(unsigned(a)

end a r c h ;

A.2.2

+ 1);

Fixed-amount shift operations

Listing A.4 Fixed-amountshift operations

l i b r a r y ieee;
use ieee. std-logic-1164, a l l ;
e n t i t y fixed-shift-demo i s
port (
a: in std-logic-vector (7 downto 0 ) ;
shl, sh2, sh3, rot, swap: o u t
std-logic-vector (7 downto 0 )
);

end fixed-shift-demo;
10

15

20

a r c h i t e c t u r e arch of f ixed-shift-demo i s
begin
-_ s h i f t l e f t 3 p o s i t i o n s
shl <= a(4 downto 0 ) & " 0 0 0 " ;
-- s h i f t r i g h t 3 p o s i t i o n s ( l o g i c a l s h i f t )
sh2 <= " 0 0 0 " & a(7 downto 3);
-- s h i f t r i g h t 3 p o s i t i o n s and s h i f t i n g i n s i g n
__ ( a r i t h m e t i c s h i f t )
sh3 <= a(7) & a(7) & a(7)&
a(7 downto 3);
-- r o t a t e r i g h t 3 p o s i t i o n s
rot <= a(2 downto 0 ) & a(7 downto 3);
-- swap t w o n i b b l e s
swap <= a(3 downto 0 ) & a(7 downto 4);
end arch;

A.2.3

Routing with concurrent statements

Listing A S Routing with concurrent statements

l i b r a r y ieee;
u s e ieee. std-logic-1164. a l l ;
e n t i t y decoderl i s
port (
a: in std-logic-vector (1 downto 0) ;
en: in std-logic;
y l , y2: o u t std-logic-vector(3 downto 0 )
);

end decoderl ;
10

a r c h i t e c t u r e concurrent-arch of decoderl i s
s i g n a l s : std-logic-vector ( 2 downto 0 ) ;
begin

___________-_____________________________-_-_
_________________________________________-_

bit

COMBINATIONAL CIRCUITS

--

IS

conditional

signal

assignment

423

statement

--

y l <= "0000" when (en='O') e l s e

" 0 0 0 1 " when ( a = " 0 0 " ) e l s e
" 0 0 1 0 " when ( a = " 0 1 " ) e l s e
" 0 1 0 0 " when ( a = t ' l O 1 l ) e l s e
'1 1 0 0 0 1' ;
-_ a = "11

20

I'

-- s e 1 e c t e d

sig n a 1 assignment

sta t eme nt

--

25

<= en & a ;
with s s e l e c t
YZ <= l t O O O O t l when " 0 0 0 " I 11001" I t l O I O " I " O 1 1 " ,
000 1
when 'I 10 0 'I ,
" 0 0 1 0 1 1 when "101",
0 100
when It 1 10 I' ,
" 1 0 0 0 ' 1 when o t h e r s ;
-- s = "1 1 I

30

'I

end concurrent-arch;

A.2.4

Routing with if and case statements

Listing A.6 If and case statement templates

library ieee;
use ieee. std-logic-1164. a l l ;
e n t i t y decoder2 i s
port (
a : i n s t d - l o g i c - v e c t o r (1 downto 0 ) ;
e n : i n std-logic;
y l , y 2 : o u t s t d - l o g i c - v e c t o r (3 downto 0 )

1;

end d e c o d e r 2 ;
10

a r c h i t e c t u r e s e q - a r c h of d e c o d e r 2 i s
s i g n a l s : s t d - l o g i c - v e c t o r (2 downto 0 ) ;
begin

____________________---------_--------------____________________--------_----_---------

15

-- i f

statement

____________________------------------------__________________-__---------------------p r o c e s s ( e n , a)
begin
i f (en='O') t h e n
y l <= "0000";
e l s i f (a='lOOll) t h e n
y l <= "0001";
e I s i f ( a = "0 1 'I ) t h e n
yl <= "0010";
e l s i f (a=!!10 ) t h e n
yl <= "0100";
else
y l <= " 1 0 0 0 " ;

424

SAMPLE VHDL TEMPLATES

end i f ;
end p r o c e s s ;

30

__

__
__

case

statement

45

<= en L! a ;
process ( s )
begin
case s is
when l l O O O 1 t I l t O O 1 l t I l t O l o l l I "o111t
y 2 <= " 0 0 0 1 " ;
when " 1 0 0 " = >
y 2 <= " 0 0 0 1 " ;
when l t l ~
=> llp
y 2 <= " 0 0 1 0 " ;
when l l l l O t ' = >

jn

when o t h e r s =>
y2 <= " 1 0 0 0 " ;
end c a s e ;
end p r o c e s s ;

35

40

=>

y 2 <= " 0 1 0 0 " ;

end s e q - a r c h ;

A.2.5

Combinational circuit using process

Listing A.7 Combinational circuit using process

library ieee;
use ieee. std-logic-1164. a l l ;
e n t i t y comb-proc i s
port (
a , b : i n s t d - l o g i c - v e c t o r ( 1 downto 0 ) ;
d a t a - i n : s t d - l o g i c - v e c t o r ( 7 downto 0 ) ;
xa-out , xb-out : o u t s t d - l o g i c - v e c t o r ( 7 downto 0 ) ;
ya-out , yb-out : o u t s t d - l o g i c - v e c t o r ( 7 downto 0 )
);

10

end c o m b - p r o c

a r c h i t e c t u r e arch of comb-proc i s
begin

_--------------------------------------------

15

-- w i t h o u t

default

output

signal

-- m u s t i n c l u d e e l s e b r a n c h
__ o u t p u t s i g n a l m u s t b e a s s i g n e d
p r o c e s s (a,b,data-in)
20

assignment

__-------------------------------------------

begin
i f a > b then
xa-out <= d a t a - i n ;
xb-out <= ( o t h e r s = > ' O ' ) ;
e l s i f a < b then

in all

branches

MEMORY COMPONENTS

xa-out <=
xb-out <=
e l s e -- a=b
xa-out <=
xb-out <=

15

(others=>O);
data-in;

(others=>O);
(others=>O);

end i f ;
end p r o c e s s ;

30

--

__

with

default

output

signal

assignment

p r o c e s s ( a ,b , d a t a - i n )
begin
ya-out <= ( o t h e r s = > O ) ;
yb-out <= ( o t h e r s = > O ) ;
i f a > b then

3s

ya-out

10

<= d a t a - i n ;

e l s i f a < b then
yb-out <= d a t a - i n ;
end i f ;
end p r o c e s s ;
IS

end a r c h ;

MEMORY COMPONENTS

A.3
A.3.1

Register template
Listing A.8 Register template

library ieee;
use ieee.std-logic-ll64.all;
e n t i t y reg-template i s
port (
clk, reset: in std-logic;
e n : in std-logic;

qi-next , q z - n e x t , q3-next : i n
s t d - l o g i c - v e c t o r ( 7 downto 0 ) ;
ql-reg , q 2 _ r e g , q 3 - r e g : o u t
s t d - l o g i c - v e c t o r ( 7 downto 0 )

10

);

end r e g - t e m p l a t e ;

15

architecture
begin

is

__

__
__
20

a r c h of r e g - t e m p l a t e

register

without

reset

p r o c e s s (clk)
begin
i f ( c l k e v e n t and c l k = l ) t h e n
ql-reg

end i f ;

<= q l - n e x t ;

425

426

SAMPLE VHDL TEMPLATES

end p r o c e s s ;
25

__------------------------------------------__ r e g i s t e r w i t h a s y n c h r o n o u s r e s e t
__------------------------------------------p r o c e s s (clk , r e s e t )
begin
if (reset=l) then
q 2 - r e g < = ( o t h e r s = > 0 ) ;
e l s i f ( c l k e v e n t and c l k = l ) t h e n
q 2 - r e g <= q 2 - n e x t ;
end i f ;
end p r o c e s s ;

30

35

__------------------------------------------__ r e g i s t e r w i t h e n a b l e a n d a s y n c h r o n o u s r e s e t
...........................................
--______________________________________-----

40

45

50

p r o c e s s (clk, reset)
begin
i f (reset=l ) then
q3-reg < = ( o t h e r s = > O ) ;
e l s i f ( c l k e v e n t and c l k = l ) t h e n
if (en=l) then
q 3 - r e g <= q 3 - n e x t ;
end i f ;
end i f ;
end p r o c e s s ;
end a r c h ;

A.3.2

Register file
Listing A.9

l i b r a r y ieee;
use i e e e . s t d - l o g i c - 1 1 6 4 .
use i e e e . n u m e r i c - s t d . a l l
e n t i t y reg-file i s
generic(
B : i n t e g e r : = 8 ; -W : i n t e g e r : = 2 --

Register file

all ;
;

n u m b e r of b i t s
n u m b e r of a d d r e s s

bits

);
10

15

port (
clk, reset: in std-logic;
wr-en: i n std-logic;
w-addr , r - a d d r : i n s t d - l o g i c - v e c t o r (W-1 downto 0 ) ;
w - d a t a : i n s t d - l o g i c - v e c t o r ( B - 1 downto 0) ;
r - d a t a : o u t s t d - l o g i c - v e c t o r ( B - 1 downto 0 )
;

end r e g - f i l e ;
a r c h i t e c t u r e a r c h of r e g - f i l e i s
t y p e r e g - f i l e - t y p e i s a r r a y (2**W-1 downto 0 ) of

REGULAR SEQUENTIALCIRCUITS

427

std-logic-vector ( B - 1 downto 0 ) ;
s i g n a l array-reg : reg-f ile-type ;
begin
p r o c e s s (clk,reset)
begin
25
i f (reset=l) t h e n
array-reg <= ( o t h e r s = > ( o t h e r s = > O ) ) ;
e l s i f (clkevent and clk=l) t h e n
i f wr-en=l t h e n
array-reg(to-integer(unsigned(w-addr))) <= w-data;
30
end i f ;
end i f ;
end p r o c e s s ;
__ r e a d p o r t
r-data <= array-reg(to-integer(unsigned(r-addr)));
35end arch;

20

A.4

REGULAR SEQUENTIAL CIRCUITS

Listing A.10

10

Sequential circuit template

l i b r a r y ieee;
u s e ieee. std-logic-1164. a l l ;
u s e ieee. numeric-std. a l l ;
e n t i t y bin-counter i s
g e n e r i c ( N : integer : = 8 ) ;
port (
c l k , reset: i n std-logic;
load, e n , syn-clr: i n std-logic;
d: i n std-logic-vector (N-1 downto 0 ) ;
max-tick: o u t std-logic;
q: o u t std-logic-vector (N-1 downto 0 )
);

end bin-counter;
IS

20

a r c h i t e c t u r e demo-arch of bin-counter i s
c o n s t a n t M A X : integer : = (2**N-1) ;
s i g n a l r-reg: unsigned(N-1 downto 0 ) ;
s i g n a l r-next : unsigned (N-1 downto 0 ) ;
begin

__

__

__

25

30

register

p r o c e s s (clk,reset)
begin
i f (reset=l) t h e n
r-reg <= ( o t h e r s = > O ) ;
e l s i f (clkevent a n d clk=l) t h e n
r-reg < = r-next;
end i f ;

428

SAMPLE VHDL TEMPLATES

end p r o c e s s ;
__ n e x t - s t a t e

r-next

35

--

40

logic

<= ( o t h e r s = > O ) when s y n - c l r = l e l s e

unsigned(d)
when l o a d = l e l s e
r-reg + 1
when e n = i > e l s e
r-reg ;

output

logic

q <= s t d - l o g i c - v e c t o r ( r - r e g ) ;
m a x - t i c k <= 1 when r-reg=MAX
end d e m o - a r c h ;

A.5

else

0;

FSM
Listing A . l l FSM template
c o d e f o r t h e FSM i n F i g u r e A . l
library i e e e ;
use i e e e . s t d - l o g i c - 1 1 6 4 . a l l ;
e n t i t y fsm-eg i s

--

port(
c l k , r e s e t : in s t d - l o g i c ;
a , b : in s t d - l o g i c ;
y o , y l : out s t d - l o g i c

1;

ID

end f sm-eg ;

15

a r c h i t e c t u r e t w o - s e g - a r c h of f s m - e g i s
type e g - s t a t e - t y p e i s (SO, sl, s 2 ) ;
signal s t a t e - r e g , state-next : eg-state-type;
begin

__
20

25

register

p r o c e s s ( c l k ,r e s e t
begin
i f ( r e s e t = l ) then
s t a t e - r e g <= S O ;
e l s i f ( c l k e v e n t and c l k = l ) t h e n
s t a t e - r e g <= s t a t e - n e x t ;
end i f ;
end p r o c e s s ;

__
__

__

30

state

next-state /output

logic

process ( s t a t e - r e g , a , b )
begin
s t a t e - n e x t <= s t a t e - r e g , ;

-- d e f a u l t

b a c k t o same s t a t e

FSM

429

lb

, ..........................................

y l c= 1

6+
I-

...................

, ...................

ylc-I

.....,.....

..........

(a) State diagram

(b) ASM chart

Figure A.l

State diagram and ASM chart of an FSM template.

I.........

430

SAMPLE VHDL TEMPLATES

y o <= 0 ;
-- d e f a u l t 0
y l <= 0 ;
-- d e f a u l t 0
case s t a t e - r e g is
when S O = >
if a = l J then
if b = l then
s t a t e - n e x t <= s 2 ;
yo <= 1 ;
else
s t a t e - n e x t <= s l ;
end i f ;
-- no e l s e b r a n c h , u s e d e f a u l t
end i f ;
when sl = >
y 1 <= 1 ;
if ( a = l ) then
s t a t e - n e x t <= S O ;
-- n o e l s e b r a n c h , u s e d e f a u l t
end i f ;
when s 2 =>
s t a t e - n e x t <= S O ;
end c a s e ;
end p r o c e s s ;

35

40

45

50

55

end t w o - s e g - a r c h ;

A.6

FSMD
Listing A.12

FSMD template

c o d e f o r t h e FSMD s h o w n i n F i g u r e A . 2
library ieee;
use i e e e . s t d - l o g i c - 1 1 6 4 . a l l
use i e e e . n u m e r i c - s t d . a l l ;
entity f i b is
port (
c l k , r e s e t : in s t d - ogic ;
s t a r t : in s t d - l o g i c
i : i n s t d - l o g i c - v e c t o r ( 4 downto 0 ) ;
r e a d y , d o n e - t i c k : out s t d - l o g i c ;
f : o u t s t d - l o g i c - v e c t o r ( 1 9 downto 0 )

--

10

1;

end f i b ;
15

20

a r c h i t e c t u r e a r c h of f i b i s
type s t a t e - t y p e is ( i d l e , o p , d o n e ) ;
signal state-reg , state-next : state-type ;
signal to-reg , to-next , t l - r e g , t l - n e x t :
u n s i g n e d ( 1 9 downto 0 ) ;
s i g n a l n - r e g , n - n e x t : u n s i g n e d ( 4 downto 0 ) ;
begin
-------------------------===========-----====

FSMD

(7)
start=l
T

2
t l t

........................................

................................................................

Figure A.2

ASMD chart of an FSMD template.

431

432

SAMPLE VHDL TEMPLATES

-_

state

and d a t a

registers

-___-______-_____-__------------------------____________________-__-__-__--__----_----25

30

process ( c l k , r e s e t )
begin
i f r e s e t = l then

s t a t e - r e g <= i d l e ;
t o - r e g <= ( o t h e r s = > O ) ;
t i - r e g <= ( o t h e r s = > O ) ;
n - r e g <= ( o t h e r s = > O ) ;
e I s i f ( c l k e v e n t and c l k = 1 ) t h e n
s t a t e - r e g <= s t a t e - n e x t ;
t o - r e g <= t o - n e x t ;
t l - r e g <= t l - n e x t ;
n - r e g <= n - n e x t ;
)

15

end i f ;
end p r o c e s s ;

________________________________________----_______________________--______-__---__---40

-- n e x t - s t a t e
l o g i c and d a t a p a t h f u n c t i o n a l u n i t s
.............................................
process ( s t a t e - r e g , n - r e g , to-reg , t l - r e g , start , i ,n-next)

begin

45

50

55

60

ready <=O;
d o n e - t i c k <= 0 ;
s t a t e - n e x t <= s t a t e - r e g ; -- d e f a u l t b a c k t o s a m e s t a t e
t o - n e x t <= t o - r e g ;
-- d e f a u l t k e e p p r e v i o u s v a l u e
t l - n e x t <= t l - r e g ;
__ d e f a u l t k e e p p r e v i o u s v a l u e
n - n e x t <= n - r e g ;
__ d e f a u l t k e e p p r e v i o u s v a l u e
case s t a t e - r e g i s
when i d l e =>
r e a d y <= 1 ) ;
i f s t a r t = l then
t o - n e x t <= ( o t h e r s = > O ) ;
t i - n e x t <= ( 0 = > 1 , o t h e r s = > O ) ;
n - n e x t <= u n s i g n e d ( i );
s t a t e - n e x t <= o p ;

end i f ;
when o p = >
i f n - r e g = O then
t i - n e x t <= ( o t h e r s = > O ) ;
state-next

<= d o n e ;

e l s i f n - r e g = l then
s t a t e - n e x t <= d o n e ;
else

65

t l - n e x t <= t l - r e g + t o - r e g ;
t o - n e x t <= t l - r e g ;
n - n e x t <= n - r e g - 1 ;

70

end i f ;
when d o n e =>

d o n e - t i c k <= 1 ;
s t a t e - n e x t <= i d l e ;

end c a s e ;
end p r o c e s s ;
75

-- o u t p u t

53 BOARD CONSTRAINT FILE (S3 .UCF)

f <= s t d - l o g i c - v e c t o r ( t l - r e g ) ;
end a r c h ;

A.7 S3 BOARD CONSTRAINT FILE (S3.UCF)

#
#
#

Pin assignment f o r Xilinx

Spartan-3 S t a r t e r board

#
#
# clock
#:

and r e s e t

NET " c l k "

NET " r e s e t "

LOC = " T 9 " ;

LOC = " L 1 4 " ;

# buttons

& switches

# 4 push

buttons
NET " b t n < O > "
LOC
NET " b t n < l > "
LOC
NET " b t n < 2 > "
LOC
#NET " b t n < 3 > " LOC
# 8
NET
NET
NET
NET
NET
NET
NET
NET

s l i d e switches
"sw<O>"
LOC =
"sw<l>"
LOC =
" s w < 2 > " LOC =
"sw<3>"
LOC =
" s w < 4 > " LOC =
"sw<5>"
LOC =
" s w < 6 > " LOC =
" s w < 7 > " LOC =

= "M13";
= "M14";
= "L13";
= "L14";

#btn<3> also used a s r e s e t

"F12";
"G12";
"H14";
"H13";
"514";
"513";
"K14";
"K13";

# RS232
#

NET " r x "

NET " t x "

LOC = " T 1 3 "

LOC = " R 1 3 "

I D R I V E = 8 I SLEW=SLOW;
I D R I V E = 8 1 SLEW=SLOW;

#
# 4-digit
#

time-multiplexed

d i g i t enable
NET " a n < O > " LOC
NET " a n < l > " LOC
NET " a n < 2 > " LOC
NET " a n < 3 > " LOC
#

# 7-segment

= "D14";
= "G14";

= "F14";
= "E13":

l e d segments

7-segment

LED d i s p l a y

433

434

SAMPLE VHDL TEMPLATES

sseg<7>
sseg<6>
sseg<5>

NET
NET
NET
NET
NET
NET
NET
NET

sseg<4>
sseg < 3 >
sseg<2>
sseg<l>

s s e g <O >

#
#
#
"N15"; #
"P15"; #
"R16"; #
"F13"; #
"N16"; #

= "P16";

LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC

= "E14";
= "G13";
=
=

=
=
=

decimal
segment
segment
segment
segment
segment
segment
segment

point
a
b
c
d
e

f
g

# 8 d i s c r e t e LEDs
#

NET
NET
NET
NET
NET
NET
NET
NET

"led<O>"
"led<l>"
"led<2>"
"led<3>"
"led<4>"
"led<5>"
"led<6>"
"led<7>"

#
# VGA
#

NET
NET
NET
NET
NET

LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC

= "K12";
= "P14";

= "L12";
= "N14";
=
=
=
=

outputs

"rgb<2>"
"rgb<l>"
"rgb<O>"
"vsync"
"hsync"

LOC
LOC
LOC
LOC
LOC

I
I
"Rl1" I
"T10" I
"R9"
I

= "R12"
= "T12"
=
=
=

#
# PS2 p o r t
#

NET " p s 2 c " L O C = " M 1 6 "

NET " p s 2 d " L O C = " M 1 5 "
#
# two
#:

"P13";
"N12";
"P12";
"P11";

I
I
I
1
I

SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;

I D R I V E = 8 I SLEW=SLOW;
I D R I V E = 8 1 SLEW=SLOW;

SRAM c h i p s

s h a r e d 1 8 - b i t memory
NET " a d < 1 7 > " L O C = " L 3 "
NET " a d < 1 6 > "
LOC="K5"
NET " a d < 1 5 > " L O C = " K 3 "
NET " a d < 1 4 > " LOC=" 5 3 "
NET " a d < 1 3 > " L O C = I ' J 4 "
NET " a d < 1 2 > " L O C = " H 4 "
NET " a d < l l > "
LOC="H3"
NET " a d < l O > "
LOC="G5"
NET " a d < 9 > "
LOC="E4"
NET " a d < 8 > "
LOC="E3"
NET " a d < 7 > "
LOC="F4"
NET " a d < 6 > "
LOC="F3"
NET " a d < 5 > "
LOC="G4"
#

DRIVE=8
DRIVE=8
DRIVE=8
DRIVE=8
DRIVE=8

address
I IOSTANDARD
1 IOSTANDARD

I
I
1
1
I

1
I
I
I
I
I

IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD

= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33

= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33

I
I
1
I
I
1
I

I
I
= LVCMOS33 I
= LVCMOS33 I
= LVCMOS33

= LVCMOS33

SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;

53 BOARD CONSTRAINT FILE (S3.UCF)

IW

NET
NET
NET
NET
NET

"ad<4>"
"ad<3>"
"ad<2>"
"ad<l>"
"ad<O>"

LOC="L4"
LOC="M3"
LOC="M4"
LOC="N3"
LOC="L5"

I
I
I
I
I

IOSTANDARD = LVCMOS33 I
IOSTANDARD = LVCMOS33 I
IOSTANDARD = LVCMOS33 I
IOSTANDARD = LVCMOS33 I
IOSTANDARD = LVCMOS33 I

shared oe, we
NET "oe-n"
LOC="K4" I IOSTANDARD
NET "we-n"
LOC="G3" I IOSTANDARD

SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;

=
=

LVCMOS33 I SLEW=FAST;
LVCMOS33 I SLEW=FAST;

# sram chip 1 data, ce, ub, lb

NET "dio_a<l5>" LOC="Rl" I IOSTANDARD=LVCMOS33
NET "dio_a<l4>" LOC="Pl" I IOSTANDARD=LVCMOS33
NET "dio_a<l3>" LOC="L2" I IOSTANDARD=LVCMOS33
NET "dio-a<12>" LOC="52" I IOSTANDARD=LVCMOS33
NET "dio-a<ll>" LOC="Hl" I IOSTANDARD=LVCMOS33
NET "dio-a<lO>" LOC="F2" I IOSTANDARD=LVCMOS33
NET "dio-a<9>" LOC="P8" I IOSTANDARD=LVCMOS33
NET "dio-a<8>" LOC="D3" 1 IOSTANDARD=LVCMOS33
NET "dio-a<7>" LOC="Bl" I IOSTANDARD=LVCMOS33
NET "dio-a<6>" LOC="Cl" I IOSTANDARD=LVCMOS33
NET "dio-a<5>" LOC="C2" I IOSTANDARD=LVCMOS33
NET "dio-a<4>" LOC="R5" I IOSTANDARD=LVCMOS33
NET d i o - a < 3> " L0C = " T5 " 1 I0STANDARD = LV CM 0S33
NET "dio-a<2>" LOC="RG" I IOSTANDARD=LVCMOS33
NET "dio-a<l>" LOC="T8" I IOSTANDARD=LVCMOS33
NET "dio-a<O>" LOC="N7" I IOSTANDARD=LVCMOS33
NET 'I ce-a-n"
LOC="P7" I IOSTANDARD=LVCMOS33
NET "ub-a-n"
LOC="T4" I IOSTANDARD=LVCMOS33
NET "lb-a-n"
LOC="P6" I IOSTANDARD=LVCMOS33
I'

# sram chip 2 data, ce, ub, lb

NET "dio_b<l5>" LOC="Nl" I IOSTANDARD=LVCMOS33
NET "dio_b<l4>" LOC="Ml" I IOSTANDARD=LVCMOS33
NET "dio_b<l3>" LOC="K2" I IOSTANDARD=LVCMOS33
NET "dio-b <12>" LOC="C3" I IOSTANDARD=LVCMOS33
NET "dio-b<ll>" LOC="F5" 1 IOSTANDARD=LVCMOS33
NET "dio-b< l o > " LOC="Gl" I IOSTANDARD=LVCMOS33
NET "dio-b<9>" LOC="E2" I IOSTANDARD=LVCMOS33
NET "dio-b<8>" LOC="D2" I IOSTANDARD=LVCMOS33
NET "dio-b<7>" LOC="Dl I IOSTANDARD=LVCMOS33
NET "dio-b<6>" LOC="El I IOSTANDARD=LVCMOS33
NET "dio-b< 5 > " LOC="G2" I IOSTANDARD=LVCMOS33
NET "dio-b<4>" LOC="J1 I' I IOSTANDARD=LVCMOS33
NET "dio-b< 3 > " LOC="Kl" I IOSTANDARD=LVCMOS33
NET "dio-b<2>" LOC="M2" 1 IOSTANDARD=LVCMOS33
NET "dio-b<1>" LOC="N2" I IOSTANDARD=LVCMOS33
NET "dio-b< O > " LOC="P2" I IOSTANDARD=LVCMOS33
NET ce-b-n"
LOC="N5" I IOSTANDARD=LVCMOS33
NET "ub-b-n"
LOC="R4" I IOSTANDARD=LVCMOS33
NET "lb-b-n"
LOC="P5" I IOSTANDARD=LVCMOS33
'I

'I

I
I
I
I

SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST ;
SLEW=FAST;

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

SLEW=FAST;
SLEW=FAST;
SLEW=FAST ;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;
SLEW=FAST;

I
I
I
I
1
I
1
I
I
I

I
I
I

435

436
#
#
#

SAMPLE VHDL TEMPLATES

Timing constraint of S3 50-MHz onboard oscillator

name of the clock signal is clk

NET " c l k " TNM-NET = " c l k " ;

TIMESPEC 1'TS-clk9t= PERIOD " c l k " 40 ns HIGH 50 %;