IDDQ Testing Outline O Introduction O Inductive Fault Analysis O Faults That Can Be Detected O Circuit Constrains O Design and Test Rules O ATPG for IDDQ Testing O Current Monitoring Methods O Built-in Current Sensors O QTAG Standard OQ Deep Sub-micron Issues © Some Specific Examples Conclusions 7 1000 testng-t IDDQ Testing IDD --- Current flow through VDD Q--- Quiescent state IDDQ Testing --- Detecting faults by monitoring IDDQ 4 vop >) cmos circuit Normal IDDQ: ~10Amp. ‘Abnormal IDDQ: >10°Amp. 1000 testing? 7 Advantages of IDDQ Testing Fault effect is easy to detect Many realistic faults are detectable ATPG is relatively simple Test length is shorter Built-in current sensing is possible 7 1000 testing s Inductive Fault Analysis (IFA) « A systematic method to generate realistic fault lists * Taking into account —Circuit fabrication technology —Defect statistics —Physical layout 1000 testing 4 7Framwork of Inductive Fault Analysis aay Teepe) Primitive Foul =] JE staes anion Detect /$— 1000 testing 5 7 Calculation of Defect Likelihood Defect spot cy We Aa xtra conductance Missing insulator Whether a fault presents depends on 1, Size of spot (defect statistics) 2. Distance of two conductors (layout) 3. Fabrication process 7 1000 testing 6 ys 2D D> (a) Defect-free poly path \ ae {c) insignificant missing poly Defects in a Poly Path Results of IFA Combin,: Both bridge and break present T-SON(SOP): Transistor struck-on (stuck-open) ) New T: New transistor created 1000 testing 8New Transistors Faults That Can Be Detected Jt > L => (A (A) Caused by oxtra poly {B) Missing thinox / 1000 testing s difusion L~ + Bridge & stuck-on faults + Break faults. — Line break — Gate break — Drain break — Source break + Transistor stuck-open faults + Other faults 7 1000 testng.10 Bridging & Stuck-on Faults Line Break Faults > py 5V o 4 Oort? | | > Induce large —- ~ current logic 0: 0V Lc - _t-—— logic 4:5V = 25v al 1 4 3 Oor1? = = a4 Ly A floating node may drift to 1.5V~3.5V ae and hence may turn on both PMOS and NMOS transistors —> Logic monitoring is inadequate ! / 7 1000 testing 11 1000 testing 12Circuit Model to Analyze Break B 7 10a testng.13 ie Gate Break Faults (Maly ICCAD 1988) B 41. Off for Vos Control direction or loop can be defined 1000 testing 24A Minimum Set of Design & Test Rule for IDDQ Testing (Lee TCAD'92) 1. Gate and drain (or source) nodes of a transistor are not in the same TG. ‘A2. No conducting path exists from VDD to GND during steady state. A3. Each output of a TG is connected to VDD or GND during steady state. ‘A4. No control loops among TGs exist. AS. The bulk (or well) of an n-(p-)type transistor is connected to GND (VDD). AG. During testing, each Plis controlled by a monitored power source. 1000 testing 25 Results of Design & Test Rules Theorem 1: All irredundant single BFs in a circuit satisfying ‘A1-A6 can be detected using IDDQ testing. Theorem 2: For a circuit satisfying A1-A6, a test detecting a gle BF falso detects all multiple BFs that contain f. ‘Theorem 3: If any one of A1-A6 is removed, then circuits exist for which IDDQ testing cannot give correct test results. Strategies for dealing with circuits not satisfying each rule are required to ensure IDDQ detectabi Fault Simulation 4. Fault models --- Bridging, break, stuck-open, stuck-at ? 2. Fault list generation --- need inductive fault analysis . Fault coverage ? }. Easy for bridging and stuck-on faults . Difficult for break and stuck-open faults aan . Stuck-at faults may or may not be modeled as short to VDD or GND 7 1000 testing 27 Fault simulation for BFs If A1-A6 are satisfied, then fault simulation is quite simple 1. Perform a good circuit simulation for the given test pattern. 2. Any BF between a node with logic 1 and a node with logic 0 is detected. © No simulation on faulty circuit is needed. => No fault list enumeration is needed. 10a testing 28Test Generation 1. Conventional test generation for stuck-at faults can be modified to detect BFs. 2. No fault propagation. 3. Must make sure the faults result in a conducting path between VDD and GND. ——Switch level test generation may be necessary. . Break and stuck-open faults are difficult to detect. / 1000 testing 29 Test generator for BFs Again, assume A1-A6 are satisfied 1. For the BF (a, b) to be detected, add an XOR gate with its inputs connected to a and b. 2. The test generator work is simply to set the ‘output of the XOR gate to be 1. [> No Fault propagation. Test Length Using IDDQ Testing for BFs| Prob. (a BF is detected by a random vector) =12 [> rob. (a BF is not detected by n random vectors) = oe Ifn=20, 1 Prob. (a fault is not detected) = 705" In general, the length of a complete test set for BFs is quite small. Usually 30 is enough for a combinational UY 7 1000 testing 31 ‘omparison Between IDDQ and Logic Testin TDDA Testing Fault Coverage(%) Logie Testing lcxeut 5. vec. |12 ve. [16 woe. ,20 vee Jime(s Javec. FC _frinayn) lease 9.69| 99.09 = | aod sol 70] s1.4 lease 98,93) 99.37 2.15] 184 20.5 Je1908 9082 99.39 +139| 2a. 386 96.7| 98.00 2a e526 97.04| 98.15 ‘ 564 jesse 95.641 97.25Test generation results for IDDQ test (Source:1996 IDDQ Testing Workshop) Total Not Covered Circuit [Targets [rests [Give-up _[Untestabie [rime(s) [wissing Rate(%) leas 432 13] 0.24] 42] lease 54 ol _os7| d leaeo 34] 4 of 0.39] d leras6 | 14a2] a9 of 5a 04] lergos | t604{ 1 2 3.0| oa leze70 | 22858| 17459] 412| leasao_| 3314] 50] 44.32 17| fests | 4955] as. oa lerss2_| _69656| 20] 14.271 0 laverage | 2497| 1] 837] ol 1000 testing 33 Current monitoring Techniques ATE ATE RY [current Supply] Mane DUT DUT cUuT External Test Built-In monitoring Fixture Current Sensor 1000 testing 34 External Devices (Hawkins 86, 89) ‘TEST POWER SUPPLY [HH ssrnose) Problems: Joao 1. Current resolution is limitted. 2. Test equipment must be modified. 3. Current cannot be measured at the full speed of the tester. 4. Cannot partition circuit. 1000 testing 35 Built-in Current Sensors (BICSs) yoo Avon Test'™™|_BICS [=P Pass inputs > outputs Fail oR Inputs: Outputs — rest mm] Bios km Pass/Fail Sometimes called ISSQ testing 7 1000 testing 36BICS Based on Logic Threshold Favalli (JSSC-90) BICS Based on Bipolar Transistor and Differential Amplifier (Maly, ICCAD '88) yop yoo yoo yoo cas t Far] Par Pa lea veattin) pli a _ ee “Tete te SE Miowr] Mga Fae tout = 1 if no fault th a es ee Zo ittault exists gee When large IDDQ exists, V>Vr and Fail ty 4 ~ —H ae {Ea} toner 4 oa | + ¥ {| The switching circuit may switch off a mu faulty module to prevent large power |. ‘uymoaul 1000 testng:37 7 1000 testing 38 Improvement on Favalli's design Improvement on Favalli's Design vod yoo e yop yoo yoo Pu] [Pu Pu up | fPLup up inputs - Putt] |, [Pur Put down) “down town] — a] 4 Tout Merge all MT and MTD Uciwro respectively 7 1000 testing 39BICS Based on Integrators Miura & Kinoshita (ITC-92) fe ‘eno V-1 Translator Level Translator Integral Circuitry. Feuteeceanaeaecamuitesugn sven ees) 1000 testng-41 Verhelst's BICS Patent keMP}|—> o2 1 Ves Virtual Short > Voo' ~ Voo Current Mirror => Ipp~ lo 7 1000 testng.42 BICS Based on Dual Power Supply & Operational Amplifier Virtual Short Voo=3v Fault indication Virtual short > VDD-Vin Infinite input impedance of OP ‘0 and IRS=IDD 7 1000 testing 43 BICS Based on Current Conveyor Virtual Short lz zy Von=sv| Current Conveyor | J ]¥ Threshold vp pat FallPass cut aE oa Virtual short DYDD ~ Voo' Current Conveying ly ~ Ix 7 1000 testing aAdvantages of Built-In Current Sensors (BICS) + Higher test rate compared to external devices + Easier to partition circuits + Easier to control current resolution + Suitable for mixed-mode circuits + Built-In self test capability achievable + Lower test equipment cost + On-Line testing possible 7 1000 testing 45 Disadvantages of BICS + Impact on circuit performance + Reliability of itself + Area overhead + Power consumption 1000 testng.46 QTAG Standard + Motivation : — ATE based IDDQ facilities are not flexible or effective. — Circuit designers are reluctant to use BICS. + Goal : To provide a de-facto standard for IDDQ monitors on test fixture for production test. 1000 testing a7 Partnership of QTAG + Semicoductor test department: Users, must drive the standard *ATE Vendors: must supply the software to operate the monitors from ATE “Test Fixture Vendors: must provide a small area close to CUT on all test fixtures to mount the monitors. +Monitor Developers: must supply the desired monitors. 1000 testing 48QTAG lIppq Test Configuration (Baker, ITC '94) Development of the Standard + Kick-off meeting at ITC’95, define 4 development phases Power Supply Unit = phase 1: Monitor standard definition 3 $ phase 2: Monitor design ql phase 3: Monitor evaluation 3 phase 4: Working toward a standard + Results are reported in 4 papers presented in ITC’94 wu vi i" +1994 OCIMU (off-chip measurement unit) was = |pypass| developed by Alcatel Do love put + in 1995 ITC, the Monitor Description Format(MDF) 1 MoRiToR language is presented +1996 OCIMU => POCIMU (threshold programmable) -— Vss D 1000 testng.49 1000 testing 50 : An example of Interface to Digital ATE QTAG Monitor on a Probe Card Power Supply Unit Stag enna Power x —Frenae - x Power Ring anv Wvooannes fe doves maar J 27 lur| foo lara Sa 7 ~ Probe Nails v| [meas 7 1000 testing 51 1000 testing 52Circuit Diagram of IDUNA-1 monitor Top-level Block Diagram of IDUNA II IREF DL TRIGGER En vpp_MoN—+-s s 6 wor aig EL... internal voo_psu—2 [ ovrass—t+brneed [Front[*feuck] — ne n veer —}+ ‘ a 4 v woo] 100m —vss tout Device under txt 1poatestng 83 Front-end Circuit Diagram of IDUNA II Back-end Circuit Diagram voo_Psu, of IDUNA-2 HE a et TPs _"t vadg2 noc]Companies with Members in QTAG ‘AMD Ericson NEC AT&T GEC Philips ATTEST HP Sandia Lab. BNR Intel Schlumberger Bosch mT Sequent Brooktree LRM ‘Siemens Chips&Technologies LTX Sun Cadence MCT Synopsys Credence Megatest Teradyne CrossCheck Motorola TI Digital National Semicon. Vertex 7 1000 testng 57 Deep Sub-micron IDDQ Test Issues Components of Defect-free IDDQ + Reverse biased p-n junction leakage current ~ State dependent reverse based p-n junction. ©.9, drain-substrate leakage + State independent reverse biased wells + Sub-threshold leakage When Ves < VT, os 0 Sub-Threshold Leakage Current + When Vos < Vr, Ios is an exponential function of (Ves-Vr) Define s = 28 =!) * Define 5 = — the inverse rate of decrease 402814) of bs in volts per decade => Typically $=80 ""tecade 7 1000 testing 59 + In deep-submicron region, © low voltage power supply © low threshold voltage © increased subthreshold current Example: Vr 0.6 v0.3 (600 ~300)/ 70 > Ips increase by 10 1057 timesDeep Sub-micron IDDQ test Options sTechnology solution Ex: Silicon On Insulator (SO!) <> sharper sub-threshold “Technology soluti current slope gy solution Ex: - Hierarchical power-line distribution with multiple threshold transistors ~ Switched-Source impedcance (can reduce IDS to 0.3% of its original value, very useful in ‘Technology solution Giga-bit DRAM) Ex: Separate Source and substrate connection 1000 testing 61 Applications and Examples + Low power design + Power management + Memory coupling test + CPU testing + Boundary scan + IDDQ Testing 7 1000 testing 62 Applications of IDDQ and IDDT Testings \Normal \Large |No IDDT ImDDQ___|IDDT. small IK [Bad design [No action IDDQ |(Redesign (Tum off for lforlow power lpower) __ management) [Faulty [Faulty 7 1000 testing 63 IDDT-Testable SRAM Structure wo] 5 > Mellie bl Se [1 [2] bo] — ao 7 1000 testing 64Some Experimental Results (for a Dynamic Combinational logic) Detect Coverages(%) hoor}}ooa+1007 Franson Tos lopen drainsource 969| +00 single Noating gato +09 +00 double toating gato +09 109 Short doects inthe procharge chips +09 109 1000 testing 65 Conclusions + Extremely important to achieve high-quality test. * BICS can be either extremely profitable or nothing. + ATPG for faults other than BFs needs further research. + Deep sub-micron issues have to be addressed. 1000 testing 66