2

:
,

/ .

Master/Slave

, .
,
(master).

.
,
(slave).
.


:
,

.

 ABUS
(ABUSn..0)

.

 DBUS
(DBUSm..0)


.


.

.
?

 CBUS


( ).




.
:

RDBUS
WRBUS
M/IO ()
FCBUS ( )
...
8


(Dedicated)

-
-


:
,

/ .

10


Master

Slave

DMA

DMA
...

/
/

/



/


11


:
,

,

12




, :

.

13




.
:

ABUS
DBUS
RDBUS
WRBUS
FCBUS
inta
...

14

 -
ABUS
DBUS

!

RDBUS

highZ

FCBUS
0 1

0.
ABUS RDBUS
.
DBUS FCBUS.

15

 -
ABUS
DBUS

!

RDBUS
FCBUS
0 1

1.
ABUS
RDBUS. ABUS ,
RDBUS .
1.-2. ABUS

.
16

 -
ABUS
DBUS

!

RDBUS
FCBUS
0 1

2 3

2.

HIT, RDBUS
.
2-3. RDBUS ,
HIT
.
17

ABUS
DBUS

!

RDBUS

FCBUS
0 1

2 3

3.
DBUS FCBUS.
DBUS , FCBUS
.

18

ABUS
DBUS

!

RDBUS

FCBUS
0 1

2 3

4. DBUS
, FCBUS .

19

ABUS
DBUS

!

RDBUS

FCBUS
0 1

2 3

56

5. FCBUS
DBUS .

20

ABUS
DBUS

!

RDBUS

FCBUS
0 1

2 3

56

6. RDBUS
, DBUS
.

21

ABUS
DBUS

!

RDBUS

FCBUS
0 1

2 3

56

7 8

7. RDBUS
DBUS
, FCBUS
.

22

ABUS
DBUS

!

RDBUS

Master
Slave

FCBUS
0 1

2 3

highZ

56

7 8

8. FCBUS
ABUS
. .

23

ABUS
DBUS

!

WRBUS

Master
Slave

FCBUS
0 1

2 3

highZ

56

7 8

(/ )
.
DBUS
RDBUS WRBUS.

24


DBUS

!

inta

FCBUS
0 1

highZ

45

(/ )
.

ABUS RDBUS
inta.

25


inta

.

inta
RDBUS .
DBUS
FCBUS

.

26





,


.



RDBUS, WRBUS FCBUS.

27



MCLK
.
:

ABUS
DBUS
RDBUS
WRBUS
MCLK
inta

?
MCLK

28


--
MCLK
ABUS
DBUS

!

RDBUS
0 i

i+1

0.
ABUS RDBUS
.
DBUS.

29


--
MCLK
ABUS
DBUS
RDBUS
0 i

i+1

i. i.
ABUS RDBUS
.
i. i+1. i. (i+1).
( HIT).

30


--
MCLK
ABUS

DBUS
RDBUS
0 i

i+1

i+1. (i+1). RDBUS

.
i+1. j. (i+1).
RDBUS
, .
DBUS

31


--
MCLK
ABUS

DBUS
RDBUS
0 i

i+1

Master
Slave

j+1

j+1. (+1).
ABUS RDBUS
.
j+1. (+1)-
DBUS
.

32


--
MCLK
ABUS
DBUS
WRBUS
!

Master
Slave

0 i

i+1

highZ

j+1

.
DBUS
RDBUS
WRBUS.

33


MCLK
ABUS

DBUS

inta

Master

0 i

i+1

Slave

j+1

.

ABUS RDBUS
, inta,
DBUS.
34





,

.

,

,



.
35


Latency ( , )

Throughput

Bandwidth

I/O
36



.

:

.

37



.
/
:

/
hreq hack.
hreq
.
hack
.

38

 -
hreq
hack.
hack

hreq
.

hreq ,
, hack
,
.

39


hreq

1.
2.
3.
4.
5.
6.
7.
8.

hack

procesor
hreq
hack
uredaj

40


hreq

1.
2.
3.
4.
5.
6.
7.
8.

hack

procesor
hreq

hack
uredaj

,






41


hreq

1.
2.
3.
4.
5.
6.
7.
8.
9.

hack

procesor
hreq
hack
uredaj

,



42



,
/
,
,

.


:

(Daisy chain).

43


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT

moduli
BR

BG_IN

BG_OUT
BG_IN

BR0
BG0
BR1
BG1

BRi
BGi

:
BR (Bus Request) -

BG (Bus Grant) -

BUSYBUS
44

BG0

BG1

0
DC 1

m-1
BGn-1

BR0

BR1

1 CD

m-1
n-1
W

n-1E

BRn-1

45

BG0

BG1

0
DC 1

m-1
BGn-1

BR0

BR1

1 CD

BR0
BG0

m-1
n-1
W

n-1E

BRn-1

46

BG0

BG1

0
DC 1

m-1
BGn-1

BR0

BR1

1 CD

BR1
BG1

m-1
n-1
W

n-1E

BRn-1

47

BG0

BG1

0
DC 1

m-1
BGn-1

BR0

BR1

1 CD

m-1
n-1
W

n-1E

BR0 BR1

BG0
BRn-1

48

BG0

BG1

0
DC 1

m-1
BGn-1

BR0

BR1

1 CD

m-1
n-1
W

n-1E

BRn-1

49


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT

moduli
BR

BG_IN

BG_OUT
BG_IN

BR0
BG0
BR1
BG1

BRi
BGi

BUSYBUS

50


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT
BG_IN

moduli
BR

BG_OUT
BG_IN

BR0
BG0
BR1
BG1

BRi
BGi

1. 1
2. 1
3. ,
1 BUSYBUS

4. 1

51


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT
BG_IN

moduli
BR

BG_OUT
BG_IN

BR0
BG0
BR1
BG1

BRi
BGi

1. 1
2. 0
3. 0
1
4. 0 1
(BUSYBUS )

52


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT
BG_IN

moduli
BR

BG_OUT
BG_IN

BR0
BG0
BR1
BG1

BRi
BGi

1. 0 ,
BUSYBUS
2. BUSYBUS
0, BUSYBUS

3. 0
53


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT
BG_IN

moduli
BR

BG_OUT
BG_IN

BR
BG

( )

(Daisy chain)
i ( ) BG_IN
i-1 ( )
BG_OUT
54

BR

BG

BR

BG

!!

BR

55


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT

moduli
BR

BG_IN

BG_OUT
BG_IN

BR
BG

BUSYBUS

56


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT
BG_IN

moduli
BR

BG_OUT
BG_IN

BR
BG

1. 1
2. 0.
0
3. 1
, BUSYBUS
4. 1
57


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0
BR

BG_OUT
BG_IN

moduli
BR

BG_OUT
BG_IN

BR
BG

1. 1
2. 0
3.
0. 0
4. 0 1
(BUSYBUS )

58


BUSYBUS
BCLK

BR

BG_OUT
BG_IN

modul1

modul0

BG_OUT

BR
BG_IN

moduli
BR

BG_OUT
BG_IN

BR
BG

1. 1 ,
BUSYBUS
2. BUSYBUS
0, BUSYBUS

3. 0
59


BUSYBUS
REGBUS
BCLK

modul
0

BR

modul
1

BG_OUT
BG_IN

BR

...
...
0
0

BG_OUT
BG_IN

modul
(n-1)

...

CD
...
...
...

BR

BG_OUT
BG_IN

n-1

m-1
m-1

DC
0

...
...

n-1

ARBITRATOR

60


BUSYBUS
REGBUS
BCLK

modul
1

modul
0
BR
BG_IN

BG_OUT
1

BR
BG_IN

...

BG_OUT

...

modul
(n-1)
BR
BG_IN

BG_OUT

61




.


.

62



?

.

63




(LOAD/STORE),
/
.

(IN/OUT)

(LOAD/STORE),
/
.
M/IO
64

 -
/


. ( )
/


.
:
M/IO 0,
M/IO 1.

65

: IO

memorija

u/i uredaj bez DMA

u/i uredaj bez DMA

UPRAVLJACKA
JEDINICA
stWR RD WR
stRD

UPRAVLJACKA
JEDINICA
stWR RD WR
stRD

UPRAVLJACKA
JEDINICA
stWR RD WR
stRD

LOKACIJE

HIT
DEKODER
ADRESA

LOKACIJE

HIT
DEKODER
ADRESA

...

HIT
DEKODER
ADRESA

LOKACIJE

ABUS
DBUS
RDBUS
WRBUS
FCBUS
MAR

MDR

UPRAVLJACKA
JEDINICA
procesor

MAR

MDR
LOKACIJE

RD WR stRD
UPRAVLJACKA
JEDINICA
u/i uredaj sa DMA

DEKODER
ADRESA
HIT

stWR

MAR
...

MDR
LOKACIJE

RD WR stRD
UPRAVLJACKA
JEDINICA
u/i uredaj sa DMA

DEKODER
ADRESA
HIT

stWR

66

: IO
memorija

u/i uredaj bez DMA

u/i uredaj bez DMA

UPRAVLJACKA
JEDINICA
stRD
stWR RD WR

UPRAVLJACKA
JEDINICA
stRD
stWR RD WR

UPRAVLJACKA
JEDINICA
stRD
stWR RD WR

LOKACIJE

HIT
DEKODER
ADRESA

LOKACIJE

HIT

...

HIT

DEKODER
ADRESA

LOKACIJE

DEKODER
ADRESA
ABUS
DBUS
RDBUS
WRBUS
FCBUS
M/IO

MAR

MDR

UPRAVLJACKA
JEDINICA
procesor

MAR

MDR
LOKACIJE

RD WR stRD
UPRAVLJACKA
JEDINICA
u/i uredaj sa DMA

DEKODER
ADRESA
HIT

stWR

MAR
...

MDR
LOKACIJE

RD WR stRD
UPRAVLJACKA
JEDINICA
u/i uredaj sa DMA

DEKODER
ADRESA
HIT

stWR

67



.



.

68


- ( )

I/O Bus ( : SCSI, USB, ISA, IDE)

,
backplane

Backplane Bus ( : PCI)

backplane chassis


69


Processor-Memory Bus
Processor

Memory
Bus
Adaptor
I/O
Bus

Bus
Adaptor

Bus
Adaptor

I/O
Bus

I/O
Bus

I/O
Bus
Adaptors

-:

I/O :
70


Processor-Memory Bus
Processor

Memory
Bus
Adaptor
Bus
Adaptor

Backplane Bus
Bus
Adaptor

I/O Bus
I/O Bus

Backplane
-
-:
I/O Backplane

:
-
71