I HC BCH KHOA H NI

KHOA IN B MN IU KHIN T NG

THIT K H THNG X L NH S
TRN NN FPGA
Nhm sinh vin thc hin: Ng Hi Bc

Trung Hiu
Lp : iu khin t ng 1 K48
Gi{o vin hng dn:
Ts. Lu Hng Vit
H Ni, 6 - 2008
1

Mc lc
M u

Bi ton t ra v nhim v

Phn 1

Khi qut

Phn 2

Gii php phn cng FPGA

Phn 3

Thc thi h thng

Phn 4

M phng, kt lun v m rng

Phn m u
Bi ton iu khin tay my

Nhim v

Thit k h thng quan st (th gic my)phc v iu

khin tay my:
Thu thp hnh nh i tng
X l v tnh ton cc c trng i tng: v tr,
kch thc.
Truyn cc thng s i tng ti h thng iu
khin nhm iu khin chnh xc tay my.
Cn c mt h quan st ( th gic my) ng vai tr con mt
quan st phc v iu khin tay my
3

Phn 1: Khi qut

1.1.

Th gic my v Sensor th
gic.

1.2.

H thng x l nh s.

1.3

Cc thut ton x l nh s.

1.1. Th gic my v sensor th gic

nh ngha
ng dng
Phm vi ng
dng

u im

Victhng
Lng
H
iu
skhin
dng
thng
sn tin
cc
xut,
tin
thit
trnh
x
iu
b
l(khin,
quang
ln
iu gim
khin
hc v
st
phc
tay
khng
m{y,
tp:
tipCNC,
xc,
xet
tng
h|nhvi
thu
) thp
v
Linh
hot,
d
thch
ng
nhiu
T
phn
Sn
tch
phm
hnh
a
dng,
vi
mc
thay
ch
i
thu
thp
dng
ng
sn
phm,
ha nh
taquy
nh|trnh
cng
ngh,
mi
thng
H
tin
thng
vs
iu
gi{m
khin
my
t hin
ng,
mc s
hoc
tc
qu

trng
sn
xut.
Ph{t
hin
kin
(s{t
ph{t
thay
cao,
trnh.
trnh.
Kh)gi{m
i
nngs{t
xa
l qu{
thng
tin phc tp,
Lin
Quy
trnh
cng
ngh
thay
i.
quan
n
nhiu
ng|nh
:
quang
h
tr
h
thng
iu
khin
ra
quyt
Nhn
dng
( khun
mt,
k t,
hnh
hc,C
s
xut
hin
ca
robot
cng
to{n hc, phn mm, in t, c
nh.
dng)
nghip.
hc
Kh
nng
loi
li (fault
Qu}n
s.th
Thay
sb
gi{m
s{t catolerance)
con ngi.

1.2. H thng x l nh s
Phn vng,
phn ngng

Biu din

Tin x l

C s kin thc

X l v
nhn dng

Thu nhn
nh

1.3. C{c thut to{n x l nh s

Ton t ca s
Lc

Dbin
bin
D

Loi
nhiu,
thin
X lb
ng
cuci
nh
nh nh.
ph}n: ci
c12ha:c13t{ch
1tng
1 1
cph}n
i
tng
11nh,
Nh
i
thin
loi
b
nh

n m
c(nhiu)

c23 11 2 81 1
c12c22 cA
khi
nn
c11c21
13
I
(
i
,
j
)
1

1
c c21c31 c22c32c23 c33i 1 j2
4
2
1

16
c

1 2 1
c
c
31 32 33

Phn ngng,
phn vng

1 n m
x i.I (i, j );
A i 1 j 1

X l ng cu

1 n n
y j.I (i, j );
A i 1 j 1

c trng
7

Phn 2: Gii php phn cng FPGA

2.1.

Khi qut FPGA.

2.2.

Mch XST-3S 1000.

2.3.

Vi x l nhng Picoblaze.

2.4.

Cng c ISE, Sysgen.

2.1. Khi qut v FPGA

Khi nim

u im
ng dng
Kin trc

Ngn ng

FPGA
Programable
Gate(CLBs)
Arrays)
l
X
l(Field
tn hiu
s,
x l
nh,
th
gic my,
CPLD
FPGA
Configuration
logic
blocks
mt
bn dn
nhnthit
dngbging
ni,bao
mgm:
ha, m phng
SCc
lng
cng
1000
n
10.000
10.000 n vi
Configurable
I/O
blocks
(IOB)
ngn
ng
m
t
phn
cng:
(emulation)...
Cc khi logic lp trnh c triu
gi l
VHDL
Programmable interconnect
"Logic
Block
Kin
Cc
lnh
vcKm
hoclinh
ng
dng m
kin kt
trc
trc
hot,
S lng
Thm:
Verilog
ca
nkt
yuni
cu
mt
lng
ln
song
d
o{n
tr
vrt
t(thc
nix
ln,llinh
Cc
cu
hnh
c
hin
cc
logic
ktgii
ni
hot
hn. Gm
Schematic
Mch

truyn
tnm.
hiu
clock
song,
nhclock
l
ml
ha
v
chc
nng
ca
cc
khi
logic
c
bn
nh
cao hn.
cc phn t
ti cc
logic
block.
AND,
XOR
hoc
hoc
ccthi
php
Trong
nhng
ngdecoder
dng cn
thc
cc
tch
hp
cao.
Logic
resources
memory
tnh
ton
hc)
thut
tonm
nh FFT,nh
nhnALUs,
chp Cho
Lp
trnh,
php cu
rng
hnh
v c th c c
decoders.
(convolution),
thay
th cho vi x
l.li tng
phn, c th
Cc phn t lp trnh c cathm
FPGA
cc soft
v
c 2 dng c bn l cc RAMprocessor
tnh
(Static RAM) v anti-fuses. embedded
processor

2.2. Mch XST-3S1000

XST-3.0
XSA-3S1000

10

2.3. Vi x l nhng 8 bit PicoBlaze

PicoBlaze 8-bit Embedded Microcontroller

11

Phn 3: Thc thi h thng

3.1.

S cu trc v cc
thnh phn h thng.

3.2.

B iu khin trung tm.

3.3.

Giao din HMI.

3.4.

Image Processing Core

12

3.1. S cu trc ca h thng

Parallel Port

Video Codec

Framegrabber to
SDRAM

Framegrabber Buffer

Dual Port
Store FIFO
VGA
Buffer
Generator

VGA Port

FPGA
Dual Port

SDRAM
Controller

SDRAM

Read FIFO
Buffer
RS232 PORT

Center Control
System

Dual Port

Image Processing Core

Store FIFO
Buffer

13

3.2. B iu khin trung tm

RX

UART
Receive
Component

algorithm_sel
Instruction ROM

RS232 Port

Capture

TX

UART
Transmit
Component

KCPSM3

Done signals

PicoBlaze Microcontroller

14

3.3. Giao din HMI

Cu hnh
Thc
Downloadchuwowng
hingiao
chntip
thut
RS232
ton
trnhv
v
vo
I2C
capture
FPGAnh
hoc Flash
15

3.4. Image Processing Core

Read_FIFO

FIFO_to_Buffer

Buffer

picoblaze

Algorithms
select

Processing
Algorithms

Store_FIFO

16

Phn 4: M phng, kt lun, m

rng
4.1.

Thc hin kim tra hot

ng h thng

4.2.

Kt lun.

4.3.

M rng.

17

4. Thc hin kim tra hot ng h

thng
Kim tra vi trng hp c 1 i tng cn nh v.

Thc hin ln lt c{c bc t thu thp nh n x{c

nh c trng.
Quan s{t kt qu trn m|n hnh hin th v| giao din
HMI

18

4.1. Thc hin kim tra hot ng h

thng
Chun b

Chy chng trnh HMI

Gn ngun, ngoi vi cho mch

Np file cu hnh

Np file video.bit

Kch hot chip Video Decoder

Capture nh

Quay camera n hng thch hp

Nhn nt Capture capture nh

Thc hin tun t cc thut ton

Thut ton 1

Thut ton 2

Thut ton 3

Thut ton 4

Thut ton 5

Thut ton 6
19

4.2. Kt qu
Cc thut ton lc, d bin, phn ngng, x l ng
cu nh nh phn thc hin chnh xc.
Kt qu phn ngng khng tht tt trong iu kin nh
sng qu chi hoc qu ti, do cha ci thin tng
phn.
Cc thnh phn h thng khc hot ng ng nh thit
k mong mun.
Xc nh c v tr v kch thc i tng.
=> Hon thnh nhim v t ra : xy dng h th gic my
quan st i tng phc v iu khin tay my
20

4.3. Kt lun
Nhn xt :
FPGA l gii php ph hp cho bi ton x l nh.

H thng x l nh vi tc cao, chnh xc, nh c ch x l

song song.
Thch hp cho cc h th gic my x l vi tc cao.

M rng :
Xc nh i tng chuyn ng.
M rng kh nng giao tip : RS232, RS485, Ethernet, USB,
CAN
Ci thin cc thut ton: Lc nhiu, Gn nhn i tng, loi
b cc i tng nh.
21

Chng em xin ch}n th|nh cm n !

22