Chng 2 : Tm tt phn cng

TM TT PHN CNG
2.1 TNG QUT
MCS-51 l h vi iu khin ca Intel. Cc nh sn xut IC khc nh Siemens,
Advanced Micro Devices, Fujitsu v Philips c cp php lm cc nh cung cp
th hai cho cc chip ca h MCS-51.
Chng ny gii thiu v cu trc phn cng ca h MCS-51. Tham kho k
thut ca Intel cho cc chip ca h MCS-51 c tm thy ph lc E. Ta cn bit
thm nhiu chi tit trong ph lc ny, th d nh cc c tnh in chng hn.
Nhiu c trng phn cng c minh ha bng cc chui lnh ngn, cc m t
vn tt cng c cung cp cho tng th d cn cc chi tit y ca tp lnh
c dnh li cho chng 3. Ta c th tham kho ph lc A ( tm tt tp lnh ca
8051 ) v ph lc c ( cc nh ngha cho tng lnh ca 8051 ).
Vi mch tng qut ca h MCS-51 l chip 8051, linh kin u tin ca h ny
c a ra th trng. Chip 8051 c cc c trng c tm tt nh sau :
-

4KB ROM
128 byte RAM. ^
4 port xut nhp ( I/O port ) 8-bit. \/ 2 b nh thi
16-bit. v'x Mch giao tip ni tip. ^

Khng gian nh chng trnh ( m ) ngoi 64K.

Khng gian nh d liu ngoi 64K. y B x l bit
( thao tc trn cc bit ring r )
210 v tr nh c nh a ch, mi v tr 1 bit.
Nhn/chia trong 4^s.
Cc thnh vin khc ca h MCS-51 c cc t hp ROM ( EPROM ), RAM trn chip
khc nhau hoc c thm b nh thi th ba ( xem bng
2.1 ). Mi mt IC ca h MCS-51 cng c phin bn CMOS cng sut thp.

XU 1 UiCU 1V111C11

Chip
8051

B nh chdng trnh trn B nh d liuCc b nh

chip
thi
trn chip
4 KROM
128 byte
2

8031

0K

128 byte

8751

4 KEPROM

128 byte

8052

8 K ROM

256 byte

8032

0K

256 byte

8752
8 K EPROM
256 byte
Bng 2.1 : So snh cc chip ca h MCS-l

Interrupt control : diu khin ngt

Other registers : cc thanh ghi khc
128 bytes RAM : RAM 128 byte
Timer 2, 1, 0 : b nh thi 2, 1, 0
CPU : dn v diu khin trung tm
Oscillator : mch dao ng
Bus2.1 : S d khi ca chip 8051
Hnh
control : iu khin bus I/O ports : cc
port xut/nhp Serial port : port ni

Chng 2 : Tm tt phn cng

tip Address/data : a ch/d liu

Thut ng 8051 c dng ch rng ri cc chip ca h MCS- 51. Khi
vic tho lun tp trung vo mt ci tin t chip 8051 c bn, chip ci tin c ch
ra r rng. Cc c trng va nu trn c trnh by trong s khi hnh 2.1.

Hnh 2.2 : S d chn ca 8051

20

H vi iu khin 8051

2.2 CC CHN ( PINOUT )

Hnh 2.2 cho ta s chn ca chip 8051. M t tm tt chc nng ca tng chn
nh sau.
Nh ta thy trong hnh 2.2, 32 trong s' 40 chn ca 8051 c cng dng xut/nhp,
tuy nhin 24 trong 32 ng ny c 2 mc ch ( cng dng ) [ 26/32 i vi
8032/8052 ]. Mi mt ng c th hot ng xut/nhp hoc hot ng nh mt
ng iu khin hoc hot ng nh mt ng a ch/d liu ca bus a ch/d
liu a hp.
Cc c trng cp trn c trnh by trong s khi hnh 2.1.
32 chn nu trn hnh thnh 4 port 8-bit. Vi cc thit k yu cu mt mc ti
thiu b nh ngoi hoc cc thnh phn bn ngoi khc, ta c th s dng cc port ny
lm nhim v xuVnhp. 8 ng cho mi port c th c x l nh mt n v giao
tip vi cc thit b song song nh my in, b bin i D-A, v.v... hoc mi ng c
th hot ng c lp giao tip vi mt thit b n bit nh chuyn mch, LED, BJT,
FET cun dy, ng c, loa, v.v...
2.2.1 Port 0
Port 0 ( cc chn t 32 n 39 trn 8051 ) c 2 cng dng. Trong cc thit k c
ti thiu thnh phn, port 0 c s dng lm nhim v xut/nhp. Trong cc thit k
ln hn c b nh ngoi, port 0 tr thnh bus a ch v bus d liu a hp [ byte thp
ca bus a ch nu l a ch ] ( xem 2.6 : B nh ngoi ).
2.2.2 Port 1
Pp- 1 ph r--mt cng dung l xut/nhp ( cc chn t 1 n 8 trn 8051 ). Cc
chn ca port 1 c k hiu l Pl.o, Pl.l, ... , P1.7 v c dng giao tip vi thit
b bn ngoi khi c yu cu. Khng c chc nng no khc na gn cho cc chn ca
port 1, ngha l chng ch c s dng giao tip vi cc thit b ngoi vi.[ Ngoi
l : vi 8032/8052, ta c th s dng Pl.o v Pl.l hoc lm cc ng xut/nhp hoc
lm cc ng vo cho mch nh thi th ba ].
2.2.3 Port 2
Port 2 ( cc chn t 21 n 28 trn 8051 ) c 2 cng dng, hoc lm nhim v
xuVnhp hoc l byte a ch cao ca bus a ch 16-bit cho cc thit k c b nh
chng trnh ngoi hoc cc thit k c nhiu hn 256 byte b nh d liu ngoi.

Chng 2 : Tm tt phn cng

2.2.4 Port 3
Port 3 ( cc chn t 10 n 17 trn 8051 ) c 2 cng dng. Khi khng hot ng
xuVnhp, cc chn ca port 3 c nhiu chc nng ring ( mi chn c chc nng
ring lin quan n cc c trng c th ca 8051 ).
Bng 2.2 di y cho ta chc nng ca cc chn ca port 3 v 2 chn Pl.o, Pl.l
caport 1.
Bit
P3.0

Tn
RxD

a ch bit
BOH

Chc nng
Chn nhn d liu ca port ni tip

P3.1

TxD

B1H

Chn pht d liu ca port ni tip

P3.2

INTO

B2H

Ng vo ngt ngoi 0

P3.j?

INT1

B3H

Ng vo ngt ngoi 1

P3.4

TO

B4H

Ng vo ca b nh thi/m 0

P3.5

TI

B5H

Ng vo ca b nh thi/m 1

P3.6

WR

B6H

iu khin ghi b nh d liu ttgoi

P3.7

RD

B7H

iu khin c b nh d liu ngoi

Pl.o

T2

90H

Ng vo ca b nh thi/m 2

Pl.l

T2EX

91H

Np li/thu Iihn ca b dinh thi 2

Bng 2.2 : Chc nng ca cc chn ca port 3 v port 1

2.2.5 Chn cho php b nh chng trnh PSEN
8051 cung cp cho ta 4 tn hiu iu khin bus. Tn hiu cho php b nh chng
trnh PSEN ( program store enable ) l tn hiu xut trn trn chn 29. y l tn hiu
iu khin cho php ta truy xut b nh chng trnh ngoi. Chn ny thng ni vi
chn cho php xut OH ( output enable ) ca EPROM ( hoc ROM ) cho php c
cc byte lnh.
Tn hiu PSEN logic 0 trong su't thi gian tm-np lnh. Cc m nh phn ca
chng trnh hay opcode ( m thao tc ) c c t EP- ROM, qua bus d liu v
c cht vo thanh ghi lnh IR ca 8051 c gii m.
Khi thc thi mt chng trnh cha ROM ni, PSEN c duy tr logic khng
tch cc ( logic 1 ).

22

H vi iu khin 8051

2.2.6 Chn cho php cht a ch ALE

8051 s dng chn 30, chn xut. tn hiu cho php cht a ch ALE ( address
latch enable ) gii a hp ( demultiplexing ) bus d liu v bus a chi. Khi port
0 c s dng lm bus a chi/d liu a hp, chn ALE xut tn hiu cht a
chi ( byte thp ca a chi 16-bit ) vo mt thanh ghi ngoi trong sut V u ca
chu k b nh ( memory cycle ). Sau khi iu ny c thc hin, cc chn ca
port 0 s xut./nhp d liMi hp h trong sut V2 th hai ca chu k b nh.
Tn hiu ALE c tn s bng 1/6 tn s ca mch dao ng bn trong chip vi
iu khin v c th c dng lm xung clock cho phn cn li ca h thng. Nu
mch dao ng c tn s 12 MHz, tn hiu ALE c t,n s 2 MHz. Ngoi h duy
nht, l trong thi gian thc thi lnh MOVX, mt xung ALE s b b qua ( xem
hnh 2.10 ). Chn ALE C 11 c dng nhn xung ng vo lp trnh (o
EPROM trn chip i vi cc phin bn ca 8051 c EPROM ny. V
2.2.7 Chn truy xut ngoi L A
Ng vo ny ( chn 31 ) c th c ni vi 5 V ( logic 1 ) hoc vi GND (
logic 0 ). Nu chn ny ni ln 5 V, 8051/8052 thc: th^ chng trinh trong ROM
ni ( chng trnh nh hn 4K/8K ). Nu chn ny ni vi GNEM^va~chan PSIiN
cng logic 0 ), chng trnh cn thc thi cha oTbcTnhd ngoi. oTvi
8031/8032 cKan~T!?r-pHai-#-4ogic'Trvi chng khng c b nh chng trnh trn
chip. Nu chn HA logic 0 i vi 8051/8052. ROM ni bn t.rong chip c v
hiu ha v chng trnh cn thc thi cha EPROM bn ngoi.
/ Cc phin bn EPROM ca 8051 cn s dng chn HA lm chn nhn in p cp
in 21V ( v,)() ) cho vic lp trnh EPROM ni ( np L IEPRM ).
2.2.8 Chn RESET ( RST )
Ng vo RST ( chn 9 ) l ng vo xa chnh ( master reset ) ca 8051 dng
thit, lp li trng thi ban u cho h thng hay gi tt. l reset h thng. Khi ng
vo ny c treo logic 1 ti thiu hai chu k my, cc thanh ghi bn trong ca
8051 c np cc gi tr thch hp cho vic khi ng li h thng ( xem mc
2.8 ).
2.2.9 Cc chn XTAL1 v XTAL2
Nh c v trn hnh 2.2. mch dao ng bn trong chip 8051 c ghp vi
thch anh bn ngoi hai chn XTAL1 v XTAL2 ( chn 18 v
19 ). Cc t n nh cng c yu cu nh trn hnh ny. Tn s danh nh ca
thch anh l 12 MHz cho hu ht cc chip ca h MCS-51 ( 80C31BH-1 s dng
thch anh 16 MHz bn trong, mch dao ng trong chip khng cn thch anh bn
ngoi ). hnh 2.3, 1 ngun xung clock TTL c th c ni vi cc chn XTAL1
v XTAL2.

Chng 2 : Tm tt phn cng

23 j

Hnh 2.3 8051 ghp vi mch dao ng TTL bn ngoi TTL oscillator : mch dao ng
TTL

2.3 CU TRC CA PORT XUT/NHP

S mch bn trong cho cc chn ca port xut/nhp c v n gin nh
hnh 2.4. Vic ghi n 1 chn ca port s np d liu vo b cht, ciia port, ng ra
Q ca b cht iu khin mt transistor trng v transistor ny ni vi chn ca
port. Kh nng fanout, ca cc port, 1. 2 v 3 l 4 ti vi mch TTL loi Schottky
cng sut thp ( LS ) cn cua port. 0 l 8 ti loi LS ( xem thm chi tit ph lc
E ).
Lu l in tr ko ln ( pull up ) s kVinnp r port 0 L-tr khi port, ny
lm nhim v ca bus a ch/d liu a hp ), do vy mt in tr ko ln bn
ngoi phi c cn n.
Gi tr ca in tr ny ph thuc vo c tnh ng vo ca thnh phn ghp
ni vi chn cua port,.

Write _
to latch

* Opel) drain output for Poi't

0 when operating as ail
I/O port

8051 internal bus : bus ni ca 8051

Read latch : c b cht
Internal pull up : ko ln bn trong
Read pin : c chn port
Port pin : chn port
Port latch : b cht ca port

Hnh 2.4 : Mch bn trong ca cc port xut nhp

S) 24

H vi iu khin 8051

Write to latch : ghi vo b cht

y ta thy c c 2 kh nng : c b ch't v c chn port". Cc lnh
yu cu thao tc c-sa-ghi ( nh lnh CPL P1.5 ) c b cht trnh s hiu
nhm mc in p do s kin dng ti tng. Cc lnh nhp 1 bit ca port ( nh
MOV c, P1.5 ) c chn port. Trong trng hp ny b cht ca port phi cha 1
nu khng FET s c kch bo ha v iu ny ko ng ra xung mc thp. Vic
reset h thng s set tt c cc b cht port, do vy cc chn port c th c dng
lm cc ng nhp m khng cn phi set cc b cht port mt cch tng minh.
Tuy nhin nu mt b cht port b xa ( nh CLR P1.5 ), chn port khng th lm
nHmvu tip theo l ng nhp tr khi trc tin ta phi set b cht ( nh SETB
Pl.5 ).
Hnh 2.4 khng trnh by mch cho cc chc nng khc ca cc port 0, 2 v 3.
Khi cc chc nng khc c s dng, cc mch kch ng ra c chuyn n mt
a ch ni ( p o r t 2 ), a ch/d liu ( p o r t 0 ) hoc tn hiu iu khin ( p o r t 3 )
tng ng.
2.4 T CHC B NH
Hu ht cc b vi x l ( CPU ) u c khng gian nh chung cho d liu v
chng trnh. iu ny cng hp l v cc chng trnh thng c lu trn a
v c np vo RAM thc thi; vy th c hai, d liu v chng trnh, u lu
tr trong RAM.
Cc chip vi iu khin him khi c s dng ging nh cc CPU trong cc h
my tnh, thay vo chng c dng lm thnh phn trung tm trong cc thit k
hng iu khin, trong b nh c dung lng gii hn, khng c a v h
iu hnh. Chng trnh iu khin phi thng tr trong ROM.
Do l do trn, 8051 c khng gian b nh ring cho chng trnh v d liu.
Nh ta thy trong bng 2.1 mc 2.1, c 2 b nh chng trnh v d liu u
t bn trong chip, tuy nhin ta c th m rng b nh chng trnh v b nh d
liu bng cch s dng cc chip nh bn ngoi vi dung lng ti a l 64 K cho
b nh chng trnh ( hay b nh m ) v 64 K cho b nh d liu.

Chng 2 : Tm tt phn cng

B nh ni trong chip bao gm ROM ( ch c 8051/8052 ) v RAM. RAM

trn chip bao gm vng RAM a chc nng ( nhiu cng dng ). vng RAM vi
tng bit c nh a ch ( gi tt l vng RAM nh a ch bit ), cc dy ( bank )
thanh ghi v cc t.hanh ghi chc nng c bit SFR ( special function register ).
Hai c tnh ng lu l :
(a) cc thanh ghi v cc port xut/nhp c inh ia ch theo kiu nl^sx
b nh ( memory mapped ) v c truy xut nh

(b) vng stack thng tr t.ronp RAM trn chip ( RAM ni ) thay v
trong RAM ngoi nh i vi cc b vi x l.
Hnh 2.5 tm tt cc khng gian nh cho chip 8031 khng c ROM ni, khng
trnh by chi tit v b nh d liu trn chip ( cc ci t.in ca 8032/8052 s c
tm tt. sau ).
Hnh 2.6 cho ta chi tit cua b nh d liu t.rn chip. Ta thy rng khng gian
nh ni ny c chia thnh : cc dy thanh ghi ( 00H 4- 1FH ), vng RAM nh
a chi bit ( 20H -- 2FH ), vng RAM a mc ch ( 30H -T 7FH ) v cc thanh
ghi chc nng c bit ( 80H -T FFH ).
FFF
F

Code

F F Ft

memory

memory

enabled

enabled

via PSEN

via RD
0000

Hnh 2.5 :
TIII tt cc
khng gian
nh' ca chip

On-chip

memory

00
00

Data

Extern
nl
memory

8031
On-chip memory : b nh trn chip
External memory : b nh' ngoi
Code memory : b nh' chng trnh ( m )
Enabled via FSHN : c cho php bi PSlN Data memory :
b nh d liu
Enabled via RD and WR : c cho php bi Rl) v WR

and WR

26

H vi iu khin 8051

2.4.1 Vng RAM a mc ch

Mc d hnh 2.6 trnh by vng RAM a mc ch c 80 byte t a ch t
30H n 7FH, bn di vng ny t a ch 00H n 2FH l vng nh c th c
s dng tng t ( mc d cc v tr nh ny c cc mc ch khc nh s tho lun
di y ). Bt k v tr nh no trong vng RA.M a mc ch u c th c
truy xut t do bng cch s dng cc kiu nh a ch trc tip hoc gin tip. Th
d c ni dung ti a ch 5FH ca RAM ni vo thanh cha A, ta dng lnh
sau :
MOV A, 5FH
Lnh trn di chuyn 1 byte d liu bng cch dng kiu nh a ch trc tip
xc nh v tr ngun ( ngha l a ch 5FH ). ch ca d liu c xc nh r
rng trong opcode ca lnh l thanh cha A ( cc kiu nh a ch s c cp
trong chng 3 ).
Byte

By

address

Le

7F

addres
s FF
FO

3 by Ui

F7|p6|FSF4|F3|F2|FlF
7|E6|E5|B4|E3|E2[E1|

purpose

RAM

D7|DG|5|D4|D3|D2|DI|

30

BC|BD|BA|

2F

7F 7E 7D 7D 7B 7A 79 78

2E

77 76 75 74 73 72 71 70

2D

6F 6E 6D ec 6B 6A

2C

67

66

65

64

63

62

61

60

2B

5F

5E

5D

5C

5B

5A 59

58

.2

2A

57

56

55

54

53

52

51

50

29

4F

4E

4D

4c

4B

4A 49

48

4>

28

47

46

45

44

43

42

41

40

27

3F

3E

3D

3C

3B

3A 39

38

'U

26

37

36

35

34

33

32

31

30

25

2F

2E

2D

2C

2B

2A 29

28

24

27

26

25

24

23

22

21

20

23

IF

IE

ID

1C

IB

1A 19

18

22

17

16

15

14

13

12

11

10

21

OF

OD

0c

OB

A 09

08

20

07

06

05

04

03

02

00

' IF 18
byte < 17

01

Bank^

Bank 1

00

- I - AC |AB|AA|A )8

A7|A6|A5|A4|A3|A2|AI|

99
98

not bit addressable

SBUP
SCON

9F 9E 9D 9C 9B 9A 99 98

97|96|95|94|93|92|>l|9Q

8D

not bit addressable

THl

8C

nut bit addressable

THO

HL>t bit addressable

TLl

8A

not bit addressable

TLO

89

not bit addressable

TMOD

8B

87

83

08
07

AF |

88
Bank 2

l
OF

B7 B6 B5 B4 B3 B2 Bl BO

69

8F 8E 8D 8C 8B8A 89

TCON

not bit addressable

PCON

DPH

not bit addressable

82
Defau register bank for
R0-R7

61

not

bit

addressable

addressable

not

bit

DPL
SP

86 H5 B4183| PO
SPECIAL FUNCTION REGISTERS
s2siso

80

87

Hnh 2.6 : B nh d liu trn chip 8051

Chng 2 : Tm tt phn cng

Byte address, bit address : a ch byte, a ch bit

General purpose RAM : vng RAM a mc ch
Bank : dy
Default register bank for RO - R7 : dy thanh ghi mc nh RO - R7
Special function registers : cc thanh ghi chc nng c bit Not bit
addressable : khng nh a ch bit
Vng RAM a mc ch cn c th c truy xut bng cch dng kiu nh
a ch gin ti ftp mifl gc thanh phi RO. R Th d hai lnh sau thc hin ciing'cong
vic nh lnh th d trn :
MOV RO, #5FH
MOV A, @R0
Lnh u tin s dng kiu nh a ch tc thi di chuyn gi tr 5FH vo
thanh ghi RO, lnh tip theo s dng kiu nh a ch gin tip i chuyn d liu
tr bi RO vo thanh cha A.
2.4.2 Vng RAM nh a ch bit
8051 cha 210 v tr bit c nh a ch trong 128 bit cha trong cc byte
a ch t 20H n 2FH [16 byte X 8 bit = 128 bit ] v phn cn li cha trong
cc thanh ghi chc nng c bit.
tng truy xut cc bit ring r thng qua phn mm l mt c trng mnh
ca hu ht cc b vi iu khin. Cc bit c th c set, xa, AND, OR, v.v... bng
mt lnh. Hu ht cc b vi x l yu cu mt chui lnh c-sa-ghi nhn c
cng mt kt qu. Ngoi ra 8051 cn c cc port xut/nhp c th nh a ch tng
bit, iu ny lm n gin vic giao tip bng phn mm vi cc thit b xuVnhp
n bit.
Nh va cp trn, 8051 c 128 v tr bit c nh a ch v c nhiu mc
ch cc byte c a ch t 20H n 2FH. Cc a ch ny c truy xut nh l
cc byte hay cc bit ty vo lnh c th. Th d set bit 67H bng 1 ta dng lnh
sau :
c

~'') SETB 67H

ham chiu hnh 2.6 ta thy bit a ch 67H l bit c ngha ln nnat ca
bte a chi 2CH. Lnh va nu trn khng nh hng n cc bit khc
trong byte ny. Hu ht cc b vi x l mun thc hin Lc nh trn phi dng cc
lnh c dng tng t nh sau :
MOV A, 2CH ;
c c byte
ORL A, #10000000B
;set bit cd ngha ln
MOV 2CH, A ;
ghi tr li c byte

nht

28

Ho vi iu khin 8051
2.4.3 Cc dy thanh ghi
32 v tr thp nht ca b nh ni cha cc'dy thanh ghi. Cc lnh cua 8051 h
tr 8 t.hanh ghi t RO n R7 thuc dy 0 ( bank 0 ). y l dy mc nh sau khi
rcsctAi thHBL Cc thanh ghi ny cc a chi t 00H n 07H. Lnh sau y c
ni dung ti a ch 05H vo thanh cT"
MOV A, R
Lnh ny l lnh 1-byte dng kiu-Lati ia chi thanh ghi. D nhin thao tc
tng t. c th c thc hin vi 1 lnh 2-byte bng cch (mg kiu nh ia chi
trc tip :
MC) OH
Cc lnh s dng cc thanh ghi t RO n R7 l cc lnh ngn v thc hin
nhanh hn so vi cc lnh tng ng s dng kiu nh a ch trc tip. Cc gi
tr d liu thng c s dng nn cha mt trong cc thanh ghi ny. Dy tha nh
ghi ang c s dng c goi l dy thanh ghi tch cc. Dy thanh ghi tch cc
c th thav Vbng carjxjjiay doi cc bii cbB-dy-trQHg: t trang thi
chng trnh PSW ( s cp sau ). Gi s rng dy t.hanh ghi 3 ( bank 3 ) tch cc,
lnh sau dy ghi ni dung ca thanh cha A vo v tr 18H :
MOV RO, A
Y tng cc dy thanh ghi" cho php chuyn i ng cnh nhanh v c hiu
qua nhng ni m cc phn ring r ca phn mm s dng mt tp thanh ghi
ring, c lp vi cc phn khc ca phn mm.
2.5 CC THANH GHI CHC NNG C BIT ( SFR )
Cc t.hanh ghi ni ca hu ht cc b vi x l u c tr u_v xut r ninaMi
mt tp.lnh. Th d lnh INCA ca chip 6809 tng ni dung cua thnh cha A bi
1. Thao tc c xc nh r rng trong opcode ca lnh. Vic truy xut cc thanh
ghi cig c s dng trn 8051. Lnh INC A thc-hin cng cng vic trn.
Cc thanh ghi ni ca 8051 c cu hnh thnh mt phn ca RAM trn chip,
do vy mi mt thanh ghi cng c mt a ch. iu ny hp l vi 8051 v chip
ny c rt nhiu thanh ghi. Cng nh cc thanh ghi t RO n R7, ta c 21 thanh
ghi chc nng c bit SFR chim phn
trn ca RAM ni t a ch 80H n FFH ( xem hnh 2.6 ).
*" " : -------------------------------------- : 1
Lu l khng phi tt c 128 a ch t 80h n FFH u c
nh ngha m ch c 21 a ch c nh ngha [ 26 trn 8032/8052 ].

Chng 2 : Tm tt phn cng

Thanh cha A c th c truy xut r rng nh c minh ha trong cc th d

cc phn trn. Hu ht cc, t.hanh ghi r.hir nng r bit c truy xut bng
kiu nh a ch trc tip. Trong hnh 2.6 ta cn lu l mt s thanh ghi chc
nng c bit c nh a ch tng bit v nh a ch tng byte. Th d ta c lnh
sau :
SETB OEOH
s set bit 0 ca thanh cha A ln 1, cc bit khc ca thanh cha khng thay i. Ta
nhn thy rng ti a ch EOH c th l : a ch byte cho c thanh cha v a ch
bit ca bit c ngha thp nht trong thanh cha. V lnh SETB thao tc trn cc bit
v khng thao tc trn cc byte, ch c bit c nh a ch b nh hng. Lu' l
cc bit dc nh ia chi trong mt thanh ghi chc nng c bit c 5 bit cao cua
a ch ging nhau cho tt c cc bit ca thanh ghi ny. Ly th d port 1 c 'a
ch~bte l^ ( hay 10010000B y~va cc bit~rong port ny c cc a ch t
90H ti 97H hay lOOlOxxxB.
T trng thi chng trnh PSW ( program status wrd ) s c tho lun chi
tit trong mc sau. Cc thanh ghi chc nng c bit khc cng c gii thiu vn
tt, cc chi tit v chng s c cp trong cc chng tip theo.
2.5.1 T trng thi chng trnh PSW
Bit

K hiu a ch

PSW.7

CY

D7H

PSW.6 AC
PSW. 5.
PSW.4 RS1
PSW.3 RSO

M t bit

F0

C nh
D6H

C nh ph

D5H

C 0

D4H

Chn dy thanh

ghi ( bit 1 )

Chn dy thanh

ghi ( bit 0 )

D3H

= bank 0 : a ch t 00H n 07H

= bank 1 : a ch t 08H n OFH

10 bank 2 : a ch t 10H n 17H

PSW.2 ov

PSW.1
PSW.0 p

11 = bank 3 : a ch t 18H n 1FH 1

D2H

C trn

D1H

D tr

DOH

C kim tra chn l

Bng 2.3 : Thanh ghi PSW

S) 30

H vi iu khin 8051

PSW c a. ch l DOH cha cc bit trng thi c chc nng c 1

tt trong bng 2.3. Tng bit ca PSW c kho st. di y :
C nh
C nh CY ( carry flag ) c 2 cng dng. Cng dng truyn thng trong cc php ton
s hc l c set. bng 1 nu c s nh t php cng bit. 7 hoc c s mn mang
n bit 7. Th d nu thanh cha A c ni dung l FFH, lnh :
ADD A, #1
s lm cho thanh cha A c ni dung l 00H v c CY trong PSW dc set bng 1.
C nh CY cn l thanh cha logic c dng nh mt thanh ghi 1-bit i vi
ccJjih46gic-JJiao-te--fefaxc-bit. Ly th d lnh sau (lay s AND bit 25H vi
c nh CY v dt kt. qu tr v c nh :
ANL c, 25H

; AND bit ' a chi 25H vi c' nh

n/ C nh ph
Khi cng cc gi tr BCD, c nh ph AC ( auxiliary carry flag ) c set hang
1 nu c mt s nh c to ra t bit 3 chuyn sang bit 4 hoc 11PU kt qua trong
-ct thp nm trong tm t OAH n 0FH. Nu cc gi tr c cng l gi tr
BCD, lnh cng phi c tip theo bi lnh DA A ( hiu chinh thp phn thanh
cha A ) a cc kt qu ln hon 9 v gi tr ng.
C 0
y l c c nhiu mc ch dnh cho cc ng dng ca ngi lp trinh.
Cc bit chn dy thanh ghi
Cr bit chn dy thanh ghi RSO, RS1 dng xc nh dy thanh ghi tch cc.
Cc bit ny c xa sau khi c thao t.c reset h thng v di mc logic bi phn
mm khi cn. Th d ba lnh sau cho php dy thanh ghi 3 ( banjc 3 ) tch cc, sau
di chuyn ni dung ca R7 ( a chi byte 1FH ) vo thanh cha A :
SETB RS1
SETB RSO
MOV A, R7
'
Khi on chng trnh trn c dch, cc a ch bit. s thay th
/ cho cc k hiu RSO v RS1, vy th lnh SETB RS1 tng ng vi / lnh SETB
0D4H.

Chng 2 : Tm tt phn cng

C trn
C trn ov ( overflow flag ) c set bng 1 sau php ton cng hoc tr nu c
xut hin mt trn s hc. Khi cc s c du c cng hoc c tr, phn mm c
th'kim tra bit. trn ov xc nh xem kt qu c nm trong tm hay khng.
Vi php cng cc s khng du, c trn ov c b qua. Kt qu ln hn +128
hoc nh hn -127 s set c ov bng 1. Th d php cng sau y gy ra 1 trn
v
set c ov
trong PSW :
S hex :

OF

S thp phn :

15

+ ZE

+127

8E

142

8EH biu din s m -116. nh vy khng ng vi kt, qu mong mun l 142 nn

c ov c set bng 1.
C chn l
Bit chn l p t ng c set. bng 1 hay xa bng 0 mi chu k my thit
lp kim tra chn cho thanh cha A. S cc bit. 1 trong thanh cha cng vi bit p lun
lun l s chan. Th d nu thanh clia c ni dung 10101101B, bit. p s l 1 c s
bit, 1 l 6. Bit. chn l c s dng nhiu kt hp vi cc chng trnh xut/nhp
ni tip trc khi truyn d liu hoe kim tra chan le sau khi nhn d liu.
2.5.2 Thanh ghi B
Thanh ghi B a chi F0H c dng chung vi thanh cha A trong cc php ton
nhn, chia. Lnh ML AB nhn 2 s 8-bit, khng au cha trong A v B v cha kt
qua 16-bit vo cp thanh ghi B:A ( thanh cha A ct byte thp v thanh ghi B ct byte
cao ).
Lnh chia DIV AB chia A bi B. thng s ct trong thanh cha A v d s ct
trong t.lianh ghi B. Thanh ghi B cn c x l nh 1 thanh ghi nhp. Cc bit c
nh a ch ca thanh ghi B c a chi t, F0H n F7H.
2.5.3 Con tr stack
Con tr stack SP ( stack pointer ) l 1 thanh ghi 8-bit. a ch 81H. SP cha ch
ca d lieu bin ang nh ca stack. Cc lnh lin quan n stack bao gm lnh ct,
d liu vo stack valnh ly d liu ra khi stack. Vic ct vo stack lm tng SP trc
khi ghi d liu v vic y d liu ra khni.stac? s-gam SP. Vng stack cua 8051
c gi trong RAM ni v c gii hn n cc a chi truy xut c bi kiu nh

1132

H vi iu khin 8051

a ch gin tip. Vng RAM ni c 128 byte trn 8031/8051 hoc 256 byte trn
8032/8052; nu ta khi ng SP bt u vng stack a ch 60H bng lnh :
MOV SP, #5FH
vng stack c gii hn l 32 byte trn 8031/8051 v a ch cao nht ca RAM trn
chip l 7FH. Gi tr 5FH c dng y v SP tng ln 60H trc khi thao tc ct vo
stack u tin c thc thi.
Nu ta khng khi ng SP, ni dung mc nh ca thanh ghi ny l 07H nhm duy
tr s tng thch vi 8048, b vi iu khin tin nhim ca 8051. Kt qu l thao tc
ct vo stack u tin s lu d liu vo v tr nh c a ch 08H. Nh vy nu phn
mm ng dng khng khi ng SP, dy thanh ghi 1 ( v c l 2 v '3 ) khng cn hp
l v vng ny c s dng lm stack. Cc lnh PUSH v POP s ct d liu vo stack
v ly d liu t stack, cc lnh gi chng trnh con ( ACALL, LCALL ) v lnh tr
v ( RET, RETI ) cng ct v phc hi ni dung ca b m chng trnh PC ( program
counter ).
2.5.4 Con tr d liu DPTR
Con tr d liu DPTR ( data pointer ) c dng truy xut b nh chng trnh
ngoi hoc b nh d liu ngoi. DPTR l 1 thanh ghi 16- bit c a ch l 82H ( DPL,
byte thp ) v 83H ( DPH, byte cao ). Ba lnh sau y ghi 55H vo RAM ngoi a
cii 1000H :
MOV A, #55H ' 1
MOV DPTR, #1000H
MOV @DPTR, A
Lnh u tin s dng kiu nh a ch tc thi nap hng d liu 55H
vfl_thanh cha A. Lnh th hai cng s dng kiu nh a ch tc thi, ln ny np
hng a ch 16-bit 1000H cho con tr d liu DPTR. Lnh th ba s dng kiu nh
a ch gin tip di chuyn gi tr 55H cha trong thanh cha A n RAM ngoi ti a
ch cha trong DPTR ( 1000H).
'~"
2.5.5 Cc thanh ghi port
Cc port xut nhp ca 8051 bao gm port 0 tai a ch 80H, port 1 ti a ch 90H,
port 2 ti a ch AOH v port 3 ti a ch BOH. Cc port 0, 2 v 3 khng c dng
xut/nhp nu ta s dng thm b nh ngoi hoc nu c mt s' c tnh c bit
ca 8051 c s dng ( nh l ngt, port ni tip, ... ). P1.2 n P1.7, ngc li, lun
lun l cc ng xut/nhp a mc ch hp l.
Tt c port u c inh ia ch tng hit, nhm cung cp cc kh nng giao tip
manh. Th d ta c mt ng c ni qua mt cun dy v "iH mch kch ng
transistor ni ti bit 7 ca port 1, ng c c th ngng hay chy ch nh vo mt lnh
n ca 8051 :
SETB P1.7 lm ng c

Chng 2 : Tm tt phn cng

chy v
CLR Pl.7 lm ng c
ngng.
Cc lnh trn s dng ton t . ( dot ) nh a ch 1 bit trong 1 byte, cho php
nh a ch tng bit.
Trnh dch hp ng thc hin bin i dng k hiu thnh a ch thc t, ngha l
hai lnh sau tng ng :
CLR P1.7
CLR 97H
Vic s dng cc k hiu c nh ngha trc ( tin nh ngha ) ca trnh dch
hp ng s c tho lun chi tit trong cc ti liu v lp trnh hp ng trn h MCS51 hoc chng 7.
Th d sau y kho st vic giao tip vi 1 thit b c bit trng thi gi l BUSY,
bit ny c set bng 1 khi thit b ang bn v c xa khi thit b sn sng. Nu
BUSY c ni vi bit 5 ca Port 1, vng lp sau y c dng ch cho n khi
thit b sn sng :
WAIT: JB P1.5, WAIT
Lnh trn c ngha l nu bit P1.5 c set, nhy n nhn WAIT ( cng c ngha l
nhy v v kim tra ln na ).
2.5.6 Cc thanh ghi nh thi
8051 e 2 b m/nh thi ( timer/counter ) 16-bit nh cc khong thi gian
hoc m cc s kin. B nh thi 0 c a ch 8H ( TLO, byte thp ) v 8CH
( THO, byte cao ); b nh thi 1 c a ch 8BH ( TL1, byte thp ) v 8DH ( THI, byte
cao ).
Hot ng ca b nh thi c thit lp bi thanh ghi ch nh thi TMOD (
timer mode register ) ia ch 89H v thanh ghi iu khin nh thi TCON ( timer
control register ) a ch 88H. Ch c TCON c nh a ch tng bit. '
Cc b nh thi s c tho lun chi tit sau.
2.5.7 Cc thanh ghi ca porljii-fci#p
Bn trong 8051 c mt port ni tip truyn thng vi cc thit b ni tip nh
cc thit b u cui hoc modem, hoc giao tip vi cc IC khc c mch giao tip
ni tip ( nh cc thanh ghi dch chng hn ). Mt thanh ghi c gi l b m d liu
ni tip SBUF ( serial data buffer ) a ch 99H lu gi d liu truyn i v d liu
nhn v. Vic ghi ln SBUF s np d liu truyn v vic c SBUF s ly d liu
nhn c.
Cc ch hot ng khc nhau c lp trnh thng qua thanh ghi iu khin port
ni tip SCON ( serial port control register ) a chi 98H, thanh ghi ny c

H vi iu khin 8051

cfinhTciia clii tng bit..

Hot ng chi t.it ca port ni t.ip s m t sau.
2.5.8 Cc thanh ghi ngt
8051 c mt cu trc ngt vi 2 mc u tin v 5 nguyn nhn ngt..
( 5 source, 2 priority level interrupt structure ). Cc ngt, b v hiu ha sau khi reset h
thng v sau c cho php bng cch ghi vo thanh ghi cho php ngt IE (
interrupt enable register ) a ch A8H. Mc u tin ngt c thit lp qua thanh ghi
lu tin ngt IP ( interrupt priority register ) a ch B8H. C 2 thanh ghi ny u c
nh a ch tng bit.
Cc ngt s c cp chi tit sau.
2.5.9 Thanh ghi iu khin ngun
Tlninh ghi iu khin ngun PCON ( power control register ) c a
('111 87H cha cc bit. iu khin c tm tt trong bung 2.4.

Bit SMOD tng gp i tc baud cua port ni tip khi port ny lio;it ng cc
ch 1. 2 hoc 3. Cc bit 4. 5 v () CIK1 PCON khng c nh ngha. Cc bit. 2 v
3 l cc bit c da niU' dch dnh cho cc ng dng cua ngi s dng.
\Cc bit iu khin ngun, nguii giam PD v nghi IDL, hp l trong tt ra'eAip
thuc h MCS-51, nhng ch c hin thc trong cc phin ban CMOS ca MCS-51.
PCON khng c nh a ch bit,.
Ch ngun gim
Lnh thit lp bit PD bng 1 s l lnh sau cng c thc thi trc khi i vo ch
ngun gim. ch ngun gim :
(1) mch dao ng trn chip ngng hot ng

Chng 2 : Tm tt phn cng

35 g

(2) mi chc nng ngng hot ng

(3) ni dung ca RAM trn chip c duy tr
(4) cc chn port duy tr mc logic ca chng
(5)
ALE v PSHN 'c gi mc thp. Ch ra khi ch ny bng
cch reset h thng.
Trong sut thi gian ch ngun gim, Vcc c in p l 2V. Cn phi gi cho
Vcc khng thp hn sau khi t c ch ngun gim v cn phc hi Vcc = 5V
ti thiu 10 chu k dao ng trc khi chn RST t mc thp ln na.
Bit,
7

K hiu M t
SMOD
tng gp i tc baud, bit ny khi set lm cho
tc baud tng 2 cc ch 1, 2 v 3 ca port ni tip

Khng nh ngha

Khng nh ngha

Khng nh ngha

GF1

Bit c' a mc ch 1

GFO
PD

Bit c' a mc ch 2
Ngun gim; thit lp tch cc ch ngun gi 111,
ch ra khi ch bng reset.

1
Q

IDL

Ch ngh; thit lp tch cc ch ngh, ch 1-a

khi ch bng 1 ngt hoc reset h thng.

Bng 2.4 : Thanh ghi PCON
Ch ngh
Lnh thit lp bit IDL bng 1 s l lnh sau cng c thc thi tc khi i vo ch
ngh, ch ngh,'tn hiu clock ni c kha khohg cho n CPU nhng
khng kha i vi cc chc nng ngt, nh thi v port ni tip. Trng thi cua
CPU c duy tr v ni dung nia tt. c cc thanh ghi cng c gi khng i.
Cc chn port, cng c duy tr cc mc logic ca chng. ALE v HSliN c gi
mc cao.
Ch ngh kt. thc bng cch cho php ngt, hoc bng cch reset h thng. C
hai cch va nu u xa bit IDL.

S) 36

H vi iu khin 8051

2.6 B NH NGOI
Cc b vi iu khin cn c kh nng m rng cc ti nguyn trn chip ( b nh,
I/O, v.v... trnh hin tng c chai trong thit k. Cu trc ca MCS-51 cho ta kh
nng m rng khng gian b nh chng trnh n 64K v khng gian b nh d liu
n 64K. ROM v RAM
Iigoi c thm vo khi' cn.

Cc IC giao tip ngoi vi cng c th c thm vo m rng kh nng

xu't/nhp. Chng tr thnh 1 phn ca khng gian b nh d liu ngoi bng cch s
dng cch nh a ch kiu I/O nh x b nh. Khi b nh ngoi c s dng, port 0
khng lm nhim v ca port xut/nhp, port ny tr thnh bus a ch ( AO - A7 ) v
bus d liu ( DO
- D7 ) a hp. Ng ra ALE cht byte thp ca a ch thi im bt u mi mt chu
k b nh ngoi. Port 2 thng ( nhng khng phi lun lun ) c dng lm byte cao
ca bus a ch.
Trc khi tho lun cc chi tit c th v cc bus a ch v d liu a hp, tng
tng qut c trnh by hnh 2.7.
- Memory cycle -

A0-A15

D0-D7

Address

Data

(a) Nonniultiplexed (24 pins)

-Memory cycle AddTess

A8-A15

Address

Data

lb) Multiplexed (10 pins)

Hnh 2.7\: a hp bus a ch ( byte thp ) v bus d liu (a) khng a hp ( 24

chn ) (b) a hp ( 16 chn )
Memory cycle : chu k b nh
Address : a ch Data : d liu
Nonmultiplexed : khng a hp
Multiplexed : a hp

Chng 2 : Tm tt phn cng

37 g

Sp xp khng a hp s dng 16 ng a chi v 8 ng d liu, tng cng

24 ng, sp xp a hp kt hp 8 ng cua bus d liu v byte thp ca bus a
chi, do vy t.a chi cn 16 ng.
Vic tit kim cc chn cho php t,a ng gi b vi iu khin h MCS-51
trong 1 v 40 chn.
Sp xp a hp c hot, ng nh sau : trong Vi chu k u ca chu k b nh,
byt.e thp ca a chi c cung cp bi port 0 v c cht nh till hiu ALE.
Mch cht 74HC373 gi cho byte thp ca a chi 011. nh trong c chu k b
nh. Trong V sau ca chu k b nh, port 0 c s dng lm bus d liu v d
liu c c hay ghi.
2.6.1 Truy xut b nh chng trnh ngoi
B nh chng trnh ngoi l b nh ch c, c cho php bi till hiu
PSIN. Khi c 1 EPROM ngoi c s dng, c hai port 0 v port 2 u khng
cn l cc port xut/nhp.
2.8.

Kt ni phn cng vi b nh Iigoi EPROM c trnh by hnh

Hnh 2.8 : Truy xut b nh chng trnh ngoi

Mt chu k my ca 8051 c lg chu k dao ng. Nu b dao ng trn chip c
tn s 12 MHz, mt chu k my di 1 (J.S. Trong 1 chu k my in hnh, ALE c 2
xung v 2 byte ca lnh c c t b nh chng trnh ( riu lnh ch c 1 byte,
byte th hai c loi b ). Gin thi gian ca chu k my ny, c gi l chu

S) 38

k tm-np nh c trnh by d hnh 2.9.

H vi iu khin 8051

H vi iu khin 8051

ALE

PSEN

"^PCH (Program counter high byte)^

Port 2

Port

PCH

T---------------------1---- I-----------------------r
I
I
i
I
I.1.__________________________________I
i
I
|__

__________________________________I

Hnh 2.9 : Gin d thi gian ca chu k tm-np lnh b nh ngoi

One machine cycle : mt chu k my Program

counter high byte : byte cao ca PC
2.6.2 Truy xut b nh d liu ngoi
B nh d liu ngoi l b nh c/ghi c cho php bi cc tn hiu RD v
WR cc chn P3.7 v P3.6. Lnh dng truy xu't b nh d liu ngoi l
MOVX, s dng hoc con tr d liu 16-bit DPTR hoc RO, RI lm thanh ghi cha
a ch.
RAM c th giao tip vi 8051 theo cng cch nh EPROM ngoi tr ng RD
ni vi ng cho php xut ( OE ) ca RAM v WR ni vi ng ghi (w) ca
RAM. Cc kt ni vi bus d liu v bus a ch ging nh EPROM. Bng cch s
dng cc port 0 v port 2 nh phn c 1 dung lng RAM ngoi ln n 64-Kc kt ni vi 8051.

thi gian ca thao tc c d liu b nh d liu ngoi c trnh by

hnh 2.10 cho lnh MOVX- A, @DPTR. Lu l ca_2^ xung ALE^r PSRN drtr
hn qua n' m xung RT nho php (nr RAMJ _nu lnh MOVX v RAM ngoi
khng bao gi c dng, cc xung ALE lun c tn s' bn^ 1/6 tn s ca mch dao
ng ].
Gin thi gian ca chu k ghi ( lnh MOVX @DPTR, A ) cng tng t
ngoi tr cc xung WR mc thp v d liu c xut ra port 0 (RD vn mc
cao ).

 UiH' madimc cyuli'

Om* machine cycle

SI S2 S3 S4 S5 S6 SI S2 S3 S4 S5 S6

Port 0

Hnh 2.10 : Gin thi gian ca lnh MOVX

One machine cycle : mt chu k my Data pointer
high byte : byte cao ca DPTR External data in :
nhp d liu t b nh ngoi Opcode : m thao
tc

S) 40

H vi iu khin 8051

Port, 2 gim bt c chc nang lm nhim v cung cp byte cao ca a chi

t.rong cc h thng ti t.hiu thnh phn, h thiig khng dng b nh chng trnh
ngoi
v eln c 1 dung lng nho b nh
d liu
ngoi. Cc a ch 8 bit c
th truy xut, b nh d liu ngoi
vi cu
hnh b nh nh hng trang ( page-orient.e ). Nu c nhiu hoi 1 trang 256-byte
RAM, 1 vi bit t port 2 ( hoc 1 port khc ) c th chn
1 trang. Th d vi 1 RAM1KB f ngh~7er trang 256 byte~)7t,a c
th
kTloi RAM ny vi 8051 nh hnh 2.11.
Cc bit 0 v 1 ca port 2 phi c khi ng chn 1 trang, ri lnh MOVX
c dng c hoc ghi trn trang ny. Tli d ta gi s P2.0 = P2.1 = 0, cc lnh
sau c th dng c cc ni dung ca RAM ugoi da ch 0050H vo thanh
cha A :
MOV RO, #50H
MOVX A, @R0
dc a ch CU1 cng ca RAM ny, 03FFH, trang 3 c chn ngha l
ta phi set cho cc bit P2.0 v P2.1 bng 1. Chui lnh sau c dng :
SETB P2.0
SETB P2.1
MOV RO,
#0FFH MOVX
A, @R0
Mt c trng ca thit k ny l cc bit t 2 n 7 ca port 2 khng na, cc
bit cn li ny c th s dng cho mc

Nu c nhiu EPROM hoc nhiu RAM hoc c 2 gio tip vi 8051 ta cn

phi gii m a chi. Vic gii m ny cng cn cho hu ht cc b vi x l.
^^JThj nu cc RAM v ROM 8 KB c s dng, a ch phi dc gii m
chn cc IC nh ny trn cc gii hn 8 K : 0000H - 1FFFH, 2000H - 3FFFH, ...
Mt IC gii m in hnh l 74HC138 c dng vi cc Iig ra c ni
vi cc ng vo chn chip cs ca cc IC nh nh c m t hnh 2.12 cho mt
b nh c nhiu EPROM 2764 ( 8K ) v RAM 6264 ( 8K ). Cn lu l do cc
ng cho php ring r (PSN cho b nh

Chng 2 : Tm tt phn cng

chng trnh, RD v WR cho b nh d liu ), 8051 c th qun l khng gian nh n

64K cho b nh EPROM v 64K cho b nh RAM.

Hnh 2.12 : Gii m a ch

2.6.4 Cc khng gian nh chng trnh v d liu gi nhau
V b nh chng trnh l b nh ch c, mt tnh hung kh x c pht sinh
trong qu trnh pht trin phn mm cho 8051. Lm th no phn mm c vit cho
mt h thng ch g r nu phn mYi ch c th c thc thi t khng gian b
nh chng trnh chi c.
Gii php tng qut l cho cc khng gian b nh chng trnh v d liu ngoi gi
ln nhau. V PSHN c dng c b nh chng trnh v RD c dng c b
nh d liu, mt RAM c th chim khng gian nh chng trnh v d liu bng cch
ni chn OE ti ng ra cng AND c cc ng vo l PSEN v RD .
Mch trnh by hnh 2.13 cho php IC RAM c ghi nh l b nh d liu v
c c nh l b nh chng trnh hoc d liu. Vy th mt chng trnh c th
c np vo RAM ( bng cch ghi vo

42

H vi iu khin 8051

RAM nh l b nh d liu ) v c thc thi (bng cch truy xut nh b nh chng trnh
).

PSEN

Hnh 2.13 : Gi 2 khng gin nh chng trnh v d liu

2.7 CC CI TIN CA 8032 / 8052

- Cc vi mch 8032 / 8052 ( v cc phin bn CMOS ) c hai cai tin so vi
8031/8051. Mt l c thm 128 byte RAM trn chip t. a ch 80H n FFH. iu
ny khng xung t vi cc thanh ghi chc nng c bit ( c cng a ch ) v 128
byte RAM thm vo ch c th truy xut bng cch dng kiu nh a ch gin tip.
Mt lnh nh sau :
MOV A, 0F0H
di chuyn ni dung ca thanh ghi B ti thanh cha A trn cc IC cua h MCS-51.
Chui lnh :
MOV RO, #0F0H
MOV A, @R0
c vo thanh ghi A ni dung ti a chi F0H t.rn cc IC 8032/8052 nhng khng
c nh ngha trn 8031/8051. T chc b Iih ni ca 8032/8052 c tm tt
hnh 2.14.
mi Accessible* hy IiuiirmAccessible bv direct, FF
II
addressing only
addressing only
Upper

128
bvtes

80
H

Accessible bv direct _____Special

7FH

and indirect

function

addressing

registers

Lower

128

80
H

byt.es

00
H

Hnh 2.14 : Khng gian nh ni ca 8032/8052

Chng 2 : Tm tt phn cng

43 g

S) 44

H vi iu khin 8051

Upper 128 bytes : 128 byte trn

Lower 128 bytes : 128 byte
di
Accessible by indirect addressing only : ch c truy xut bng kiu nh a ch
gin tip
Accessible by direct addressing only : ch c truy xut bng kiu nh a ch
trc tip
Accessible by direct and indirect addressing : truy xut bng kiu nh a
ch trc tip v gin tip
Thanh ghi
a ch
M t
a ch bit
T2CON
C8H
iu khin
C
RCAP2L

CAH

Nhn byte thp

RCAP2H
CBH
Nhn byte cao
TL2
CCH
Byte thp ca b nh thi 2
TH2
CDH
Byte cao ca b nh thi 2
Bng 2.5 : Cc thanh ghi ca b nh thi 2

Khng
Khng
Khng
Khng

Ci tin th 2 l c thm b nh thi 16-bit. B nh thi 2 ny c lp

trnh nh vo 5 thanh ghi chc nng c bit thm vo. Chng c tm tt trong
bng 2.5 v s c m t chi tit sau trong chng 4 ( hot ng nh thi ).
2.8 HOT NG RESET
8051 c reset bng cch gi chn RST mc cao ti thiu 2 chu k my
v sau chuyn v mc thp. RST c th c tac ng bng tay hoc c tc
ng khi cp ngun bng cch dng mt mch RC nh c trnh by hnh 2.15.
Trng thi ca tt c cc thanh ghi sau khi reset h thng c tm tt trong bng
2.6.
Quan trng nht trong cc thanh ghi ny c l l thanh ghi PC ( b m
chng trnh ), c np 0000H. Khi RST tr li mc thp, vic thc thi chng
trnh lun lun bt u v tr u tin trong b nh chng trnh: a ch 0000H.
Ni dung ca RAM trn chp khng b nh hng bi hat""ng reset.
Thanh ghi

Ni dung

B m chng trnh

0000H

Thanh cha A

00H

Thanh ghi B

00H

PSW

00H

Chng 2 : Tm tt phn cng

SP
DPTR Port 0-3 IP
IE
Cc thanh ghi nh thi
SCON
SBUF
PC ON ( HMOS )
PC ON ( CMOS ) 07H
0000H
FFH
xxxOOOOOB
( 8031/8051 )
xxOOOOOOB
( 8032/8052 )
OxxOOOOOB
( 8031/8051 )
OxOOOOOOB
( 8032/8052 )
OOH
OOH
OOH
OxxxxxxxB
OxxxOOOOB

45 g

S) 46

H vi iu khin 8051

+5 V

+5 V

RST

lai Mann-l 1'-OHt +5

V

== Of.iF

Bng 2.6 : Gi tr ca cc thanh ghi sau khi reset h thng

RST

2K

1 b > Power-on reset

Hnh 2.15 : Hai mch dng reset h thng (a) reset bng tay (b) reset khi cp
ngun
Reset : nt nht reset Manual reset : reset bng tay Power-on reset : reset khi cp
ngun