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Hoạt Động Định Thời: set bằng 1 bởi tầng cuôi của bộ định thời. Giản đồ thời gian ở hình 4.1.b cho thấy tầng
Hoạt Động Định Thời: set bằng 1 bởi tầng cuôi của bộ định thời. Giản đồ thời gian ở hình 4.1.b cho thấy tầng
HOT NG NH THI
4.1 M U
Ni dung ca chng ny kho st cc b nh thi ( timer ) ca chip 8051. Ta hy
bt u t quan im n gin v cc b nh thi thng c s dng cho cc b vi
x l hoc cc b vi iu khin.
Mt b nh thi l mt chui cc flipflnp vi mi flipflop l mt mch chia 2,
chui ny nhn mt tn hiu ng vo lm ngun xung clock. Xung clock t vo
flipflop th nht, flipflop ny chia i tn s xung clock. Ng ra ca flipflop th nht
tr thnh ngun xung clock cho flipflop th hai, ngun xung clock ny cng c chia
cho 2, v.v... V mi mt tng k tip nhau u chia cho 2 nn mt b nh thi c n tng
s chia tn s xung clock ng vo ca b ny cho 2n.
Ng ra ca tng cui cng lm xung clock cho mt flipflop bo trn b inh thi
hay cn goi l c trn ( overflow flag ), c trn ny c kim txa_bi_phn mm hoc
to ra mt ngt. Gi tr nh phn trong cac flipflop ca b nh thi l s" m ca cc
xung clock t khi b nh thi bt u m. Th d mt b nh thi 16-bit s m t
0000H n pFFFH. C trn c set bng 1 khi xy ra trn s m t FFFFH xung
0000H.
Hot ng ca mt b nh thi n gin c minh ha trong hnh 4.1, b nh
thi 3-bit. Mi mt tng l mt D.FF kch khi cnh m hot ng nh mt mch chia
cho 2 do ta ni ng ra Q vi ng vo D. Flipflop c n gin l mt mch cht D c
set bng 1 bi tng cui ca b nh thi. Gin thi gian hnh 4.1.b cho thy tng
th nht (Qo) chia 2 tn s xung clock, tng th hai chia 4 tn s' xung clock v v.v...
S" m ( count ) c ghi dng thp phn v c kim tra d dng bng cch kho
st trng thi ca 3 liplop. Th d s' m l 4 xut hin khi Q 2 = 1, Qi = 0 v Qo = 0 (
4io = 1002 ). Cc liplop hnh
4.1 l cc flipflop tc ng cnh m ( ngha l ng ra Q ca cc flipflop i trng thi
theo cnh m ca xung clock ). Khi s" m trn t 11 la
i66
nh thi trong
(b)
m s kin.
(c)
To tc baud
8051.
LSB
MSB
"Fla g
Clock
BTI
Qo(LSB)
QI
i
!, (MSB7|_
'
Q:
Count
3i4
5I6
7I0
Flag
Hnh 4.1 : Mt b nh thi 3-bit (a) s logic (b) gin thi gian
Timer flipflops : cc flipflop nh thi
Flag flipflop : flipflop c Count : s
m
Flag is set on 7-to-0 timer overflow : c' c set khi C trail b nh thi ( s m trn
t 7 xung 0 )
Vi b nh thi 16-bit, tng cui cng ( tng th 16 ) chia tn s 'ung clock
ng vo ca b nh thi cho 2 - 655^6.
67 g)
Mc ch
a
ch
nh a
chi bit
TCON
iu khin
88H
TMOD
Chn ch
89H
Khng
TLO
8AH
Khng
TL1
8BH
Khng
THO THI
8CH
8DH
Khng
Khng
T2CON
iu khin b nh thi 2
C8H
RCAP2L
CAH
Khng
RCAP2H
TL2
CBH
CCH
Khng
Khng
TH2
CDH
Khng
nh thi
H vi iu khin 1951
phn mm thi im bt u ca mt chng trnh khi ng ch hot ng
ca b nh thi. Sau , b nh thi c th c dng, bt u, v.v... bng cch truy
xut cc thanh ghi chc nng c bit khc ca b inh thi.
Bit
7
Tn
GATE
B nh thi M t
1
Bit iu khin cng. Khi dc set ln 1,
b nh thi ch hot ng trong khi
NT1 mc cao.
C/T
MI
MO
GATE
C/T
MI
MO
MI
MO
Ch
M t
Ch d
Ch
Ch
Ch d
B dnh thi 0 : TLO l mt b nh thi 8-bit dc iu
khin bi cc bit chn ch ca b nh thi 0. THO,
tng t TLO ch khc l c iu khin bi cc bit chn
ch ca b nh thi 1.
B nh thi 1 : dng, khng hot ng.
Bng 4.3 : Cc ch nh thi
9 (S3
TF1
8FH
v/
TCON.5
TF0
8DH
TCON.4
TRO
8CH
TCON.3 IE1
TCON.2 IT1
8BH
8AH
C trn ca b nh thi 0
Bit diu khin hot dng ca b nh thi 0.
C ngt bn ngoi 1 ( kch khi cnh ). C' ny
c set bi phn cng khi c canh m ( xung )
xut hin trn chn 1NT1. c xa bi phn
mm, hoc phn cng khi CPU tr n trinS phc
v ngt.
C ngt bn ngoi 1 ( kch khi cnh hoc mc ).
C ny dc set hoc xa bi phn mm khi xy
ra cnh m ( xung ) hoc mc thp ti chn
ngtngoi.
VTCON.1
IEO
89H
TCON.O
C ngt bn
ITO
88H
IS 70
H vi iu khin 8051
TLx
clock
(5 bit.s)
THx
TFx
(8 bits)
Overflow
flag
UI) Mode 0
Timei*
clock
Overflow
flag
,t I
clock
Timer
(a) Mode 1
(a)
Mode 2
TLx
Timer
clock
Tilx
Overflow
flag
Timer
clock
/
12F.
Overflow
flag
(aJ Mode 3
0, 1, 2, 3 Reload : np li
1/12
71 g)
/
Ch 2 l ch t np li 8-bit. B.yte th7p ca b inh thi ( TLx ) hoat, ng
nh thi 8-bit trong khi bv.e caq ca b nh thi lu gi gi tr np li. Khi s m trn
t FFH xung 00H, khng ch c trn ca b nh thi c set ln 1 m gi tr trong
THx cn c nap vo TLx ; vic m s tip tc t gi tr ny cho n khi xy ra 1 trn
( FFH > 00H ) k tip, v.v... Ch ny kh tin li do bi vic t.rn b nh thi xy
ra nhng khong thi gian xc nh v tun hon mt khi cc thanh ghi TMOD v THx
d c khi ng ( xem hnh 4.2c ).
IS 72
H vi iu khin 8051
4.5.2 m s kin
Nu C/T = 1, b nh thi c cung cp xung clock t 1 ngun to xung bn ngoi.
Trong a s cc ng dng, ngun xung clock ny cung 'cp cho b nh thi mt xung
da trn vic xy ra mt s kin - b nh thi by gi m s kin. S cc s kin c
xc nh trong phn mm bng cch c cac~tKnh ghi nh thi ( TLx / THx X gi tr
16-bit trong cc thanh ghi ny tng theo mi s kin. Hai chn ca port 3 ( P3.4 v
P3.6 ) by gi tr thnh ng vo xung clock cho cc b nh thi. Chn P3.4 l ng vo
xung clock cho b nh thi 0 ( ta cn gi l chn TO ng cnh ny ), chn P3.5 hoc
TI l ng vo xung clock cho b nh thi 1 ( xem hnh 4.3 ).
73 g)
Hnh 4.3 : Ngun xung clock Crystal : tinh th thch anh On-chip oscillator : b dao
ng bn trong chip TO or TI pin : chn TO hoc TI
0 = Up ( interval timing ) : 0 = v tr trn ( nh thi mt khong thi gian )
1 = Down ( event counting ) : 1 = v tr di ( m s kin )
Timer clock : xung clock nh thi
Trong cc ng dng m s kin, cc thanh ghi nh thi tng mi khi xy ra chuyn
trang thi t. 1 xung 0 ng vo Tx ( TO hoc TI ). Ng vo Tx c ly mu trong
sut thi gian S5P2 ca mi mt chu k my, vy th khi ng vo mc cao trong mt
chu k v mc thp trong chu kv k. s m c tng. Gi tr mi xut hin trong cc
thanh ghi nh thi trong sut thi gian S3P1 ca chu k tip theo chu k pht hin s
chuyn trng thi. T ta thy phi mt 2 chu k my ( 2|.IS ) nhn bit s chuyn
trang thi t 1 xung 0. tn s cc i cua ngun xung clock bn ngoi l 500 KHz ( vi
gi s chip vi iu khin Hot d0rig~v3i thch anh 12 MHz X
IS 74
H vi iu khin 8051
Hnh 4.4 : Bt u v dng cc b nh thri Timer clock : xung clock dnh thi Timer
registers : cc thanh ghi nh thi
0 = Up ( timer stopped ) : 0 = v tr trn ( b nh thi dng )
1 = Down ( timer started ) : 1 = v tr di ( b nh thi c khi ng )
Th d b nh thi 0 c khi ng bng lnh :
SETB TRO
jg.-r-----------------------------------------------------
IS 76
H vi iu khin 8051
; dng b nh thi
CLR TF1
; xa c' trn
dng
ta
cn
cgi
tr ( ni dung ) cha
trong cc thanh ghi nh thi ang hot ng.
phi
Do ta phi c 2 thanh ghi nh thi bng 2 dng lnh lin tip ( do khng c lnh
c ng thi c hai thanh ghi nh thi ny ), mt sai pha ( phase error ) c th xut
hin nu c trn i-byte thp chuven sang bvte cao-gia 2 lrTc v do^vy ta khng
th c ng c gi tr cn c. Gii php a ra l trc tin ta phi c byte cao, k
n .c byt thp v ri c byte cao ln na. Nu byte cao thay i gi tr, ta lp li
cc thao tc c va nu. Cc lnh sau y c ni dung ca cc thanh ghi nh thi TL1
/ THI, a vo cc thanh ghi R6 / R7 v gii quyt vn va nu :
AGAIN :
MOV A, THI
MOV R6, TL1 '
CJNE A, THI, AGAIN
MOV R7, A
77 g)
tn s' 1 MHz. Khong thi gian ngn nht c th nh thi c b gii hn khng
phi bi tn s ca xung clock nh thi m bi phn mm ngha l thi gian thc thi cc
lnh to ra gii hn i vi cc khong thi gian nh thi rt ngn. Lnh ngn nht ca
8051 thc hin trong mt chu k my hay 1 0.S. Bng 4.5 tm tt cc k thut c
dng o ra cc khang thi
gian nh
thi khc nhau.
K thut
iu chnh phn mm 'S'
10
256
65536
khng gii hn
SETB Pl.o
; 1 chu k my
CLR Pl.o
; 1 chu k my
SJMP LOOP
; 2 chu k my
END
Chng trnh trn to ra dng xung trn chn Pl.o, xung c chu k l 4 (J.S : thi gian
mc cao l 1 (J.S v thi gian mc thp l 3 (J.S trong mt chu k. Tn s ca xung l 250
KHz v chu k nhim v l 25% (xem hnh 4.6)
I-*-----------------4ns --------------------*-1
|SETB Pl.o CLR Pl.o I SJMP loop SETB Pl.o etc.
Pl.o
i78
Lnh SETB Pl.o thc t khng st bit 0 ca port 1 ln 1 cho n khi kt thc lnh
ny, trong thi gian S6P2, v cc lnh tip theo cng tng t. Chu k ca tn hiu ng
ra c th ko di thm mt t bng cch chn cc lnh NOP ( khng ton hng ) vo trong
vng lp. Mi lnh NOP c chn thm lm cho chu kv ca tn hiu ng ra c cng
tin 1 sT Th diTeTta chn 2 lnh NOP sau lnh SETB Pl.o, chng tfh s to
ng ra mt xung vung c chu k 6 ns v tn s l 166.7 KHz. Tuy vy ta cn thy rng
vic iu chnh phn mm nh trn s tr nn cng knh v vng v, cch la chn tt
nht tr hon vn l s dng b nh thi.
Cc khong thi gian di va phi d dng nhn c bng cch s dng ch t
np li 8-bt, ch 2. Do cc khong thi gian cn c nh thi c thit lp bi
mt s m 8-bit, khong thi gian di nht c th c trc khi trn l 2H = 256 (.LS.
Th d 4.2 : Sng vung 10 KHz
Vit 1 chng trnh to sng vung 10 KHz trn chn Pl.o bng cch s dng b
nh thi 0.
Sng vung 10 KHz yu cu chu k 100 ns vi thi gian mc cao l 50 ns v thi
gian mc thp l 50 ^s. Do khong thi gian ny nh hn 256 ns nn ch 2 c s
dng. Mt trn xy ra sau mi 50 ns yu cu mt gi tr s m nh hn 00H mt lng
l +50 phi c np v np li cho TL0, ngha l gi tr np cho THO l -50. Di y
l chng trnh theo yu cu :
ORG
8100H
MOV
TMOD, #02H
; ch t np li 8-bit
MOV
THO, #-50H
SETB
TRO
TF0, LOOP
; ch trn 1
CLR
TF0
; xa c trn
CPL
Pl.o
LOOP: JNB
SJMP
LOOP
; lp li
END
Chng trnh trn s dng lnh ly b bit CPL thay v l lnh STB v CLR nh
trong th d 4.1. Gia hai thao tc ly b c mt tr hon
Bit
K hiu
a ch bit
T2CON.7
TF2
CFH
T2CON.6
EXF2 CEH
T2CON.4
T2CON.3
T2CON.2
RCLK CDH
TCLK CCH
EXEN2 CBH
TR2
CAH
CP/RL2C C8H
M t
84
H vi iu khin 8051
4.10 TO TC BAUD
Mt ng dng khc ca b nh thi l cung cp xung clock tc baud cho port
ni tip ca chip vi iu khin. B nh thi 1 8051 hor b inh thi 1 Ja-44fhhrif4~2_L-8Q52 thc hin c cng vic ny. To tc baud s cp n trong
chng 5.
Trong chng ny ta kho st cc b nh thi ca cc b vi iu khin 8051 v
8052. Cc gii php phn mm cho cc th d lm ni bt nt chung nhng b gii hn.
Cc gii php ny lm mt nhiu thi gian ca CPU. Cc chng trnh thc thi cc
vng lp ch b nh thi trn. iu ny tt cho c mc ch nghin cu hc hi
nhng di vi cc ng dng hng iu khin thc t s dng cc b vi iu khin,
CPU phi thc hin cc nhim v khc cng nh phi p ng vi cc s kin bn
ngoi ( nh l ngi iu khin a vo mt tham s t bn phm chng hn ). Trong
chng kho st hot ng ngt, ta s minh
On-chip
osc.
8052
12
TL2
12 MHz
0 = Up
1 - Down
Tl (P1.0)
C/T2
0 = Up
1 = Down
CaplmT
TR2
T2EX .
(Pl.l)
EXEN2
0 = Up
1 = Down
\7 \7
TH2
TF2
H vi iu khin 8051