:

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.
.
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.
Alpha 21164 MIPS R10000 .

:


.


load/store pipeline load/store
.

.

. .
.

) (Basic Block
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. pipeline .

Instruction Issueing

commit

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. pipeline cache
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.

.
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.
:

( (

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.

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pipeline .
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.

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pipeline .

pipeline
.
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Commit

.
out of order . .
:
:

)( checkpoints .

HistoryBuffer . . Commit
HistoryBuffer .

Record Buffer .
. . .

Record Buffer . Commit

Record Buffer Register File Store .
... Record Buffer .

IV
8086

8086

8086

RSIK 8086 CISC

.
8086 MB=2 20 .
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)Unit ) (Execution Unit .

BIU .
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EU . BIU 8086 .

U V .
Cache :
cache ) (Back writer
.
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pro . p6 X86
RISC .
, (-) -
X86 - . .
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SIMD )(packed operand.

 p6

CPU .

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p6 .
.
)(prooagation delay .

0.18 0.13 ( )

 p6

IP Branch Target
Buffer BHB Branch HistoryBits
integer .

.
.
.

.

 IV

IV p6
. 0.18
GH 1 . III

GHZ 1.13.
Hyper pipelining


netburst .

 IV

 NetBurst

Netburst p6
:

SSE2


.
.
:
branch Target Buffer p6 .
.

(

)
. SIMD .
IV SSE2 .

SSE2

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SSE2:

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) (packed
SIMD integer .

. XMM .

SSE2 . :
,
IEEE 46
.
.

.
.