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C S L THUYT MSP430
I. TNG QUAN V CU TRC V CHC NNG H MSP430
I.1. Gii thiu
MSP430 cha 16 bit RISC CPU, cc ngoi vi v h thng b nh thi linh hot c
kt ni vi nhau theo cu trc VON-NEUMANN, c cc Bus lin kt nh: Bus a ch b
nh ( MAB), Bus d liu b nh ( MDB). y l mt b x l hin i vi cc m un
b nh tng t v nhng kt ni ngoi vi tn hiu s, MSP430 a ra c nhng
gii php tt cho nhng nhu cu ng dng vi tn hiu hn tp.
MSP430 c mt s phin bn nh: MSP430x1xx, MSP430x2xx, MSP430x3xx,
MSP430x4xx, MSP430x5xx. Di y l nhng c im tng qut ca h vi iu khin
MSP430:
+ Cu trc s dng ngun thp gip ko di tui th ca Pin
- Duy tr 0.1A dng nui RAM.
- Ch 0.8A real- time clock.
- 250 A/ MIPS.
+ B tng t hiu sut cao cho cc php o chnh xc
- 12 bit hoc 10 bit ADC-200 kskp, cm bin nhit , Vref.
- 12 bit DAC.
- B gim st in p ngun.
+ 16 bit RISC CPU cho php c nhiu ng dng, th hin mt phn kch thc Code
lp trnh.
- Thanh ghi ln nn loi tr c trng hp tt nghn tp tin khi ang lm vic.
- Thit k nh gn lm gim lng tiu th in v gim gi thnh.
- Ti u ha cho nhng chng trnh ngn ng bc cao nh C, C++
- C 7 ch nh a ch.
- Kh nng ngt theo vc t ln.
+ Trong lp trnh cho b nh Flash cho php thay i Code mt cch linh hot, phm vi
rng, b nh Flash cn c th lu li nh nht k ca d liu.
I.2. H thng nh thi ( Clock) linh hot
H thng Clock c thit k mt cch c bit cho nhng ng dng s dng ngun
cung cp l Pin. Mt b to xung nhp ph tn s thp ( ACLK) c cung cp trc tip
t mt b dao ng thch anh 32 KHz. ACLK c s dng nh l mt Real-time Clock
nn kch hot cc tnh nng. Mt b dao ng k thut s tc cao ( DCO) c th
lm ngun xung ng h chnh ( MCLK) s dng cho CPU v nhng kt ni ngoi vi tc
cao. Bi thit k ny, DCO c th hot ng n nh 1MHz trong thi gian t hn 2
S. MSP430 c thit k da trn nhng gii php c hiu qu s dng mt RISC CPU
16 bt hiu sut cao.
+ B nh thi ph tn s thp: Hot ng ch sn sang s dng ngun cc thp.
+ B nh thi chnh ( Master Clock) tc cao: Hot ng x l tn hiu hiu sut cao.

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Hnh I.1: S cu trc ca MSP430

I.3. Cc vng a ch
MSP430 c thit k theo cu trc Von-Neumann c mt vng a ch c chia thnh
nhiu vng nh l thanh ghi hm c bit ( SFRs), nhng ngoi vi, RAM, b nh
Flash/ROM.

Hnh I.2: S b nh ca MSP430

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I.3.1. Flash/ROM
a ch bt u ca Flash/ROM ph thuc vo ln ca Flash/ROM v cn ty thuc
vo tng h vi iu khin. a ch kt thc ca Flash/ROM l 0x1FFFFh. Flash/ROM c
th s dng cho c m chng trnh v d liu. Nhng bng Byte hoc Word c th c
tn tr v s dng ngay trong Flash/ROM m khng cn copy vo RAM trc khi s
dng chng.
Nhng bng vc t c nh x n 16 Word pha trn ca vng a ch Flash/ROM vi
u tin ngt cao nht vng a ch cao nht ca Flash/ROM.
I.3.2. RAM
RAM bt u a ch 0200h v gii hn cui cng ty thuc vo kch thc ca RAM.
RAM c th s dng cho c m chng trnh v d liu.
I.3.3. Cc module ngoi vi
Trong vng khng gian a ch ca MSP430 c 2 vng a ch dnh cho nhng M un
ngoi vi. Vng a ch t 0100 n 01FFh s dng dnh ring cho nhng m un ngoi
vi 16 Bt. Vng a ch t 010 n 0FFh s dng dnh ring cho nhng m un ngoi vi
8 Bt.
I.3.4. Thanh ghi hm c bit
SFRs lin quan nhiu n s cho php nhng tnh nng ca mt s m un ngoi vi v
dng truyn nhng tn hiu ngt t ngoi vi. SFRs nm 16 Byte thp ca vng a
ch v c t chc bng Byte. SFRs ch c th c truy cp bi ch th Byte.
I.3.5. T chc b nh
Byte th dng nh v tr ca a ch l hoc chn, cn Word th ch s dng cho a ch
chn. V vy khi s dng nhng ch lnh T th ch c a ch chn th c s dng.
Byte thp ca mt Word lun l s chn, Byte cao th mt s l k tip.

Hnh I.3: Bit, Byte, Word trong cu trc nh ca MSP430

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II. H THNG RESET, NGT V CC CH HOT NG

II.1. H thng reset v khi ng
H thng mch reset bao gm 2 h thng l POR ( Power On Reset) v PUC
( Power Up Claer).

Hnh II.1: S h thng Reset ca MSP430

+ POR ch c sinh ra bi 3 s kin sau:
- Cp ngun cho thit b.
- Tn hiu chn RST /NMI mc thp khi thit lp cu hnh cho h thng Reset.
- SVS mc thp khi PORON = 1.
+ PUC th lun sinh ra khi POR c sinh ra, nhng khng xy ra ngc li. Nhng s
kin sau y s khi ng PUC:
- Khi POR c sinh ra.
- Watchdog timer ht hiu lc khi trong ch watchdog.
- Khi cht an ton ca Watchdog timer, Flash memory b vi phm.
II.1.1. Power On Reset ( POR)
POR c sinh ra bi cc iu kin lin quan n phn cng:
+ Thit b c cp ngun. POR c sinh ra nu in p cung cp gim xung di gi
tr m ti thit b khng cn lm vic chnh xc na, cn gi l s st p.
+ Khi chn RST /NMI mc thp nu n c thit lp chc nng Reset hn l ngt
khng kh ngy. Mc nh th chc nng ca chn ny l Reset.
+ nhng phng n ln hn c b gim st in p cung cp SVS. y ta c th thit
lp cu hnh, khng ging nh b d st p. N t c SVSFG nu in p st di mc
c lp trnh v c th Reset mt cch ty chn.
II.1.2. Power Up Clear ( PUC)
PUC th lun sinh ra khi POR c sinh ra, nhng khng xy ra ngc li. Nhng s
kin sau y s khi ng PUC:
+ Watchdog timer b trn trong ch gim st.

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+ Mt s c gn ghi vo thanh ghi iu khin gim st WDTCTL m khng ng t kha

0x5A trong Byte cao. Mt Reset c khi ng nu watchdog khng cho php hoc
ch nh thi khong.
+ PUC cn c sinh ra bi mt s truy cp a ch d tr ca nhng thanh ghi ngoi vi
hoc c b nh khng c thc thi.
II.1.3. Cc iu kin sau khi reset
Nhng iu kin ban u cho nhng thanh ghi v nhng ngoi vi sau khi Reset POR v
PUC c gii thiu tng qut nh sau:
+ Chn RST /NMI c thit lp cho Reset, n cng c th c s dng cho kt ni
JTAG mt vi loi nh F2013.
+ Phn ln cc chn I/O c thit lp nh l ng vo tn hiu s. Cng c mt vi ngoi
l l nhng chn ny c th s dng vi b dao ng thch anh nh F2013.
+Thanh ghi trng thi c Clear. iu ny c ngha l IC s hot ng ht cng sut,
mc d n c th c mt ch ngun thp trc khi c Reset tr li.
+ Watchdog timer bt u ch gim st. y l mt iu ct yu v bi v n l mt
c tnh an ton, nhng c ngha l bn phi vn hnh n hoc cho php n trc khi n
ht thi gian ch v Reset li chip.
+ B m chng trnh c np bi mt vector Reset c lu a ch 0xFFFE. N s
cung cp a ch ca lnh u tin c thc thi.
II.2. H thng ngt
H thng ngt c b tr thnh mt dy kt ni gm nhiu m un. M un gn nht l
CPU/NMIRS th c quyn u tin ngt cao hn. y c 3 loi ngt l: Reset h thng,
ngt kh ngy, ngt khng kh ngy.

Hnh II.2: S h thng ngt

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II.2.1. Ngt khng kh ngy

Ngt khng kh ngy NMI th khng b che bi bt ngt cho php chung GIE nhng b
che bi cc bt ngt ring l nh NMIIE, ACCVIE, OFIE. Khi mt ngt NMI c chp
nhn th tt c nhng bt ngt cho php NMI t ng Reset. Chng trnh bt u chy
a ch c lu tr trong vector ngt khng kh ngy l 0FFFCh.
Ngt khng kh ngy c th c sinh ra bi 3 ngun sau:
+ Bin ca chn RST /NMI khi c thit lp ch NMI.
+ Xut hin nhng s t gy dao ng.
+ C s vt qu d liu b nh Flash.

Hnh II.3: S khi ca ngun ngt kh ngy

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Chn RST /NMI

Khi cp ngun, chn RST /NMI c thit lp ch Reset. Chc nng ca chn
RST /NMI c chn trong thanh ghi b iu khin gim WDTCTL. Nu chn
RST /NMI c thit lp khi ng li chc nng, CPU gi ch Reset trong lc
chn RST /NMI mc thp. Sau khi chn RST /NMI ln mc cao th CPU bt u chy
chng trnh t a ch lu trong vector Reset l 0FFFEh.
Nu chn RST /NMI c thit lp tnh nng NMI bi phn mm ngi s dng, mt tn
hiu bin c chn bi bt WDTNMIES sinh ra ngt NMI nu bt NMIIE c Set. C
NMIIFG cng c Set.
S vi phm d liu b nh Flash
C nh ACCVIFG c Set khi xut hin nhng s vi phm d liu b nh Flash. N c
th cho php pht sinh ngt NMI khi bt ACCVIE c thit lp. C ACCVIFG c th
c kim tra bi chng trnh ngt NMI nu NMI c gy ra bi s vi phm b nh
Flash.
S t gy dao ng
S t gy tn hiu dao ng bo cho ta bit c th b dao ng thch anh b li. S t
gy dao ng ny cng c th pht sinh ra ngt NMI bi vic thit lp bt OFIE.
Tn hiu PUC c th kch hot s t gy dao ng bi v b ngt mch PUC l LFXT1
ch LF thnh ra tt i ch HF. PUC cng tt i b dao ng XT2.
V d v mt b iu khin ngt NMI
Ngt NMI l mt ngt nhiu ngun. Ngt NMI t ng Reset cc Bit ngt cho php nh
NMIIE, OFIE v ACCVIE. S dng chng trnh ngt NMI reset cc c ngt v cho
php li cc Bit ngt sao cho ph hp vi nhng ng dng.

Hnh II.4: iu khin ngt NMI

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II.2.2. Ngt kh ngy

Ngt kh ngy c gy ra bi cc thit b ngoi vi vi kh nng ngt bao gm c b
nh thi gim st s trn ca b m thi gian. Mi ngun ngt kh ngy c th mt tc
dng mt cch ring l bi mt bt ngt cho php hoc tt c nhng ngt kh ngy c th
b mt tc dng bi bt cho php ngt GIE thanh ghi trng thi.
II.2.3. X l ngt
Khi mt ngt c yu cu t thit b ngoi vi, cc Bit ngt c cho php v Bit GIE
c Set, chng trnh ngt c yu cu. Ch c nhng Bit cho php ring r phi c
Set cho ngt khng kh ngy c yu cu.
S chp nhn ngt:
Thi gian tr ngt l 5 chu k ( CPUx) v 6 chu k ( CPU), bt u vi s chp nhn ca
mt yu cu ngt v ko di n khi thc hin nhng lnh u tin ca cc chng trnh
ngt. Ngt Logic c thc hin theo cc bc nh sau:
1. Bt k mt lnh no ang thc thi u c hon thnh.
2. B m chng trnh PC, a ch ca lnh k tip c y ln ngn xp.
3. SR c y ln ngn xp.
4. Cc ngt vi u tin cao hn th c chn nu cc ngt xy ra trong sut qu trnh
thc thi v lm tr hon chng trnh.
5. Nhng c ngt yu cu Reset mt cch t ng trn c ngun n. Nhiu c ngun
vn Set cho chng trnh bng phn mm.
6. SR c Clear. iu ny s chm dt bt c ch ngun thp no v Bit GIE
c Clear, hn na cc ngt th khng c tc dng.
7. Ni dung ca vc t ngt c np vo trong PC: Chng trnh ngt tip tc ti a
ch .

Hnh II.5: X l ngt

Quay v t chng trnh ngt:
Chng trnh ngt c chm dt vi lnh RETI: Quay v t mt chng trnh ngt.
S tr li t chng trnh ngt mt 5 chu k ( CPU) v 3 chu k ( CPUx) thc thi cc
hot ng sau:
1. SR vi tt c cc thit lp trc c ly ra t ngn xp. Tt c cc thit lp
trc ca GIE, CPUOFF, c hiu lc, bt chp cc ci t trong sut chng trnh
ngt.
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2. PC c ly ra t ngn xp v bt u thc thi ti ni m n b gin on khi ngt.

Hnh II.6: Quay v t chng trnh ngt

II.2.4. Ngt c hng ( Ngt vc t)
Ngt vc t khi u a ch nm trong dy a ch t 0FFFFh n 0FFC0h. Mt vc t
c lp trnh bi ngi s dng vi 16 bit a ch ca ngt tng ng.
N th ngh cung cp mt thng trnh ngt cho mi vc t ngt c gn cho mt M
un. Mt thng trnh ngt c th bao gm mt lnh RETI v mt vi vc t ngt c th
tr n n.
Nhng vc t ngt khng c ch nh c th c s dng cho m chng nu cn
thit.
Mt s m un Bit cho php, Bit ngt cho php, c ngt th nm SFRs. SFRs nm
phm vi a ch thp hn v c thc hin nh dang Byte. SFRs phi c truy cp
bng nhng lnh Byte.
a ch ca cc ngun ngt v c ngt c trnh by di Bng II.1

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INTERRUPT
SOURCE

INTERRUPT
FLAG

Power-up,
external
reset, watchdog, flash
password,
illegal
instruction fetch.

PORIFG
RSTIFG
WDTIFG
KEYV

NMI, oscillator fault, NMIIFG

flash memory access ACCVIFG
violation.
OFIFG
device-specific
device-specific
device-specific
Watchdog timer
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific
device-specific

WDTIFG

SYSTEM
INTERRUPT

WORD
ADDRESS

PRIORITY

RESET

0FFFEh

31

(non)-maskable
(non)-maskable
(non)-maskable

0FFFCh

30

0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
0FFDEh
0FFDCh
0FFDAh
0FFD8h
0FFD6h
0FFD4h
0FFD2h
0FFD0h
0FFCEh
0FFCCh
0FFCAh
0FFC8h
0FFC6h
0FFC4h
0FFC2h
0FFC0h

29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

maskable

Bng II.1: Nhng ngun ngt, c ngt v vc t ngt

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II.3. Cc ch hot ng
H MSP430 c thit k cho nhng ng dng s dng ngun thp v s dng nhiu
ch hot ng khc nhau. Cc ch hot ng khc nhau 3 c im chnh:
+ Mc s dng ngun thp.
+ Tc v lu lng d liu.
+ Mc lm nh i lng tiu th in ca cc thit b ngoi vi.

Hnh II.7: Dng tiu th ca MSP430x1xx cc ch hot ng

ch ngun thp LPM0 n LPM4 c thit lp vi cc Bit SCG0, SCG1,
OSCOFF, CPUOFF trong thanh ghi trng thi. u im ca cc Bit iu khin SCG0,
SCG1, OSCOFF v CPUOFF trong thanh ghi trng thi l ch hot ng hin ti s
c lu trong Stack trong sut qu trnh ngt din ra. Chng trnh s quay v ch
hot ng trc nu gi tr c lu trong thanh ghi trng thi khng b thay i trong
sut qu trnh ngt. Chng trnh c th quay v mt ch hot ng khc nu c s
thay i gi tr c lu bn trong Stack trong sut qu trnh ngt din ra. Cc Bt iu
khin v Stack c th c truy cp bi bt k lnh no. Cc ch hot ng ca h
MSP430 c trnh by Bng II.2
Mode SCG1 SCG0 OSCOFF CPUOFF CPU and Clocks Status
0
0
0
CPU on, MCLK on, SMCLK on,
Active 0
ACLK on.
0
0
1
CPU off, MCLK off, SMCLK on,
LPM0 0
ACKL on.
1
0
1
CPU off, MCLK off, SMCLK on,
LPM1 0
ACKL on.
0
0
1
CPU off, MCLK off, SMCLK off,
LPM2 1
DCO off, ACKL on.
1
0
1
CPU off, MCLK off, SMCLK on,
LPM3 1
DCO off, ACKL on.
1
1
1
CPU off, MCLK off, SMCLK off,
LPM4 1
DCO off, ACLK off.
Bng II.2: Cc ch hot ng c bn ca MSP430

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II.3.1. Cch nhp v thot khi Low-Power Modes

Mt s kin ngt c cho php s kch hot MSP430 t bt k ch hot ng ngun
thp no. Chng trnh l:
Nhp chng trnh ngt:
+ PC v SR c lu tr trn ngn xp.
+ Cc Bit CPUOFF, SCG1 v OSCOFF t ng Reset.
Tr v t chng trnh ngt:
+ SR c ly ra t ngn xp v khi phc li ch iu hnh trc .
+ Cc Bit SR c lu tr trong ngn xp c th b thay i trong thng trnh dch v
ngt quay tr v mt ch hot ng khc khi lnh RETI c thc thi.
V d:
; Ch LPM0
BIS #GIE+CPUOFF,SR ; Khi to LPM0
;...
; Dng chng trnh
;
; Thot khi chng trnh con ngt LPM0
BIC #CPUOFF,0(SP)
; Tr v chng trnh chnh bng lnh RETI
RETI
; Ch LPM3
BIS #GIE+CPUOFF+SCG1+SCG0,SR ; Khi to LPM3
;...
; Dng chng trnh
;
; Thot khi chng trnh con ngt LPM3
BIC #CPUOFF+SCG1+SCG0,0(SR)
; Tr v chng trnh chnh bng
lnh RETI
RETI
III. RISC 16 BIT CPU
III.1. Gii thiu b x l trung tm CPU
CPU ca h vi iu khin MSP430 mang nhng c im thit k c bit nh k thut
tnh ton r nhnh, s dng ngn ng lp trnh cp cao nh C, C++. CPU cn c th nh
a ch ca mt vng a ch bng cch nh du vng nh.
CPU mang nhng c im sau:
+ Cu trc RISC vi 27 lnh ch th v 7 ch nh a ch.
+ y thanh ghi d liu bao gm thanh ghi b m chng trnh, thanh ghi trng thi,
thanh ghi con tr ngn xp.

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Hnh III.1: S cc khi chc nng ca CPU

+ Hn 16 bit thanh ghi tp tin gip gim bt s truy cp b nh.
+ 16 bit Bus a ch cp pht d liu trc tip.
+ 16 bit Bus d liu cp pht trc tip nhng thao tc trn khi thng tin.
+ B sinh hng ( Constant Generator ) cung cp 6 gi tr tc thi thng s dng nht v
lm gim c kch thc ca Code lp trnh.
III.2. Cc thanh ghi CPU
CPU c 16 thanh ghi 16 bit, 4 thanh ghi u l R0, R1,R2 v R3 l cc thanh ghi c chc
nng c bit, trong khi 12 thanh ghi cn li ( T R4 n R15) dng vi mc ch s
dng chung. Ni chung 16 thanh ghi ny l c trng cho mt b x l dng tp lnh rt
gn RISC CPU. Sau y l tm tt v cc tnh nng ca cc thanh ghi trong CPU:

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III.2.1.Thanh ghi b m chng trnh ( R0/PC)

Thanh ghi ny cha cc lnh k tip c thc thi. Mi lnh ny s dng mt s chn
ca nhng Byte ( hai, bn hoc su) v PC c gia tng mt cch ph hp. Cc lnh ny
cha dung lng trong khong 64 KB v PC sp xp chng theo a ch.
15

B m chng trnh ( R0/PC)

Hnh III.2: B m chng trnh
V d:
MOV
MOV

#LABEL,PC; a ni dung ca LABEL vo PC

LABEL,PC ; a a ch LABEL vo PC

MOV

@R14, PC ; Da gin tip a ch ca ni dung trong R14 vo PC

III.2.2.Con tr ngn xp ( SP)

Khi mt chng trnh con c gi, CPU nhy n chng trnh con v thc thi n,
sau quay tr v chng trnh chnh. Do phi c mt b nh tm lu gi a ch
ca chng trnh con trc khi CPU nhy n. l mc ch c s ca con tr ngn
xp. C nhiu b x l s dng mt b nh dnh ring cho con tr ngn xp nhng vi
h MSP430 th s dng nhng a ch cao ca RAM. Khi nhp a ch vo hay ly ra th
con tr ngn xp t ng iu chnh tng ln hay gim xung.
15

Con tr ngn xp ( R1/SP)

Hnh III.3: Con tr ngn xp

V d:
MOV
MOV
PUSH
POP

2(SP),R6 ; SP +2> R6
R7,0(SP) ; R7 > SP
#0123h
; a gi tr 0123h vo ngn xp
R8
; R8 = 0123h

Hnh III.4: S dng ngn xp

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Hnh III.5: Thao tc a d liu vo v ly ra t ngn xp

III.2.3.Thanh ghi trng thi ( SR)
Thanh ghi trng thi ( SR/R2) c s dng nh l mt thanh ghi ngun hoc thanh ghi
ch gm h thng cc c ( l nhng Bit n). Mt s c thng s dng l C, Z, N v V.
Chng c s dng trong cc thut ton hoc cc thao tc logic.
15
D tr

8
V

0
SCG1 SCG0

OSC CPU
GIE N Z C
OFF OFF

Hnh III.6: M t v cc Bit ca thanh ghi trng thi

+ C V: C trn. C ny c thit lp mi khi kt qu ca mt php tnh s c du qu
ln to ra Bit bc cao lm trn Bit du. C trn ch c dng pht hin li trong cc
php ton s hc c du.
+ SCG1: B nh thi h thng 1. Khi bit ny c thit lp s lm tt SMCLK.
+ SCG0: B nh thi h thng 0. Khi bt ny c thit lp s lm tt DCO nu
DCOCLK khng c s dng cho MCLK v SMCLK.
+ OSCOFF: Tt b dao ng. Khi bt ny c thit lp s lm tt b dao ng thch
anh LFXT1 khi LFXT1CLK khng s dng cho MCLK hoc SMCLK.
+ CPUOFF: Khi bt ny c thit lp s lm tt CPU.
+ GIE: Ngt cho php. Khi bt ny c set th cho php ngt kh ngy. Khi ta reset th
ngt kh ngy ny mt tc dng.
+ C Z: Zero bt. C Z c thit lp khi kt qu ca mt Byte hoc T l 0 v c
Clear khi kt qu khc 0.
+ C C: C carry. C ny thng thng dng cho cc lnh ton hc, c thit lp khi
c mt s nh sinh ra bi php cng hoc s mn bi php tr v c Clear nu khng
c s nh.
+ C N: Ph nh bt. C ny c thit lp khi kt qu ca mt Byte hoc Word b ph
nh v c Clear khi kt qu ngc li.
III.2.4.Thanh ghi b sinh hng CG1 v CG2
C su gi tr hng s thng c s dng c sinh ra bi thanh ghi b sinh hng R2
v R3 m khng cn b sung thm mt t 16 bit ca m chng trnh. Nhng hng s
c chn vi ch inh a ch thanh ghi ngun ( AS).

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Thanh ghi
R2
R2
R2
R2
R3
R3
R3
R3

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As
Hng s
Ghi ch
00
-------Ch thanh ghi
01
( 0)
Ch nh a ch
10
00004h
+4, x l Bit
11
00008h
+8, x l Bit
00
00000h
0, x l Word
01
00001h
+1
10
00002h
+2, x l Bit
11
0FFFFh
-1, x l Word
Bng III.1: Cc gi tr tc thi ca b sinh hng

Nhng u im:
+ Khng cn nhng lnh c bit.
+ Khng cn b sung t m cho 6 hng s.
+ M truy cp b nh khng i hi phi khi phc li hng s.
III.2.5. Thanh ghi s dng chung R4-R15
12 thanh ghi t R4 n R15 khng c mc ch chuyn dng, cc thanh ghi ny c th s
dng lm thanh ghi d liu hoc a ch u c v u l cc gi tr 16 Bit, t gip
n gin ha cc hot ng. Mt s qui c nn c lm theo nu chng trnh c
vit bng assemble. Nhng thanh ghi c bit ny nn c s dng di chuyn cc
tham s v tr v cc kt qu. Tt c cc vn ny u c gii quyt nu chng
trnh c vit bng C.
III.3 Cc ch nh a ch
III.3.1 nh a ch trc tip (immediate mode)
MOV #30H, R0 ; a gi tr 30h vo thanh ghi R0

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III.3.2. nh a ch gin tip thanh ghi (indirect register mode)

MOV @R10, 0(R0) ; a a ch gi tr ni dung ca thanh ghi R10 vo a ch c
cha ni dung thanh ghi R0. Nhng gi tr thanh ghi khng thay i.

III.3.3. nh a ch gin tip t tng ( indicrect autoincrement mode )

MOV @R10+,0(R0); Ly ni dung ca thanh ghi R10 vo thanh ghi R0 v ng
thi tng a ch thanh ghi R10 ln 2.
V d : Lc u Thanh ghi R10 c cha a ch ca nh (123h) c cha gi tr l 10h,
thanh ghi R0 c cha a ch l 0AFH th sao khi thc hin lnh ta c kt qu nh sau:
a ch con tr ca R10 tng ln 125h, cn a ch con tr ca R0 khng i l 0AFH,
Nhng n c cha gi tr l 10h.

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III.3.4. nh a ch trc tip thanh ghi( immediate mode )

MOV R0,R1 ; a gi tr thanh ghi R0 vo thanh ghi R1.

III.3.5. nh a ch tuyt i ( absoluto mode)

MOV &EDE,&TONI ; a gi tr ca a ch c cha nhn EDE vo a ch c
cha nhn TONI.
Vd: EDE c a ch l 0FF0h cha gi tr l 1234h, TONI c a ch l 1FFh c gi tr
bt k. Sau khi thc hin lnh th TONI c gi tr l 1234h.
III.3.6. nh a ch gia cc bin (symbolic mode)
MOV EDE,TONI ; a gi tr ca bin c a ch ca bin EDE vo bin TONI.
V d: EDE c gi tr 10h, TONI c gi tr bt k. Sau khi thc hin lnh TONI c gi tr
l 10h.
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III.3.7. nh a ch con tr ( indexed mode)

MOV 2(R5),3(R6) ; a gi tr ti a ch ca R5 +2 vo a ch R6+3.

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IV. CC B NH THI C BN
IV.1. Gii thiu
MSP430 s dng b nh thi m h thng c gi r v s dng ngun cc thp. C 3
xung Clock bn trong nn ngi s dng c th la chn sao cho cn bng gia hiu sut
lm vic vi ngun in th tiu th. Mt m un b nh thi c 2 hoc 3 ngun xung
Clock:
+ LFXT1CLK: B dao ng tn s thp/ tn s cao, n c th c s dng vi tn s
thch anh 32768 Hz hoc tn s thch anh chun, hoc b cng hng t 450 KHz n 8
MHz.
+ XT2CLK: B dao ng tn s cao. B dao ng ny c th c s dng vi thch
anh chun, b cng hng, hoc ngun xung Clock bn ngoi c tn s t 450 KHz n
8 MHz.
+ DCOCLK: B dao ng c iu khin bng k thut s ( DCO).
Ba tn hiu xung Clock trn c c l t nhng m un Clock c bn nh:
+ ACLK: Ngun xung Clock b tr. ACLK c lu trong b m LFXT1CLK v c
chia 1, 2, 4 hoc 8. ACLK chng trnh c th c chn cho nhng m un ngoi vi
ring r.

Hnh IV.1: S khi chc nng ca b nh thi MSP430

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+ MCLK: B nh thi ch. MCLK c th c chn nh l LFXT1CLK, XT2CLK (

nu sn c), hoc DCOCLK. MCLK c chia 1, 2, 4 hoc 8. MCLK th c s dng
bi CPU v h thng.
+ SMCLK: B nh thi con. SMCLK c th c chn nh l LFXT1CLK, XT2CLK (
nu sn c), hoc DCOCLK. SMCLK c chia 1, 2, 4 hoc 8 v c chn cho nhng
m un ngoi vi ring r.
IV.2. Ch hot ng ca cc Clock Module +
PUC, MCLK, SMCLK c bt ngun t B to xung tc cao DCO, tn s khong
1.1 MHz. ACLK th c bt ngun t LFXT1CLK ch TF vi mt dung khng 6
pF bn trong.
Nhng Bit iu khin SCG0, SCG1, OSCOFF v CPUOFF ca thanh ghi trng thi thit
lp cu hnh cc ch hot ng ca MSP430, cho php hoc khng cho php s phn
on ca Clock Module+.
Clock Module+ c th c thit lp hoc ti thit lp bi mt chng trnh trong bt k
mt khong thi gian no trong sut qu trnh thc thi chng trnh.
V d nh:
BIS.B #RSEL2+RSEL1+RSEL0,&BCSCTL1 ; Select range 7
BIS.B #DCO2+DCO1+DCO0,&DCOCTL;
Select max DCO tap
IV.2.1. B dao ng tn s thp
B dao ng tn s thp ( VLO) cung cp mt tn s 12 KHz m khng cn mt thch
anh. Ngun VLOCLK c chn bi vic thit lp LFXT1Sx = 10 khi XTS = 0. Bit
OSCOFF tt VLO cho LPM4. B dao ng thch anh LFXT1 b tt khi VLO c chn
gim lng tiu th ca mch in. VLO khng cn cp ngun khi khng c s
dng.
IV.2.2. B dao ng LFXT1
B dao ng LFXT1 tiu th nng lng cc thp, s dng dao ng thch anh 32768
Hz trong ch LF ( XTS = 0). Thch anh c kt ni vo chn XIN v XOUT.
Chng trnh la chn Bit XCAPx thit lp vic cung cp mt in dung cho LFXT1.
in dung ny c th l 1pF, 6pF,10pF hoc 12.5pF ty loi. Ta c th gn thm nhng
t in bn ngoi nu cn.
LFXT1 cng cn mt thch anh tc cao hoc mt b cng hng khi ch HF (
XTS = 1, XCAPx = 00). Thch anh hoc b cng hng ny kt ni vi chn XIN v
XOUT v cn mc thm mt t in. T in ny c gi tr phi ph hp vi chi tit k
thut ca thch anh hoc b cng hng. Khi LFXT1 ch HF th bit LFXT1Sx la
chn bin hot ng.
LFXT1 cng c th s dng ngun tn hiu bn ngoi chn XIN ch LF hoc HF
khi LFXT1Sx = 1, OSCOFF = 0 v XCAPx = 00. Khi s dng vi ngun tn hiu bn
ngoi th tn s phi ph hp vi gi tr trong datasheet cho vic la chn ch . Nu tn
s vo ny thp di gii hn cho php th Bit LFXT1OF c th c thit lp cn tr
CPU t vic kha LFXT1CLK.
Chng trnh c th ngt LFXT1 bi vic thit lp OSCOFF nu LFXT1CLK khng bt
ngun t SMCLK hoc MCLK.

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Hnh IV.2: Ngt tn hiu cho b dao ng LFXT1

IV.2.3. B dao ng XT2
mt vi h MSP430 c thm b dao ng thch anh th 2 l XT2. XT2 l ngun
ca XT2CLK v n mang nhng c im tng ng vi LFXT1 trong ch HF. Bit
XT2Sx la chn phm vi hot ng ca XT2. Bit XT2OFF ngt XT2 nu XT2CLK
khng c s dng cho SMCLK v MCLK.
XT2 c th s dng ngun tn hiu bn ngoi chn XT2IN khi Bit XT2Sx = 11 v
XT2OFF = 0. Khi s dng vi tn hiu bn ngoi th tn s ny phi ph hp vi gi tr
ca bng s liu XT2. Khi tn s ny thp di mc qui nh th Bit XT2OF s c
thit lp cn tr CPU bng cch kha XT2CLK.

Hnh IV.3: Tt tn hiu XT2

IV.2.4. B dao ng k thut s ( DCO)
DCO l mt b tch hp dao ng k thut s. Tn s DCO c th c iu chnh bi
chng trnh s dng nhng Bit DCOx, MODx, RSELx.
Chng trnh c th hy DCOCLK bi vic thit lp SCG0 khi n khng tng l ngun
SMCLK v MCLK.

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Hnh IV.4: iu khin ON/OFF ca DCO

iu chnh tn s DCO:
Sau mt PUC, RSELx = 7 v DCOx = 3, DCO bt u vi mt tn s trung bnh.
SMCLK v MCLK c ngun t DCOCLK. Bi v CPU thc thi m chng trnh t
MCLK, m MCLK th li bt ngun t DCO. Code chng trnh c thc thi bt u t
PUC v chm hn 2s.
Tn s ca DCOCLK c thit lp bi cc tnh nng sau:
+ Bn Bit RSELx cho php la chn 16 dy tn s cho DCO. Nhng dy tn s ny th
c mc nh cho tng h MSP430 v c trnh by trong Datasheet ca tng loi.
+ Ba Bit DCOx ca dy DCO c la chn bi cc bit RSELx n 8 bc tn s c
cch bit xp x 10%.
+ Nm bit MODx , chuyn i tn s c chn bi cc bit DCOx v tn s k tip cao
hn c thit lp bi DCOx + 1. Khi DCOx = 07h th nhng bit MODx khng chu nh
hng bi v DCO c thit lp cao nht cho vic la chn dy RSELx.

Hnh IV.5: Dy DCOx v bc RSELx

i vi MSP430F2xx c hiu chnh thanh ghi DCOCTL v BCSCTL1 cho vic tn

tr nhng tn s c bit trong b nh thanh ghi A. S dng nhng hiu chnh thit lp,
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thng tin c sao chp vo thanh ghi DCOCTL v BCSCTL1. Vic hiu chnh ny nh
hng n cc Bit DCOx, MODx, RSELx v xa cc Bit , ngoi tr XT2OFF th c
thit lp tr li. Nhng Bit ca BCSCTL1 c th c t hoc xa bi lnh BIS.B hoc
BIC.B
; Set DCO to 1 MHz:
MOV.B &CALBC1_1MHZ,&BCSCTL1 ; Set range
MOV.B &CALDCO_1MHZ,&DCOCTL ; Set DCO step + modulation
IV.2.5. B iu khin DCO
B iu khin l s trn ca 2 tn s DCO l fDCO v fDCO+ cung cp mt tn s ph c
ch gia fDCO v fDCO+ v m rng nng lng Clock, gim s nhiu in t
( EMI).
B iu khin pha trn fDCO v fDCO+ cho 32 chu k DCOCLK v c thit lp vi Bit
MODx. Khi MODx = 0 th b iu khin tt.
Phng trnh ca b iu khin :
t =(32 MODx) tDCO + MODx tDCO +1
Bi v fDCO thp hn tn s hiu dng v fDCO+1 th cao hn tn s hiu dng, sai lch
tn s gn bng 0. S sai lch tn s hiu dng bng 0 mi 32 chu k DCOCLK.
B iu khin DCO c thit lp bi chng trnh. DCOCLK c th c so snh vi
tn s n nh ca gi tr bit v c hiu chnh vi cc Bit DCOx, RSELx, MODx.

Hnh IV.6: Biu iu khin DCO

IV.2.6. Ch hot ng an ton ca clock module+
+ Clock module+ c tch hp nhng c im an ton khi b li b dao ng. N d
tm nhng li dao ng ca LFXT1 v XT2. Nhng li dao ngnh sau:
- Tn s thp b t gy ( LFXT1OF) ca LFXT1 trong ch LF.
- Tn s cao b t gy ( LFXT1OF) ca LFXT1 trong ch HF.
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- Tn s cao b t gy ( XT2OF) ca XT2.

+ Nhng Bit LFXT1OF v XT2 s c set nu dao ng thch anh b t gy v hot
ng khng cn chnh xc na. Nhng Bit ny s c Set cho n khi ht nhng li dao
ng v s t ng c xa khi cc dao ng tr v bnh thng.
+ C OFIFG c Set v c cht POR khi mt li dao ng c tm thy (
LFXT1OF v XT2OF). Khi OFIFG c Set, MCLK c bt ngun t DCO, v nu
OIFE c Set, OFIFG yu cu mt ngt NMI. Khi ngt c chp hnh th OIFE t
ng Reset tr li. C OFIFG phi c xa bng chng trnh.

Hnh IV.7: Ch hot ng an ton ca clock module+

Ngun MCLK t dao ng thch anh:
Sau mt PUC, Clock module+ s dng DCOCLK ca MCLK. Nu c yu cu, MCLK
c ngun t LFXT1 v XT2.
Qu trnh chuyn i MCLK bt ngun t DCO Clock sang dao ng thch anh ( LFXT1
v XT2) l:
1. Chuyn i trn dao ng thch anh v chn ch tng thch.
2. Xa c OFIFG
3. Ch i t nht 50s
4. Kim tra c OFIFG, lp li cc bc cho n khi c OFIFG c xa hon ton.
; Chn LFXT1 (ch HF) cho MCLK
BIC.W #OSCOFF,SR
; Bt OSC.
BIS.B #XTS,&BCSCTL1
; Chn ch HF
MOV.B #LFXT1S0,&BCSCTL3
; 13MHz Thch anh
L1:
BIC.B #OFIFG,&IFG1
; Xa c OFIFG
MOV.W #0FFh,R15
; Delay
L2:
DEC.W R15 ;
JNZ L2 ;
BIT.B #OFIFG,&IFG1
; Kim tra C OFIFG
JNZ L1
; Kim tra li nu khc 0
BIS.B #SELM1+SELM0,&BCSCTL2 ; chn LFXT1CLK
IV.2.7. S ng b ca cc tn hiu xung Clock
Khi mt s chuyn i MCLK v SMCLK t mt ngun ny sang mt ngun khc th s
chuyn i ny phi c thc hin mt cch ng b.

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Hnh IV.8: S chuyn i MCLK t DCOCLK sang LFTX1CLK

IV.3. Cc thanh ghi ca Clock module+

Bng IV.1: Cc thanh ghi ca Clock module+

IV.3.1. DCOCTL, DCO control register

+ DCOx: Bit 5 n 7, la chn tn s DCO. Nhng Bit ny la chn 8 tn s DCO ring

bit trong dy c xc nh bng vic thit lp RSELx.
+ MODx: Bit 0 n 4, la chn b iu khin. Bit ny xc nh tn s fDCO+1 xut hin
bao nhiu ln trong 32 chu k DCOCLK. Trong sut chu k cn li ( 32-MOD) tn s
fDCO th c s dng. Khng cho php khi DCOx = 7.

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IV.3.2. BCSCTL1, Basic Clock System Control Register 1

+ XT2OFF: Bit 7, tt XT2.

XT2OFF = 0: XT2 m
XT2OFF = 1: XT2 ng nu n khng s dng cho MCLK v SMCLK
+ XTS: Bit 6, la chn ch LFXT1.
XTS = 0: Ch tn s thp
XTS = 1: Ch tn s cao.
+ DIVAx: Bit 4-5, b chia ACLK
00: chia 1
01: chia 2
10: chia 4
11: chia 8
+ RSELx: Bit 0-3, la chn dy tn s. C 16 dy tn s kh dng. Dy tn s thp nht
c chn bng cch cho RSELx = 0. RSEL3 c b qua khi DCOR = 1
IV.3.3. BCSCTL2, Basic Clock System Control Register 2

+ SELMx: Bit 6-7, la chn ngun ca MCLK.

00: DCOCLK
01: DCOCLK
10: XT2CLK khi XT2 ang c sn trn Chip. LFXT1CLK hoc
VCLOCK nu XT2 khng c sn trn Chip.
11: LFXT1CLK hoc VCLOCK
+ DIVMx: Bit 4-5, b chia MCLK.
00: chia 1
01: chia 2
10: chia 3
11: chia 4
+ SELS: Bit 3, la chn ngun SMCLK.
0: DCOCLK
1: XT2CLK khi XT2 ang c sn trn Chip. LFXT1CLK hoc VCLOCK
nu XT2 khng c sn trn Chip.
+ DIVSx: Bit 1-2, b chia SMCLK.
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00: chia 1
01: chia 2
10: chia 3
11: chia 4
+ DCOR: Bit 0, la chn in tr DCO
0: in tr trong.
1: in tr ngoi.
IV.3.4. BCSCTL3, Basic Clock System Control Register 3

+ XT2Sx: Bit6-7, la chn dy tn s XT2.

00: 0.4 1 MHz dao ng thch anh hoc b cng hng
01: 1 3 MHz dao ng thch anh hoc b cng hng
10: 3 16 MHz dao ng thch anh hoc b cng hng
11: 0.4 16 MHz ngun dao ng t bn ngoi
+ LFXT1Sx: Bit 4-5, la chn loi xung Clock tn s thp v la chn dy tn s ca
LFXT1. La chn gia LFXT1 v VLO khi XTS = 0. La chn dy tn s LFXT1 khi
XTS = 1.
Khi XTS = 0:
00: LFXT1 tn s 32768 Hz dao ng thch anh
01: D tr
10: VLOCLK
11: Ngun ngoi.
Khi XTS = 1:
00: 0.4 1 MHz dao ng thch anh hoc b cng hng
01: 1 3 MHz dao ng thch anh hoc b cng hng
10: 3 16 MHz dao ng thch anh hoc b cng hng
11: 0.4 16 MHz ngun dao ng t bn ngoi
+ XCAPx: Bit 2-3, la chn in dung.
00: 1pF
01: 6pF
10: 10pF
11: 12.5pF
+ XT2OF: Bit 1, li t gy dao ng XT2
0: Khng c li xut hin
1: C li xut hin.
+ LFXT1OF: Bit 0, li t gy dao ng LFXT1
0: Khng c li xut hin
1: C li xut hin.

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IV.3.5. IE1, Interrupt Enable Register 1

Bit 0 v Bit 2 7: C th s dng cho cc m un khc.

OFIE: Bit 1, cho php ngt khi dao ng b li. Cho php c ngt OFIEG hot ng.
0: Khng cho php ngt.
1: Cho php ngt.
IV.3.6. IFG1, Interrupt Flag Register 1

Bit 0 v Bit 2 7: C th s dng cho cc m un khc.

OFIFG: Bit 1, cho php c ngt khi dao ng b li.
0: Khng cho php ngt.
1: Cho php ngt.

V. B NH FLASH
V.1. Gii thiu v b nh Flash
B nh thng thng c 2 loi l b nh ch c ROM v b nh truy cp ngu nhin
RAM, b nh Flash l mt s pha trn ca 2 loi b nh ny.
c im b nh Flash l:
+ Chi ph thp
+ c/Ghi nhanh
+ An ton
+ Mt cao
B nh Flash MSP430 bao gm nhng Bt, Byte, a ch t v kh lp trnh. Mi m un
b nh Flash c tch hp sn b iu khin dng iu khin cc hot ng ghi, xa
b nh. B iu khin ny gm 3 b: B to dao ng ch, b pht in p cho lp trnh,
b xa.
in p ngun Vcc ti thiu trong hot ng vit hoc xa b nh Flash l 2.7V. Nu
in p ngun xung thp di mc ny th b nh Flash khng th hot ng c.

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Hnh V.1: S khi chc nng ca b nh Flash

V.2. S phn on trong b nh Flash
B nh Flash ca MSP430 chia thnh nhng phn on nh: Bt n, byte hoc Word c
th c ghi vo b nh Flash. y l nhng kch thc nh nht ca b nh Flash c
th b xa.
B nh Flash c phn chia thnh mt b nh chnh v thnh phn b nh thng tin.
Khng c s khc bit v hot ng ca b nh chnh v thnh phn b nh thng tin.
Code chng trnh v d liu c th c lu trong c hai b phn. S khc nhau gia
hai phn vng ny l kch thc ca phn on v cc a ch vt l.
Thnh phn b nh thng tin c 2 phn on 128 byte ( MSP430F1101 ch c mt). B
nh chnh c hai hoc nhiu hn nhng phn on 512 byte. Nhng phn on ny chia
thnh nhng khi 64 byte bt u a ch 0xx00h, 0xx40h, 0xx80h, 0xxC0h v kt thc
0xx3Fh, 0xx7Fh, 0xxBFh, 0xxFFh.

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Hnh V.2: Nhng phn on trong b nh Flash

V.3. Cc b iu khin b nh Flash
B nh Flash c cc b iu khin nh sau:
+ B iu khin lp trnh v hot ng xa
+ C 3 hoc 4 thanh ghi
+ Mt b nh thi c ngun t ACLK, MCLK v SMCLK
VI. DIGITAL I-O
VI.1. Gii thiu v ng vo/ra s ( Digital I/O)
MSP430 c cc Port xut/ nhp d liu gi l cc Port I/O. Mi Port c 8 chn I/O, s
lng Port ty thuc vo tng h MSP430. Mi chn I/O c thit lp cc chc nng
vo/ra mt cch ring r, v cc chn I/O ny cng dng c hoc ghi d liu mt
cch c lp.
P1 v P2 c th dng ngt. Mi chn I/O ca P1, P2 c tc dng ngt c lp v c th
thit lp ngt cnh ln hoc cnh xung ca tn hiu vo.
Cc ng vo/ra s c m t nh sau:
+ Nhng chn I/O ring r c th c lp trnh mt cch c lp.
+ P1 v P2 c th thit lp lm nhng ngt ring r.
+ Nhng thanh ghi d liu vo/ra c lp.
+ C th thit lp tng ln hoc gim xung ca in tr mt cch c lp.
VI.2. Cc hot ng vo/ra s
VI.2.1. Thanh ghi d liu vo PxIN
Mi Bit trong mi thanh ghi PxIN phn nh gi tr ca tn hiu vo chn I/O tng ng
khi cc chn ny c thit lp chc nng I/O.
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Bit = 0: Ng vo mc thp
Bit = 1: Ng vo mc cao
VI.2.2. Thanh ghi d liu xut PxOUT
Mi Bit trong mi thanh ghi PxOUT l gi tr xut ra trn cc chn I/O tng ng khi khi
cc chn ny c thit lp chc nng I/O. Xut d liu c hng v vic tng gim in
tr th khng c php.
Bit = 0: Ng ra mc thp
Bit = 1: Ng ra mc cao
Nu cc chn iu khin tng-gim in tr b mt hiu lc th cc Bit tng ng trong
thanh ghi PxOUT c tc dng la chn vic tng gim in tr.
Bit = 0: Gim xung.
Bit = 1: Tng ln
VI.2.3. Cc thanh ghi nh hng PxDIR
Mi Bit trong mi thanh ghi PxDIR la chn nh hng ca chn I/O tng ng, bt
chp chc nng c chn ca chn. Nhng Bit PxDIR cho nhng chn I/O c la
chn cho nhng chc nng khc phi c thit lp theo yu cu ca chc nng .
Bit = 0: Nhng chn ca Port c nh hng l ng vo.
Bit = 1: Nhng chn ca Port c nh hng l ng ra.
VI.2.4. Thanh ghi cho php tng/gim in tr PxREN
Mi Bit ca mi thanh ghi PxREN dng cho php hoc khng cho php s tng/gim
in tr ca cc chn I/O tng ng. Nhng Bit tng ng ca thanh ghi PxOUT c
chn nu chn c tng ln hoc gim xung.
Bit = 0: Tng/gim in tr khng c cho php.
Bit = 1: Tng/gim in tr c cho php.
VI.2.5. Thanh ghi chc nng la chn PxSEL v PxSEL2
Cc chn ny c a hp vi cc cc chc nng ca cc m un ngoi vi khc. Mi Bit
PxSEL v PxSEL2 c s dng cho vic la chn chc nng ca cc chn: Chc nng
I/O xut nhp d liu hoc chc nng m un giao tip ngoai vi.
PxSEL2
0
0
1
1

PxSEL
Chc nng ca chn
0
Chc nng I/O
1
Chc nng m un giao tip ngoi vi ban u
0
c d tr
1
Chc nng m un giao tip ngoi vi th hai
Bng VI.1: La chn chc nng ca chn

V d:
;tn hiu ra ACLK trn P2.0
BIS.B #01h,&P2SEL ; chn chc nng ACLK
BIS.B #01h,&P2DIR ; chn chc nng out cho P2.0

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VI.2.6. Nhng ngt P1 v P2

Mi chn ca P1 v P2 c th lm mt ngt yu cu. Cc chn ny c thit lp vi cc
thanh ghi ph nh:
Cho php ngt ( PxIE)
Thanh ghi ny cho php ngt trn nhng chn ring r.
Bit = 0: khng cho php ngt.
Bit = 1: Cho php ngt.
Mi Bit cho php ngt PxIE ny c lin kt vi c ngt PxIFG tng ng.
Vic ghi vo thanh ghi PxOUT v PxDIR c th nh hng n vic iu chnh PxIE.
Thanh ghi la chn ngt cnh ( PxIES)
La chn loi ngt khi xut hin s bin i tn hiu ( Nu PxIE v GIE c Set)
Bit = 0: Ngt cnh ln
Bit = 1: Ngt cnh xung
Thanh ghi c ngt ( PxIFG)
C ngt ny c Set t ng theo chng trnh c lp trnh trc khi xut hin
mt s chuyn i tn hiu. C PxIFG phi s dng chng trnh Reset.
Bit = 0: Khng c ngt.
Bit = 1: C ngt.
VI.3. Cc thanh ghi I/O
Port

P1

P2

P3

Thanh ghi

Ng vo
Ng ra
nh hng
C ngt
Ngt cnh
Cho php ngt
Chn cng
Chn cng 2
Cho php in tr
Ng vo
Ng ra
nh hng
C ngt
Ngt cnh
Cho php ngt
Chn cng
Chn cng 2
Cho php in tr
Ng vo
Ng ra
nh hng
Chn cng
Chn cng 2
Cho php in tr

T kha

P1IN
P1OUT
P1DIR
P1IFG
P1IES
P1IE
P1SEL
P1SEL2
P1REN
P2IN
P2OUT
P2DIR
P2IFG
P2IES
P2IE
P2SEL
P2SEL2
P2REN
P3IN
P3OUT
P3DIR
P3SEL
P3SEL2
P3REN

a ch

020H
021H
022H
023H
024H
025H
026H
041H
027H
028H
029H
02AH
02BH
02CH
02DH
02EH
042H
02FH
018H
019H
01AH
01BH
043H
010H

Loi thanh ghi

Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c

Trng thi ban

u

-Khng i
Reset vi PUC
Reset vi PUC
Khng i
Reset vi PUC
Reset vi PUC
Reset vi PUC
Reset vi PUC
-Khng i
Reset vi PUC
Reset vi PUC
Khng i
Reset vi PUC
0C0h vi PUC
Reset vi PUC
Reset vi PUC
-Khng i
Reset vi PUC
Reset vi PUC
Reset vi PUC
Reset vi PUC

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P4

P5

P6

P7

P8

Ng vo
Ng ra
nh hng
Chn cng
Chn cng 2
Cho php in tr
Ng vo
Ng ra
nh hng
Chn cng
Chn cng 2
Cho php in tr
Ng vo
Ng ra
nh hng
Chn cng
Chn cng 2
Cho php in tr
Ng vo
Ng ra
nh hng
Chn cng
Chn cng 2
Cho php in tr
Ng vo
Ng ra
nh hng
Chn cng
Chn cng 2
Cho php in tr

hnphung15@gmail.com

P4IN
P4OUT
P4DIR
P4SEL
P4SEL2
P4REN
P5IN
P5OUT
P5DIR
P5SEL
P5SEL2
P5REN
P6IN
P6OUT
P6DIR
P6SEL
P6SEL2
P6REN
P7IN
P7OUT
P7DIR
P7SEL
P7SEL2
P7REN
P8IN
P8OUT
P8DIR
P8SEL
P8SEL2
P8REN

01CH
01DH
01EH
01FH
044H
011H
030H
031H
032H
033H
045H
012H
034H
035H
036H
037H
046H
013H
038H
03AH
03CH
03EH
047H
014H
039H
03BH
03DH
03FH
048H
015H

Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ch c
Ghi/c
Ghi/c
Ghi/c
Ghi/c
Ghi/c

-Khng i
Reset vi PUC
Reset vi PUC
Reset vi PUC
Reset vi PUC
-Khng i
Reset vi PUC
Reset vi PUC
Reset vi PUC
Reset vi PUC
-Khng i
Reset vi PUC
Reset vi PUC
Reset vi PUC
Reset vi PUC
-Khng i
Reset vi PUC
Reset vi PUC
Reset vi PUC
Reset vi PUC
-Khng i
Reset vi PUC
Reset vi PUC
Reset vi PUC
Reset vi PUC

Bng VI.2: Cc cch nh ngha I/O

VII. B NH THI GIM ST

VII.1. Gii thiu v Watchdog timer
Chc nng c bn ca Watchdog timer ( WDT) l iu khin h thng khi ng li khi
chng trnh xut hin li. Chng hn nh chng trnh b kt trong mt vng lp v tn
th lc phi dng n Watchdog timer g li. Nu chc nng gim st khng c
s dng trong mt s ng dng th Watchdog timer c th c thit lp nh l mt b
nh thi khong v c th sinh ra ngt nhng khong thi gian c la chn.
Nhng M un ca watchdog timer c m t theo s sau:

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Hnh VII.1: S khi ca Watchdog timer

VII.2. Hot ng ca Watchdog timer
Watchdog timer c th c thit lp nh l mt b gim st hoc b nh thi khong
vi thanh ghi WDTCTL . Thanh ghi WDTCTL cng cha nhng Bit iu khin thit
lp cho chn RST /NMI. WDTCTL l thanh ghi 16 Bit dng ghi/c d liu v c
bo v bng mt khu. Bt k c hoc vit d liu u s dng ch lnh Word v khi ghi
d liu phi bao gm t kha 05Ah Byte cao. Khi ghi vo thanh ghi WDTCTL bt k
gi tr no hn 05Ah Byte cao th s vi phm s an ton v khi ng ngt PUC bt
chp ch thi gian no. Cn vic c d liu th ch c c cc gi tr c 069h
Byte cao.
VII.2.1. Watchdog timer counter ( WDTCNT)
+ WDTCNT l mt b m ln 16 Bit v n khng nh a ch trc tip c.
+ WDTCNT th c iu khin thng qua watchdog timer iu khin thanh ghi
WDTCTL.
+ WDTCNT c th c bt ngun t ACLK hoc SMCLK. Ngun xung Clock th c
la chn bi Bit WDTSSEL.

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VII.2.2. Ch gim st
Sau mt ngt PUC, m un WDT c thit lp trong ch gim st vi rng xung
~32ms s dng DCOCLK. Ngi s dng phi ci t, tm dng hoc xa WDT trong
khong thi gian khi ng ban u hoc mt ngt PUC s c sinh ra. Khi WDT c
thit lp hot ng trong ch gim st, vic ghi vo thanh ghi WDTCTL vi mt t
kha sai hoc ht thi gian c chn s sinh ra ngt PUC. PUC s khi ng li WDT
ch mc nh v thit lp chn RST /NMI ch Reset.
VII.2.3. Ch hn gi
Thit lp Bit WDTTMSEL chn ch hn gi. Ch ny c th s dng cho
nhng ngt c chu k. Trong ch hn gi th c WDTIFG thit lp khong thi gian
hn gi. PUC th khng c sinh ra trong ch hn gi khi ht thi gian chn v c
WDTIFG cho php Bit WDTIE khng thay i.
Khi Bit WDTIE v GIE c Set th c WDTIFG s yu cu ngt. C ngt WDTIFG s
t ng khi ng li nu ngt ca n yu cu c duy tr, hoc c th t khi ng
bng phn mm. a ch vc t ngt trong ch hn gi ny th khc trong cc ch
gim st khc.
VII.2.4. Ngt trong watchdog timer
WDT s dng 2 Bit trong SFRs cho iu khin ngt:
- C ngt WDT l WDTIFG c nh v trong IFG1.0
- Ngt cho php WDT l WDTIE c nh v trong IE1.0
Khi s dng WDT trong ch gim st th c WDTIFG l ngun ca vc t ngt.
WDTIFG c th c s dng trong chng trnh ngt nu WDT l nguyn nhn ca
vic khi ng li thit b. Nu c ny c Set sau khi WDT khi ng ch Reset
bi s ht thi gian nh thi hoc s vi phm kha an ton. Nu c WDTIFG c xa
th s Reset c gy ra bi mt ngun khc.
Khi s dng WDT trong ch hn gi, c WDTIFG c Set sau khi thi gian hn gi
c chn v yu cu phi c mt ngt hn gi khi WDTIE v GIE c Set. Vc t ngt
ny khc vi vc t Reset ch gim st. Trong ch hn gi c WDTIFG c
Reset t ng khi ngt c duy tr hoc c th t lp trnh.
VII.2.5 V d
Bt k vic ghi vo thanh ghi WDTCTL u phi c mt t 05Ah (WDTPW) Byte cao.

; Xa watchdog timer mt cch c chu k

MOV #WDTPW+WDTCNTCL,&WDTCTL
;
; Thay i watchdog timer
MOV #WDTPW+WDTCNTL+SSEL,&WDTCTL
;
; Dng watchdog timer
MOV #WDTPW+WDTHOLD,&WDTCTL
;
; thay i WDT trong ch hn gi, clock/8192 interval
MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS0,&WDTCTL
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VII.3. Nhng thanh ghi ca watchdog timer

Watchdog timer c 3 thanh ghi l WDTCTL, IE1 v IFG1 nh trnh by bng bn di.

VII.3.1. WDTCTL

+ WDTPW: Bit 8 15, lun c bng 069h v ghi bng 05Ah hoc PUC s c sinh
ra.
+ WDTHOLD: Bit 7, y l Bit dng ca watchdog timer.
WDTHOLD = 1: watchdog timer ngng.
WDTHOLD = 0: watchdog timer khng dng li.
+ WDTNMIES: Bit 6, la chn cnh ngt NMI watchdog timer. Bit ny la chn cnh
ngt cho ngt NMI khi WDTNMI = 1.
WDTNMIES = 1: Cnh ngt rt xung thp.
WDTNMIES = 0: Cnh ngt dng ln cao.
+ WDTNMI: Bit 5, la chn chc nng cho chn RST /NMI
WDTNMI = 0: reset
WDTNMI = 1: Ngt NMI
+ WDTTMSEL: Bit 4, La chn ch ca watchdog timer.
WDTTMSEL = 0: Ch gim st
WDTTMSEL = 1: Ch hn gi
+ WDTCNTCL: Bit 3, xa b m watchdog timer. WDTCNTCL = 1 th xa gi tr
m v 0000h.
+ WDTSSEL: Bit 2, la chn ngun xung Clock cho watchdog timer.
WDTSSEL = 0: SMCLK
WDTSSEL = 1: ACLK
+ WDTISx: Bit 0 -1, la chn watchdog timer thit lp c WDTIFG v/hoc sinh ra
mt PUC.
00: Watchdog clock source /32768
01: Watchdog clock source /8192
10: Watchdog clock source /512
11: Watchdog clock source /64
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VII.3.2. IE1, thanh ghi cho php ngt 1

+ Bit 5 n 7: Nhng Bit ny s dng cho nhng M un khc.

+ NMIIE: Bit 4, cho php ngt NMI. Bi v Bit ny c th s dng cho cc m un khc
nn c ngh khi Set hoc Clear Bit ny nn s dng lnh BIS.B hoc BIC.B hn l
MOV.B hoc CLR.B.
0: Khng cho php ngt
1: Cho php ngt
+ Bit 1n 3: Nhng Bit ny s dng cho nhng M un khc.
+ WDTIE: Bit 0, cho php ngt watchdog timer. Bit ny cho php c ngt WDTIFG cho
ch hn gi. Khng cn thit phi thit lp Bit ny cho ch gim st v IE1 c th
s dng cho cc m un khc. N th c ngh khi Set hoc Clear Bit ny nn s
dng lnh BIS.B hoc BIC.B hn l MOV.B hoc CLR.B.
0: Khng cho php ngt
1: Cho php ngt
VII.3.3. IFG1, thanh ghi c ngt 1

+ Bit 5 n 7 v 1 n 3: Nhng Bit ny s dng cho nhng M un khc.

+ NMIIFG: Bit 4, c ngt NMI.
0: Khng cho php ngt
1: Cho php ngt
+ WDTIFG: Bit 0, c ngt watchdog timer. Trong ch gim st th WDTIFG c
gi cho n khi c Reset bng chng trnh. Trong ch hn gi th WDTIFG c
Reset t ng bi chng trnh ngt hoc cng c th bi chng trnh. Bi v IFG1 c
th s dng cho cc m un khc nn khi xa c WDTIFG ta nn s dng lnh BIS.B
hoc BIC.B hn l MOV.B hoc CLR.B.
0: Khng cho php ngt
1: Cho php ngt

VIII. TIMER A
VIII.1. Gii thiu tng qut Timer_A
Timer_A l mt b m/nh thi 16 Bit vi 3 thanh ghi capture/compare. Timer_A c
th h tr t hp capture/compare, nhng ng ra PWM, v s xc nh thi khong.
Timer_A cng c nhng ngt bao qut. Ngt c th c sinh ra t s trn b m.
Timer_A bao gm cc khi chc nng c m t nh sau:
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Hnh VIII.1: Biu khi Timer_A

VIII.2. Ch hot ng ca Timer_A
Timer_A c 4 ch hot ng l Stop, Up, Continuous, Up/Down v c iu khin
bi Bit MCx.
MCx

Ch hot ng

M t hot ng

00

Stop

Timer_A tm dng

01

Up

m ln t 0x0000 n gi tr TACCR0

10

Continuous

Tip tc ch m t 0x0000 n 0xFFFF

11

Up/Down
m t 0x0000 n TACCR0 ri quay v 0
Bng VIII.1: Cc ch hot ng ca Timer_A
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VIII.2.1. Up mode
+ TAR m t 0x0000 ln n gi tr TACCR0
+ TAR TACCR0: C ngt thanh ghi TACCR0 l CCIFG th c Set.
+ Khi TAR = TACCR0 th EQU0 = 1 ( khi ng li vic m )
+ TACCR0 0 : C ngt TAIFG c Set.

VIII.2.2. Continuous mode

+ TAR m ln n gi tr 0xFFFF
+ Khi TAR = 0xFFFF th TAR bt u m li t 0.
+ Khi 0xFFFF 0: C ngt TAIFG c Set.

VIII.2.3. Up/Down mode

+ m t 0x0000 n TACCR0 ri quay v 0
+ TACCR0 1 TACCR0: C ngt CCIFG c Set.
+ Khi TAR = TACCR0 th vic m c o ngc.
+ Khi 0x0001 0x0000: C ngt TAIFG c Set

VIII.2.4. Cc phng php Reset Timer_A

+ Ghi 0 vo thanh ghi TAR
+ Ghi 0 vo thanh ghi TACCR0
+ Thit lp Bit TACLR trong thanh ghi iu khin Timer ( TACTL)

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VIII.2.5. Ch Capture
c s dng cho s o lng chu k thi gian ca cc s kin vi s can thip rt nh
ca CPU
+ Set Bit CAP la chn ch ny.
+ Set Bit SCS ng b Capture vi khi Timer k tip.
+ Tn hiu vo c ly mu bi CCIxA, c la chn bi Bit CCISx trong thanh ghi
TACCTLx.
+ Thit lp Bit CMx la chn cc ch Capture
+ Khi mt xung hp l c pht hin trn ng vo th gi tr trong TAR c cht trong
thanh ghi TACCRx cung cp mt mc thi gian cho s kin.
+ C ngt CCIFG c Set.
+ Bit COV = 1 iu khin s trn s kin khi mt capture th 2 c s dng, trc khi
gi tr t capture u tin c c.
VIII.2.6. Ch Compare
S dng to ra nhng xung ng ra v iu chnh rng xung ng ra.
+ Reset Bit CAP la chn ch Compare
+ TAR m ln n gi tr c lp trnh trong thanh ghi TACCRx.
+ Khi gi tr Timer bng vi gi tr trong thanh ghi TACCRx th mt ngt c sinh ra.
C ngt CCIFG th Set, EQUx = 1.
+ EQUx c tc dng so snh tn hiu ng ra OUTx ph hp vi OUTMODx.
+ Tn hiu vo CCI c cht trong SCCI.
VIII.2.7. Hot ng ng ra
OUTMODx Ch
000
Out
001
010
011
100
101
110
111

M t hot ng
Tn hiu ng ra c xc inh bi Bit OUTx
OUTx = 1 timer = TACCRx
Set
OUTx = 0 timer = 0
OUTx = toggle timer = TACCRx
Toggle/Reset
OUTx = 0 timer = TACCR0
OUTx = 1 timer = TACCRx
Set/Reset
OUTx = 0 timer = TACCR0
OUTx = toggle timer = TACCRx
Toggle
Chu k ng ra gp i chu k Timer
OUTx = 0 timer = TACCRx
Reset
OUTx = 1 Mt ch ng ra khc c la
chn v tc ng n ng ra.
OUTx = toggle timer = TACCRx
Toggle/Set
OUTx = 1 timer = TACCR0
OUTx = 0 timer = TACCRx
Reset/Set
OUTx = 1 timer = TACCR0
Bng VIII.2: Cc hot ng ng ra Timer_A

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Hnh VIII.1: Nhng ng ra mu

VIII.3. Cc thanh ghi Timer_A
Cc thanh ghi ca Timer_A c trnh by di bng sau:

Bng VIII.2: Cc thanh ghi Timer_A

VIII.3.1. TACTL,Timer_A Control

+ TASSELx: La chn ngun xung Clock Timer_A

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00 TACLK
01 ACLK
10 SMCLK
11 INCLK
+ IDx: B chia tn hiu vo
00 /1
01 /2
10 /4
11 /8
+ MCx: Bit iu khin
00 STOP
01 UP
10 CONTINUOUS
11 UP/DOWN
+ TACLR: Xa Timer_A. Set Bit ny s Reset TAR, IDx.
+ TAIE: Cho php ngt Timer_A
0 Khng cho php ngt
1 Cho php ngt
+ TAIFG: C ngt Timer_A
0 Khng c tr hon ngt
1 C tr hon ngt
VIII.3.2. TAR, Timer_A Counter

TARx: Thanh ghi m ca Timer_A

VIII.3.3. TACCTLx, Capture/compare control

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+ CMx: Ch Capture
00 Khng Capture
01 Capture trn cnh ln
10 Capture trn cnh xung
11 Capture trn c hai cnh ln v cnh xung
+ CCISx: La chn ng vo Capture/Compare
00 CCIxA
01 CCIxB
10 GND
11 Vcc
+ SCS: ng b ngun Capture
0 Khng ng b
1 ng b
+ SCCI: ng b ng vo Capture/Compare. La chn tn hiu vo CCI th c cht
vi tn hiu EQUx v c th c thng qua Bit SCCI
+ CAP: Chn ch
0 Compare
1 Capture
+ OUTMODx: Chn ch ng ra
000 Out
001 Set
010 Toggle/Reset
011 Set/Reset
100 Toggle
101 Reset
110 Toggle/Set
111 Reset/set
+ CCIE: Cho php ngt Capture/Compare.
0 Khng cho php ngt
1 Cho php ngt
+ CCI: Ng vo Capture/Compare c th c bi Bit ny.
+ OUT: Ng ra
0 Mc thp
1 Mc cao
+ COV: S trn Capture
0 Khng xut hin trn Capture
1 Xut hin trn Capture
+ CCIFG: C ngt Capture/Compare
0 Khng c tr hon ngt
1 C tr hon ngt
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VIII.3.4. TACCRx, Timer_A capture/compare

TACCRx: y l thanh ghi Timer_A Capture/Compare.

Ch Capture: TAR c copy vo thanh ghi TACCRx khi Capture c
s dng.
Ch Compare: Thanh ghi TACCRx cha d liu ca s so snh gi tr
Timer trong TAR.
VIII.3.5. TAIV, Timer_A Interrupt vector

TAIVx: Gi tr Vc t ngt Timer_A

00h Khng c tr hon ngt
02h C TACCR1 CCIFG
04h C TACCR2 CCIFG
06h c d tr
08h c d tr
0Ah C TAIFG
0Ch c d tr
0Eh c d tr
IX. B BIN I ADC10
IX.1. Gii thiu v ADC10
ADC10 l mt b bin i A-D 10 Bit c hiu sut cao. M un ADC10 lp t 10 bit
SAR core, B iu khin la chn mu, B sinh mu, B iu khin chuyn i d liu (
DTC).

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DTC cung cp cho ADC10 nhng mu c chuyn i v lu tr bt k ni u trong

b nh m khng c bt k s can thip no ca CPU. M un ADC10 c th c thit
lp bi ngi s dng cho nhng ng dng a dng.
ADC10 bao gm:
+ T l chuyn i ln nht hn 200 ksps.
+ Ly mu v gi vi chu k ly mu c th lp trnh c.
+ S chuyn i c khi to bi chng trnh hoc timer A.
+ Chng trnh la chn in p chun trn chip ( 1.5V hoc 2.5V ).
+ Chng trnh la chn s tham chiu bn trong hoc bn ngoi.
+ C 8 knh nhp tn hiu t bn ngoi ( 12 i vi MSP430x22xx).
+ C knh chuyn i cho cm bin nhit bn ngoi, Vcc, tham chiu bn ngoi.
+ La chn ngun xung clock chuyn i.
+ Nhn ADC v in p chun c cp xung mt cch ring r.
+ B chuyn i d liu lu tr kt qu chuyn i mt cch t ng.
IX.2. Hot ng ca ADC10
IX.2.1. Nhn ADC10 Bit
Nhn ADC10 chuyn i mt tn hiu vo tng t sang s 10 Bit v lu kt qu chuyn
i trong thanh ghi ADC10MEM. Nhn ADC10 s dng chng trnh la chn mc in
th ( VR+ v VR-) xc nh gii hn trn v gii hn di ca s chuyn i. Ng ra s
( NADC) c kch thc y ( 03FFh) khi tn hiu vo bng hoc nh hn VR+ v bng 0
khi tn hiu vo bng hoc nh hn VR-. Knh tn hiu vo v mc in p chun ( VR+ v
VR-) th c xc nh bi b nh iu khin chuyn i.
Kt qu chuyn i ADC s dng nh dng nh phn l:
NADC = 1023

Vin VR
VR VR

Nhn ADC10 c thit lp bi 2 thanh ghi iu khin l ADC10CTL0 v ADC10CTL1.

Nhn ADC10 c cho php bi Bit ADC10ON. C mt vi ngoi l l Bit iu khin
ADC10 c th b bin i khi ENC = 0. ENC phi c Set ln 1 trc khi c bt k s
chuyn i no c th xy ra.
S chn lc xung clock chuyn i:
ADC10CLK c s dng nh l xung clock chuyn i v b sinh chu k ly mu.
Ngun xung clock ca ADC10 c chn bi vic s dng Bit ADC10SSELx v c th
c chia t 1-8 s dng Bit ADC10DIVx. C th ngun ca ADC10CLK l SMCLK,
MCLK, ACLK v mt b dao ng bn trong l ADC10OSC.
Ngi s dng phi m bo rng ngun xung Clock c chn cho ADC10CLK phi
hot ng cho n khi s chuyn i kt thc. Khi ngun cp xung bt cht b mt khi
ang trong qu trnh chuyn i th s chuyn i s khng hon thnh v kt qu th s
b li.

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Hnh IX.1: S khi chc nng ADC10

IX.2.2. Tn hiu vo ADC10 v b ghp knh
C 8 tn hiu bn trong v 4 tn hiu bn ngoi tng t c chn nh l mt knh ca
s chuyn i bi b ghp knh tn hiu vo tng t. B ghp knh tn hiu vo l mt
kiu ngt ri ng lm gim tn hiu nhiu t nhng knh chuyn. B ghp knh tn
hiu cng l mt T-Switch lm ti thiu ha cc ghp ni gia cc knh. Nhng knh
khng c chn th b c lp t A/D v im ni trung gian th c ni mass
phn tn in dung nhm trnh s giao tip cho.
ADC10 s dng php phn b in tch. Khi tn hiu vo c chuyn mch bn trong,
s chuyn tip ny c th l nguyn nhn ca s qu trn tn hiu vo.

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Hnh IX.2: B dn knh tng t

S la chn cng tng t:
Nhng tn hiu vo bn ngoi ca ADC10 l Ax, VeREF+ v VeREF- th dng chung u
ni vi cc Port I/O mc ch tng qut, l nhng cng CMOS k thut s. Khi nhng
tn hiu tng t c t vo cc cng CMOS, dng nhiu i t Vcc n GND. Dng
nhiu ny xut hin nu in th vo c gi tr gn mc chuyn tip ca cng. Bit
ADC10AEx cung cp mt kh nng kha cc b m u vo v b m u ra.
; P2.3 on MSP430x22xx device configured for analog input
BIS.B #08h,&ADC10AE0 ; P2.3 ADC10 function and enable
IX.2.3. B sinh in p qui chiu
ADC10 tch hp in p qui chiu bn trong vi 2 s la chn mc in p. Thit lp
REFON = 1 th cho php qui chiu bn trong. Khi REF2_5 = 1 th qui chiu bn trong l
2.5V. Khi REF2_5 = 0 th qu chiu bn trong l 1.5V.
in p qui chiu bn ngoi c th cung cp cho VR+ v VR- tng ng cc chn A4 v
A3. Khi s dng in p bn ngoi hoc s dung Vcc qui chiu th nhng qui chiu
bn trong c th c tt i bo v ngun.
IX.2.4. Qu trnh bin i v ly mu

Hnh IX.3: Qu trnh ly mu

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Bin i A-D c bt u khi c xung cnh ln ca tn hiu vo SHI. SHI c la

chn bi bit SHSx t cc ngun:
- ADC10SC
- Timer_A 1
- Timer_A 0
- Timer_A 2
Bit ISSH dng o chiu tn hiu SHI. Bit SHTx dng la chn chu k ly mu l 4,
8, 16, hoc 64 ADC10CLK. nh thi ly mu thit lp SAMPCON mc cao cho vic
la chn chu k ly mu sau khi ng b vi ADC10CLK. Tsample l thi gian ly mu.
Khi SAMPCON t mc cao xung thp th qu trnh bin i A-D bt u.
Khi SAMPCON = 0 th tt c cc ng vo Ax c tng tr cao. Khi SAMPCON = 1 th
ng vo Ax ging nh mt b lc thong thp RC trong sut thi gian ly mu.

VI : in p vo chn Ax
VS : in p ngun bn ngoi
Rs : in tr ngoi
CI : in dung ng vo
Vc : in p t in
RI : in tr trong
Rs v RI nh hng n thi gian ly mu tsamlpe:
tsamlpe > (Rs+RI).ln(211).CI
Trong thc t th thi gian ly mu ln hn thi gian ly mu tnh ton v thi gian b
m n nh tREFBURST.
tsamlpe > tREFBURST
vi tREFBURST = SR.VRef 0.5ms
SR: tc qut b m ( 1s/V khi ADC10SR = 0 v 2 s/V khi ADC10SR = 1)
Vref: in p tham chiu ngoi
IX.2.5. Cc ch bin i
ADC10 c 4 ch hot ng v c la chn bi Bit CONSEQx.
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CONSEQx
00
01
10
11

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Ch bin i
Hot ng
Single channel single
bin i tng knh
Sequence-of-channels
bin i mt dy knh
Repeat single channel
bin i tng knh c lp li
Repeat sequence-of-channels bin i dy knh c lp li
Bng IX.1: Cc ch bin i

IX.2.5.1. Single-channel-single
Mi knh n c la chn bi INCHx v c bin i tng knh mt. Kt qu c
lu trong thanh ghi ADC10MEM. Bit ADC10SC dng kch hot s bin i. ENC
phi c o trng thi sau mi ln bin i.

Hnh IX.4: Lu bin i ch Single channel single

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IX.2.5.2. sequence-of-channels
bin i mt dy cc knh v knh bt u c la chn bi Bit INCHx, kt thc knh
A0. Kt qu c lu trong thanh ghi ADC10MEM. Bit ADC10SC dng kch hot s
bin i. ENC phi c o trng thi sau mi ln bin i.

Hnh IX.5: Lu bin i ch Sequence-of-channels

IX.2.5.3. Repeat-single-channel
Mi knh n c chn bi Bit INCHx c ly mu v bin i tip tc. Kt qu ADC
c lu trong ADC10MEM.

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Hnh IX.6: Lu bin i ch Repeat single channel

IX.2.5.4. Repeat-sequence-of-channels
Mt dy cc knh c ly mu v bin i tr li. Knh bt u c la chn bi Bit
INCHx, kt thc knh A0. Kt qu c lu trong thanh ghi ADC10MEM. Dy kt
thc knh A0 ln kch hot k tip s bt u li dy.

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Hnh IX.7: Lu bin i ch Repeat sequence-of-channels

IX.2.5.5. S dng Bit MSC
Khi MSC = 1 v CONSEQx > 0 th cnh ln u tin ca SHI s kch hot bin i. S
bin i vn tip tc cho n khi dy knh c bin i xong mc d trong qu trnh
bin i xut hin nhng xung cnh ln tn hiu kch hot SHI. Chc nng ca Bit ENC
khng thay i khi s dng Bit MSC.
IX.2.6. B iu khin chuyn giao d liu ADC10
ADC10 c mt b iu khin chuyn giao d liu ( DTC), n s t ng chuyn kt qu
ca bin i A-D t thanh ghi ADC10MEM sang b nh ca Chip. DTC c cho php
khi thit lp thanh ghi ADC10DTC1 c gi tr khc 0.
Khi DTC c cho php, mi khi ADC10 hon thnh vic bin i v lu kt qu vo
thanh ghi ADC10MEM th vic chuyn giao d liu c kch hot. Mi DTC yu cu
mt CPU MCLK. Trnh vic s dng cc Bus trong sut qu trnh chuyn giao d liu,
CPU c tm ngng. S chuyn giao khng c kch hot trong khi ADC10 th bn.

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IX.2.6.1. Ch chuyn giao mt khi

c kch hot khi Bit ADC10TB Reset. Gi tr n trong ADC10TC1 xc nh s lng
chuyn giao cho mt khi. a ch bt u ca khi l thanh ghi 16 Bit ADC10SA. a
ch kt thc l ADC10SA + 2n 2.

Hnh IX.8: Ch chuyn giao mt khi

a ch con tr bn trong c khi to bng ADC10SA v b m chuyn giao c
khi to bng n. DTC chuyn giao gi tr t ADC10MEM sang a ch con tr
ADC10SA. Sau mi ln chuyn giao th a ch con tr tng 2 v b m gim 1. DTC
tip tc chuyn giao t ADC10MEM cho n khi b m gim xung bng 0. Khi s
dung DTC trong ch chuyn giao mt khi th c ADC10IFG c Set sau mi khi
c chuyn giao hon thnh.

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Hnh IX.9:S chuyn giao d liu trong ch chuyn giao mt khi

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IX.2.6.2. Ch chuyn giao 2 khi

c chn khi Bit ADC10TB c Set. Gi tr n trong ADC10TC1 xc nh s chuyn
giao trong mt khi. a ch u tin trong thanh ghi ADC10SA. a ch kt thc ca
khi u tin l ADC10SA + 2n 2. Dy a ch ca khi th 2 c xc nh t SA +
2n n SA + 4n 2. a ch con tr bn trong c khi to bng ADC10SA v b m
chuyn giao c khi to bng n. DTC chuyn giao gi tr t ADC10MEM sang a
ch con tr ADC10SA. Sau mi ln chuyn giao th a ch con tr tng 2 v b m
gim 1. DTC tip tc chuyn giao t ADC10MEM cho n khi b m gim xung bng
0. thi im ny, khi th nht y, c ADC10IFG v Bit ADC10B1 th c Set.
DTC tip tc vi khi 2. B m chuyn giao bn trong t ng np li gi tr n. DTC bt
u chuyn kt qu bin i t ADC10MEM sang khi 2. Sau n ln chuyn giao hon
thnh th khi 2 y. C ADC10IFG Set, Bit ADC10B1 c clear.

Hnh IX.10: Ch chuyn giao hai khi

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Hnh IX.11: S chuyn giao d liu trong ch chuyn giao hai khi

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IX.2.6.3. Chu k thi gian chuyn i DTC

Bng IX.2: Chu k thi gian chuyn i DTC

IX.2.8. Ngt ADC10
Mt ngt v mt vc t ngt c ghp vi ADC10. Khi DTC khng c s dng (
ADC10DTC1 = 0), ADC10IFG c Set khi kt qu bin i A-D c ti xung
ADC10MEM. Khi DTC c s dng ( ADC10DTC1 > 0), ADC10IFG c Set khi s
chuyn giao mt khi c hon thnh v b m chuyn giao bng 0. Nu c hai Bit
ADC10IE v GIE c Set, ADC10IFG s sinh ra mt ngt yu cu. C ADC10IFG t
ng Reset khi ngt yu cu c duy tr hoc c th c Reset bng phn mm.

Hnh IX.12: H thng ngt ADC10

IX.3. Cc thanh ghi ADC10

Cc thanh ghi ca ADC10 c trnh by bng sau:

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Bng IX.3: Cc thanh ghi ADC10

IX.3.1. ADC10CTL0, ADC10 control register 0

+ SREFx: La chn tham chiu.

000 VR+ = Vcc v VR- = Vss
001 VR+ = VREF+ v VR- = Vss
010 VR+ = VeREF+ v VR- = Vss
011 VR+ = Buffered VeREF+ v VR- = Vss
100 VR+ = Vcc v VR- = VREF-/VeERF101 VR+ = VREF+ v VR- = VREF-/VeERF110 VR+ = VeREF+ v VR- = VREF-/VeERF111 VR+ = Buffered VeREF+ v VR- = VREF-/VeERF+ ADC10SHTx: Thi gian gi v ly mu
00 4 x ADC10CLKs
01 8 x ADC10CLKs
10 16 x ADC10CLKs
11 64 x ADC10CLKs

+ ADC10SR: Tc ly mu. Thit lp ADC10SR lm gim dng tiu th ca b m

qui chiu.
0 B m qui chiu h tr trn 200 ksps
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1 B m qui chiu h tr trn 50 ksps

+ REFOUT: Ng ra qui chiu.
0 Ng ra qui chiu tt
1 Ng ra qui chiu m
+ REFBURST: Truyn tng khi qui chiu
0 B m qui chiu lin tc
1 B m qui chiu ch trong qu trnh ly mu v bin i

+ MSC: T hp ly mu v bin i.
0 Qu trnh ly mu yu cu mt xung cnh ln ca SHI kch hot mi
ln ly mu v bin i.
1 Xung cnh ln u tin ca SHI s kch hot b nh thi ly mu.
Nhng ngoi ra, ly mu v bin i c s dng mt cch t ng n khi chu k bin
i c hon thnh.
REF2_5V: B sinh in p qui chiu. REFON phi c Set.
0 1.5V
1 2.5V
+ REFON: iu khin tham chiu.
0 Tt tham chiu
1 M tham chiu
+ ADC10ON: iu khin ADC10
0 Tt ADC10
1 Bt ADC10
+ ADC10IE: Cho php ngt ADC10
0 Khng cho php ngt
1 Cho php ngt
+ ADC10IFG: C ngt ADC10
0 Khng ngt
1 Ngt
+ ENC: Cho php bin i A-D
0 ADC10 khng c cho php
1 ADC10 c cho php
+ ADC10SC: Bt u bin i A-D.
0 Ly mu v bin i cha bt u
1 Bt u ly mu v bin i

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IX.3.2. ADC10CTL1, ADC10 control register 1

+ INCHx: La chn knh ng vo.

0000 A0
0001 A1
0010 A2
0011 A3
0100 A4
0101 A5
0110 A6
0111 A7
1000 VeERF+
1001 VERF-/VeERF1010 Cm bin nhit
1011 ( Vcc - Vss)/2
1100 ( Vcc - Vss)/2, A12 trn MSP430x22xx
1101 ( Vcc - Vss)/2, A13 trn MSP430x22xx
1110 ( Vcc - Vss)/2 , A14 trn MSP430x22xx
1111 ( Vcc - Vss)/2, A15 trn MSP430x22xx
+ SHSx: La chn ngun thi gian gi v ly mu.
00 ADC10SC
01 Timer A.OUT1
10 Timer A.OUT0
11 Timer A.OUT2
+ ADC10DF: nh dng d liu ADC10
0 Nh phn tiu chun
1 2s s b
+ ISH: o tn hiu gi v ly mu
0 Khng o tn hiu vo ly mu
1 o tn hiu vo ly mu
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+ ADC10DIVx: B chia
000 /1
001 /2
010 /3
011 /4
100 /5
101 /6
110 /7
111 /8
+ ADC10SSELx: La chn ngun xung Clock ADC10
00 ADC10OSC
01 ACLK
10 MCLK
11 SMCLK
+ CONSEQx: La chn ch bin i A-D
00 Single channel single
01 Sequence-of-channels
10 Repeat single channel
11 Repeat sequence-of-channels
+ ADC10BUSY: ADC10 bn
0 Khng hot ng
1 Tham chiu, ly mu, hoc bin i th hot ng
IX. 3.3. ADC10AE0, Analog enable control register 0

ADC10AE0x:
0 Khng cho php tn hiu vo tng t
1 Cho php tn hiu vo tng t
IX.3.4. ADC10AE1, Analog enable control register 1: ( ch c
MSP430x22xx)

ADC10AE1x:
0 Khng cho php tn hiu vo tng t
1 Cho php tn hiu vo tng t

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IX.3.5. ADC10MEM

Thanh ghi lu tr kt qu ca bin i A-D v c nh dng nh phn. Bit 10 n 15

lun l 0.
IX.3.6. ADC10DTC0

+ ADC10TB: La chn ch chuyn giao khi

0 chuyn giao 1 khi
1 chuyn giao 2 khi
+ ADC10CT:
0 Dng chuyn giao d liu khi mt khi hoc 2 khi c hon thnh
1 D liu c chuyn lin tc. DTC ch c dng nu ADC10CT c
clear hoc ADC10SA c ghi.
+ ADC10B1: Bit ny xc nh khi c lm y bi kt qu ca bin i A-D ca 2 ch
chuyn giao khi. ADC10B1 ch hp l khi c ADC10IFG c set ln u trong sut
hot ng DTC. ADC10TB cng phi c set.
0 Khi 2 y
1 Khi 1 y
+ ADC10FETCH: Bnh thng Bit ny c Reset
IX.3.7. ADC10DTC1

Bit ny xc nh s chuyn giao trong mi khi. Khi Bit ny bng 0 th DTC khng c
cho php.
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01h-0FFh s chuyn giao trn mt khi.

IX.3.8. ADC10SA

y l thanh ghi a ch bt u ca ADC10. Bit ny bt u a ch cho DTC. Bit 0 th

khng c s dng v lun c gi tr l 0.

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