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Fpga VHDL Xong
Fpga VHDL Xong
Li gii thiu
Khai thc, nghin cu c bn cng ngh mi l b-c khng th thiu trong
vic ci tin, nng cao, cng nh- ch to mi cc trang thit b qun s v dn s
nhm p ng vic hin i ho cng nghip ho ca t n-c. Cng vi s pht
trin v-t bc ca nghnh cng ngh thng tin, cc cng ngh mi v cc mch tch
hp vi in t, cc mch t hp logic lp trnh -c ra i lm cho cc sn phm
qun s cng nh- dn s ngy cng hon thin v -u vit hn. tin mt b-c xa
hn trong vic ci tin, ch to kh ti qun s nhm p ng chin tranh in t
hin i vi tc x l cc k cao, i hi phi c cng ngh tin tin ph hp vi
tnh hnh chung ca th gii.
Trn c s pht trin t cc chp PLA, hin nay cng ngh na n -c -a
vo ch to cc mch tch hp lp trnh -c FPGA v CPLD, n lm cho
mch tch hp logic ln n hng chc triu cng, tc ng h ln n 500 MHz.
ng dng cng ngh mi vo trong thit k ch to cc thit b in t lp trnh
PLIC l mt b-c cn thit cho t-ng lai vi mt n-c ang pht trin nh- Vit
Nam. p ng -c tnh bo mt trong qun s cng nh- tnh phn ng nhanh
trong chin tranh hin i cng vi nhu cu chuyn dng ho, ti -u ho (thi gian,
khng gian, gi thnh), tnh ch ng trong cng vic... ngy cng i hi kht
khe. Vic -a ra cng ngh mi trong lnh vc ch to mch in t p ng
nhng yu cu trn l hon ton cp thit mang tnh thc t cao. Cng ngh FPGA
(Field Programmable Gate Array) v CPLD (Complex Programmable Logic
Device) -c cc hng ln tp trung nghin cu v ch to, in hnh l Xilinx v
Altera. lm ch cng ngh mi v t chc thit k sn xut cng ngh FPGA
ca Xilinx cho php chng ta t thit k nhng vi mch ring, nhng b x l s
ring dnh cho ng dng ca chng ta. c bit trong lnh vc x l tn hiu s, cc
mch tch hp dng nhn dng m thanh, hnh nh, cm bin ... vi tnh mm do
cao v gi thnh thp.
Mc d cng ngh FPGA xut hin t nm 1985, xong i vi n-c ta th
n vn cn rt mi. Do vy tm hiu, lm ch v cng ngh FPGA l vic lm hon
ton cn thit. N khng ch c ngha i vi cc lnh vc in t - Vin thng,
cng ngh thng tin... m n c ngha c bit quan trng trong lnh vc an ninh
quc phng.
Xut pht t thc t i hi cp bch , b mn T ng v K thut tnh
Khoa K thut iu khin Hc Vin K thut qun s cho xut bn cun sch
Thit k thit b in t lp trnh s dng cng ngh FPGA v CPLD, ti liu ny
nm trong lot cc ti liu -c b mn n hnh, bao gm Cu trc my tnh,
Cu trc v lp trnh cho cc h x l tn hiu s, cu trc v lp trnh h vi iu
khin.
Ti kiu gii thiu ph-ng php thit k CPLD, FPGA cng nh- ngn ng lp
trnh, t i su nghin cu cc gii php c lin quan cng nh- cc cng c h
tr thit k, sau p dng thit k, tch hp vo loi CPLD v FPGA c th . Ti
liu -c chia thnh 4 ch-ng:
- Ch-ng 1: Gii thiu tng quan t chc phn cng ca ASIC. Gii thiu
tng quan t chc cc h thit b cng nh- cu trc ca chng (ti liu gii thiu cu
trc ASIC ca hng Xilinx).
- Ch-ng 2: Gii php v t chc phn mm m bo. Gii thiu cc phn
mm h tr thit k, ngn ng lp trnh.
- Ch-ng 3: Ngn ng lp trnh VHDL
- Ch-ng 4: Thit k ng dng c bn. Ch-ng ny -c thc hin vi vic
tch hp cc mch in t trn c s s dng ngn ng VHDL, thit k b iu
khin ng c b-c trn hai h thit b CPLD v FPGA.
Cun sch -c dng lm gio trnh ging dy bc i hc v sau i hc
chuyn ngnh in, in t hoc lm ti liu tham kho cho cc nghin cu sinh v
cho nhng ai quan tm n cu trc v lp trnh ASIC.
Cun sch -c bin son bi PGS. TS. Nguyn Tng C-ng v TS. Phan
Quc Thng, ThS. Phm Tun Hi, KS L Trng Ngha, do PGS. TS. Nguyn Tng
C-ng ch bin.
Nhn dp ny, tp th tc gi xin by t li cm n chn thnh nht n nhng
ng-i c nhiu ng gp trong qu trnh hon thnh ti liu, n cc anh ch em
B mn T ng v K thut tnh thuc Khoa K thut iu khin, Hc vin K
thut Qun s, c bit phi k n s h tr hiu qu ca TS. nh Ngha.
Do kinh nghim v thi gian hn ch, ti liu ny chc chn khng th trnh
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Cng dng
Tn hiu u cui (ln ti 622 Mbps) - Cho php kt ni cc chp ang dng
nh dng theo cc chun LVTTL, vi cc chip, b nh khc, v t cc chip
LVCMOS, GTL, GTL+, PCI, HSTL-I, II, ang dng ti cc chun tn hiu mch
III, SSTL- I, II .
B qun l ng h s ( DCM )
- Loi tr s gi chm ng h mc
board v on-chip, nhn chia tc th, c
th gim -c tc ng h ph hp
mc board, gim s b ng h trn bo
mch. C th iu chnh pha ng h
m bo chnh xc cao .
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vic in p 2.5 Volt (XC9500 XV), 3.3 Volt (XC9500 XL), 5 Volt (XC9500 ).
Cc thit b ny cho php lp trnh mc h thng ISP, iu ny cho php s
dng li cc thit k trong sut thi gian th mu, g ri h thng, nng cp, test
tr-c khi xut x-ng.
Da vo cc k thut x l tin tin, h XC9500 -a ra s bo hnh nhanh
(Ch cn file ch-ng trnh -c ng gi v np li), cho php kho chn ng-i
dng, giao tip -c vi chun JTAG. Tt c cc h XC9500 c c tnh tin cy
tuyt vi vi 10.000 ln np xo v l-u tr d liu trong vng 20 nm.
- H XC9500 5 V : L mt trong s 6 thit b di t 36 n 288 Macrocell vi
cc kiu ng gi chn a dng. Cc chn vo ra cho php giao tip trc tip vi h
thng 3V v 5 V (VccIO - chn giao tip ng-i dng), vi cc phin bn mi n tr
nn rt d s dng vi cc ng gi theo kiu CSP (Chip Scale Package), BGA (Ball
Grid Array) v cho php truy cp n 192 tn hiu.
* Cu trc kho chn linh hot :
Cng vi phn mm fitter -a ra kh nng nh tuyn ln nht, mm do
trong thc thi. Vi cu trc c giu c tnh, cho php -a ra nhiu tch s nhn
ring bit, c ba b ng h ton cc, c nhiu tch s nhn trn u ra hn cc loi
CPLD khc.
Cc tnh nng v cu trc ca loi ny rt thch nghi vi vic sa i thit k
trong qu trnh thit k.
* Tr gip g ri v pht trin giao tip vi JTAG IEEE 1149.1: Giao tip
JTAG ca h XC9500 thng minh hn bt c h CPLD no c mt trn th tr-ng.
N c cc c tnh chun h tr k thut hi vng, ly mu, kim tra m rng.
Hn na n gm c cc ch dn qut bin m cc loi CPLD khc khng c,
n bao gm INTEST (dng cho kim tra chc nng ca thit b ), HIGHZ ( dng
cho k thut hi vng ).
H XC9500 5V ny -a ra nhiu chun cng nghip pht trin th h th ba,
cc cng c g ri nh- Corelis , JTAG, Assert Intertech.
Cc cng c ny cho php bn pht trin cc vc t test vng bin phn tch
s nh h-ng ln nhau, test, g ri li h thng.
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Cng dng
in p v d chuyn i mc.
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- C in tr treo u cui .
- Mm do trong thit k .
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dng n gin, chng hn nh- vng kho pha, FIFO, cc b chuyn i vo ra, iu
khin Bus h thng, cc thnh phn ny khng th thiu hon thin mt thit
k m n -c dng tr-c y.
- H Spartan-IIE l n by c bn cho cc tnh nng v cu trc ca Virtex-E
-a ra nhng tnh nng ni tri hn. Cu trc CLB (Configurable Logic Block Khi logic cho php nh cu hnh) c cha RAM -c phn phi thc hin cc
chc nng logic c bn.
- Bn DLL ( Delay Locked Loop ) vng kho gi chm -c s dng cho
b qun l ng h v c th thc hin clock i xng lch v cc php nhn clock,
chia clock. Clock i xng lch c th -c thc hin bn ngoi (Mc board) hoc
bn trong chip ( Mc c bn ).
- Cc khi Block RAM gm 4Kb cho mi khi c th -c sp xp rng t
1 n 16 bit.
- c tnh Select I/O cho php giao tip vi nhiu chun khc nhau thc thi
trong cc vng kt ni vi cc chip c chun IO khc nhau, kt ni chip vi b nh,
kt ni chip vi cc giao tip n.
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cung cp bi ng-i dng chng hn nh- Vref. Tr-ng hp ny, cc chn I/O ng-i
dng -c xp t t ng nh- cc u vo cho in p ly mu Vref. Khong mt
trong 6 cc chn vo ra ca cc Bank ng vai tr ny.
- Cc chn Vref trong mt bank -c ni bn trong v v vy ch mt in p
Vref c th -c s dng trong mi bank .Tt c cc chn Vref trong cc bank cn
phi -c ni vi ngun in p bn ngoi chng hot ng ng.
c s trao i nhanh gia cc tn hiu, cc chn tn hiu u vo cn phi
-c cung cp tr-c khi ngun cp vo chn Vccint v chn Vcco v phi m bo
khng c -ng dn dng ng-c t cc chn I/O quay v in p ngun cung cp
Vccint v Vcco (C ngha l m bo cho thit b c th hot ng mt in p v
giao tip mt in p, hai in p ny c th khc nhau ).
Configurable Logic Blok v Logic Cell:
- Cc n v c bn ca CLB (Khi logc cho php nh cu hnh) thuc h
thit b Spartan-IIE chnh l cc Logic Cell ( LC - Xem hnh 1.5 v hnh 1.6 mc 1.1
ch-ng I ). Mi mt Logic Cell bao gm mt b to chc nng (Hay b to hm)
gm 4 u vo, phn t logic nh v phn t l-u tr (Flip-Flop loi D).
- u ra ca b to chc nng ca mi Logic Cell iu khin c u ra CLB
hoc u vo D ca Flip-Flop.
- Mi mt CLB c cha bn Logic Cell v -c t chc thnh hai Slice t-ng
t nhau, mt slice n c dng nh- (hnh 1.12).
- Thm vo bn b LC c bn, cc CLB ca Spartan-IIE c cha phn t logic
m n kt hp vi cc b to chc nng -a ra cc chc nng 5 hoc 6 u vo .
Look-Up tables (LUT):
- Cc b to chc nng ca Spartan -IIE thc hin nh- LUT c bn u vo.
hot ng nh- mt b to chc nng, mi mt LUT c th cung cp mt RAM
16x1bit ng b.
- Hn na hai LUT trong mt Slice c th -c kt hp to mt RAM 16x2
bit hoc 32x1 bit ng b .
Storage Element:
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Hnh 1.12 .Cu trc Logic Cell hay mt Slice n trong Spartan -IIE
- Cc phn t l-u tr trong slice ca Spartan-IIE c th -c xem nh- mt
Flip-Flop loi D kch hot bng s-n, hoc nh- mt b cht nhy mc. Cc u vo
D c th -c iu khin hoc bi b to chc nng trong slice hoc trc tip t u
vo cc slice (b qua b to chc nng). Thm vo cc -ng Clock (CLK) v Clock
Enable (CE) (hnh 1.12), mi Slice c cc tn hiu set v reset ng b (SR v BY).
-ng SR p cc phn t l-u tr v trng thi khi to, c bit trong tr-ng hp
nhi cu hnh. -ng BY p phn t l-u tr v trng thi ng-c li. C th la chn
hai -ng ny chng hot ng khng ng b.
Tt c cc tn hiu iu khin c th o ng-c mt cch hon ton c lp v
chng -c chia s bi hai Flip-Flop trong mt Slice.
Arithmetic Logic: B dn knh F5IN trong mi Slice -c kt hp vi cc
u ra b to chc nng -c ch ra hnh 1.13.
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I/O Cell :
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M t tm tt:
- M phng chc nng : Ti giai on ny, s phng chc nng ch kim tra
nhng t hp ng ca khng v mt m mch nguyn l -a ra. Ng-i thit k s
-a ra ch dn s m phng v thi gian ngay sau theo cc b-c trong lung thit
k ny. Nu nh- c chc nng no khng ng, cn phi quay li s nguyn l
hoc file HDL (Xem hnh 1.26) v sa i li, to li file Netlist v sau cho chy
li b m phng. Nhng ng-i thit k th-ng mt khong 50% thi gian vo vic
sa i i qua b-c ny cho n khi thit k t theo yu cu mong mun . Vic
s dng file HDL c rt nhiu thun li khi kim tra thit k : Ng-i thit k c th
m phng trc tip t file ngun HDL, iu ny cho php b qua thi gian tiu tn
trong qu trnh tng hp m thi gian ny th-ng -c yu cu mi khi thay i
thit k. Mt thit k khi lm vic ng, chy cng c tng hp to ra file
Netlist cho cc b-c tip theo trong qu trnh thit k .
- Thc thi trn thit b : Mt file Netlist cu thit k m t hon ton y
mt thit k m thit k ny s dng th- vin cc cng ca nh phn phi ca mt
h thit b no v t nht n cng i qua b-c kim tra. n lc -a file
ny vo trong mt chip v iu ny -c xem nh- s thc hin trn thit b.
Bin dch bao s gm nhiu ch-ng trnh s -c s dng, cc ch-ng trnh
ny nhp file Netlist ca thit k -c dch v dng n b tr, xp xp cc
cng logic. Cc ch-ng trnh ny s khc nhau vi cc nh phn phi th- vin khc
nhau.
Cc ch-ng trnh tham gia vo qu trnh bin dch bao gm: Ch-ng trnh ti
-u ho, dch cc phn t ca thit b vt l, kim tra cc qui lut thit k vi thit b
c th no (xem n c v-t qua s b m Clock cho php trong thit b ny
khng ?... ).
Trong sut giai on thit k, ng-i thit k s -c hi chn thit b ch,
ng gi, cp v cc chn la khc i vi thit b -c n nh . Thng th-ng
qu trnh bin dch kt thc vi mt bo co kt qu bao hm ton b cc ch-ng
trnh -c thc hin. Thm vo cc cnh bo li, dng bn k ca thit b v
vic s sng cc -ng vo ra. Chnh iu ny gip ng-i thit k la chn -c
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thit b ch tt nht.
- Lp t trn thit b: i vi h CPLD th b-c ny -c gi l lp t, c
ngha l -a thit k vo trong thit b ch (iu chnh cho ph hp vi ngun ti
nguyn ca thit b ch). Trong hnh v 1.26 trn, c mt phn ca thit k -c
gi l lp t vo trong CPLD. Cc CPLD c cu trc c nh , v th nn phn mm
cn ly cc cng v cc -ng ni ph hp vi mch thit k. Cng vic ny th-ng
-c phn mm x l rt nhanh bng phn mm. Mt vn khc na c kh nng
xy ra l vic gn v tr ca cc chn vo ra (Th-ng -c gi l s kho chn I/O)
c th b thc hin tr-c. Th-ng th iu ny hay xy ra khi dng li mt thit
k m thit k ny -c tha h-ng, hoc thit k ny -c np vo board mch
in ca thit k no .
Cc cu trc m n cung cp vic kho cc chn vo ra (chng hn nh- XC
9500, CoolRunner CPLDs ) c s thun tin rt ln . Chng cho php gi li cc
chn vo ra gc, bt k thit k thay i hay c s tn dng no , hoc c s thc
hin theo yu cu no . S kho chn rt quan trng khi s dng ISP (In system
Programmable Device - Cho php lp trnh trong h thng), nu mch in v v
ni vi cc chn vo ra, sau thit k b thay i v np li ch-ng trnh, bn hy
yn tm l cc chn ny vn -c gi nguyn .
- Sp t v nh tuyn :
Vi h FPGA, ch-ng trnh xp t v nh tuyn -c chy sau khi bin dch.
Xp t chnh l qu trnh chn la cc module c th hoc cc khi logic trong
FPGA ni m cc cng ca thit k s nm trong .
nh tuyn n mang ng ngha ca n, chnh l vic ni vt l cc -ng
ni gia cc khi logic. Hu ht cc nh phn phi cung cp cng c t ng sp t
v nh tuyn, v th bn khng phi lo lng v cc chi tit kh hiu phc tp ca
cu trc thit b.
Mt s nh phn phi -a ra cng c cho php bn sp t v nh tuyn bng
tay nhng phn then cht nht ca thit k, c th thu -c s thc hin tt hn
cng c t ng.
B to s mt bng b tr cc phn t logic l mt kiu ca cng c s dng
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bng tay.
Ch-ng trnh sp t v nh tuyn cn nhiu thi gian nht hon thin
thnh cng mt thit k, bi v n l cng vic rt phc tp xc nh ni t
nhng thit k ln v m bo rng chng -c ni vi nhau chnh xc v p ng
-c s thc hin nh- mong mun.
Tuy nhin cc ch-ng trnh ny ch c th lm vic tt nu cu trc ca thit b
ch c s nh tuyn ph hp vi thit k.
Bn khng th sa m ch-ng trnh b mt cu trc -c hnh thnh sai
lch, c bit nu cu trc ca thit b khng nh tuyn cc -ng ni. Nu
nh- gp phi vn ny, th gii php chung nht l chn mt thit b ch ln hn.
Mt b phn tch thi gian tnh thng th-ng l mt phn ca phn mm thc
thi ca nh phn phi. N cung cp thng tin v thi gian ca cc -ng dn trong
thit k, thng tin ny rt chnh xc v c th hin th theo nhiu cch khc nhau.
Chng hn nh- hin th tt c cc -ng ni v xp loi chng t gi chm
di nht n gi chm ngn nht.
Hn na khi ny bn c th s dng thng tin xp t -c chi tit ho sau
khi nh dng v quay tr v b m phng -c chn vi cc thng tin chi tit v
thi gian.
Qa trnh ny -c gi l ch thch ng-c (hay thng tin phn hi), n c s
thun li trong vic cung cp chnh xc thi gian ca s thc hin cc s khng v
cc s mt trong thit k cu bn. Trong c hai tr-ng hp, thi gian phn nh s
gi chm ca cc khi logic cng nh- cc -ng ni.
B-c thc hin cui cui cng l ti hay np cu hnh xung thit b.
- Ti hay np ch-ng trnh:
Ti ch-ng trnh nhn chung -c xem nh- l ti thng tin xung thit b d
bin i nh- SRAM FPGA . ng vi tn gi ca n, bn ti thng tin cu hnh
thit b vo trong b nh ca thit b.
Lung cc bit m n -c truyn i c cha tt c cc thng tin nh ngha
logic v cc -ng ni cu thit k, thng tin ny s l khc nhau i vi thit k
khc nhau. Xem hnh 1.27.
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Ch-ng II
Gii php v t chc phn mm m bo
2.1. Gii thiu s l-c
Thit k logic lp trnh -c -a ra k nguyn m trong mt ca thit
b n v hng triu cng, s thc hin ca h thng tc hng trm MHz.
Xilinx -a ra cc cng c thit k in t hon ton y m n cho php
thc hin cc thit k trong h PLD ca Xilinx. Cc gii php pht trin kt hp vi
cc k thut mnh to ra mt s linh hot, mm do, giao tip ho d s dng
gip bn c -c cc thit k tt nht c th trong mt d n ln - m khng cn
quan tm n kinh nghim ca bn. Cng c phn mm thit k ISE (Integrated
Sofware Enviroment- Mi tr-ng phn mm tch hp) l cng c thit k tng th,
bao hm cc cng c phn mm thit k chuyn dng khc nhau v y cng l
cng c -c s dng nhiu nht trong thit k cc PLD (Programmable Logic
Device) ca Xilinx.
Constraint Editor), Architecture Wizard (DCM-Digital Clock Management, MGTMulti_Gigabit Transceiver), Xilinx System Generator for DSP.
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1. Nhp thit k: Chn Start-> Program-> Xilinx ISE 6-> Project Navigator.
Chn New Project trong menu File, t project l Traffic v t trong th- mc
Traffic.
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.Ko v th vo ca s
Hnh 2.23. Cc nhm trng thi sau khi son tho xong
Kch chut vo nt Generate HDL c biu t-ng
. Hp thoi thng bo
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clock : IN std_logic;
reset : IN std_logic;
count : INOUT std_logic_vector(3 downto 0));
END COMPONENT;
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Tip tc, thc hin t-ng t trong ca s Sources in Project chn file
stat_mac.vhd, trong ca s Source nhy p vo View VHDL Instantiation
Template. Copy phn khai bo Component v phn Instantiation dn vo file
top.vhd. Khai bo mt Signal timer : std_logic_vector (3 downto 0) d-i khai bo
cu trc . Sau khi thc hin cc b-c ta s c ch-ng trnh ca lp top nh- sau.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( clock : in std_logic;
reset : in std_logic;
red_light : out std_logic;
amber_light : out std_logic;
green_light : out std_logic);
end top;
architecture Behavioral of top is
signal timer : std_logic_vector (3 downto 0);
COMPONENT counter
PORT (
clock : IN std_logic;
reset : IN std_logic;
count : INOUT std_logic_vector(3 downto 0));
END COMPONENT;
COMPONENT stat_mac
PORT (TIMER : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
RESET : IN std_logic;
AMB : OUT std_logic;
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, sau ni hai
-ng clock v reset ca hai khi li, -ng count ni vi -ng timer. Sau chn
Add Net Name c biu t-ng ch abc
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b ch m khng c li.
Hnh 2.33. Cc thng bo hon thnh vic bin dch trong ca s Process
Khi ny b phn tch thi gian cng -c t ng thc hin v ch-ng trnh
-a ra cc thng bo ca Fitter v Timing. Lc ny bn c th xem cc thng bo v
li, v logic, u vo, u ra, danh sch cc chn...bng vic kch vo cc dng
thng bo bn tri trong ct Fitter Report.
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k d-i dng VHDL sang file Nestlist c ui '.NGC '. B-c thc thi s ly file ny
v file rng buc ng-i dng to li thit k m n s dng cc ti nguyn cho
php trong FPGA. Sau qu trnh xp xp s phn chia thit k vi cc ti nguyn
cho php trong FPGA, n s dng file .UCF qun l thi gian -c gn v quyt
nh -a ra xem c th -a thm hoc ti to li cc n v logic ph hp vi thi
gian -c yu cu. Cc b-c thc thi trn FPGA gm bn b-c c bn sau y:
- Tng hp thit k
- Lp t
- M phng thi gian
- Np ch-ng trnh
Trong mc ny chng ta s tip tc i thc thi v d b iu khin n tn hiu
giao thng trn Spartan-3 FPGA. Quay li thit k vi CPLD trong ca s Sources
ca Project Navigator nhy p vo dng xc2c256-7tq144-XST VHDL v chn
cc thng s ca FPGA nh- hnh sau.
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Ch-ng III
Gii thiu ngn ng VHDL
3.1. Cc cu trc c bn ca ngn ng VHDL.
Cc thnh phn chnh xy dng trong ngn ng VHDL -c chia ra thnh nm
nhm c bn nh- sau:
- Entity
- Architecture
- Package
- Configuration.
- Library.
Entity: Trong mt h thng s, thng th-ng -c thit k theo mt s xp
chng cc modul, m mi Modul ny t-ng ng vi mt thc th thit k ( -c gi
l Entity ) trong VHDL. Mi mt Entity bao gm hai phn :
- Khai bo thc th ( Entity).
- Thn kin trc ( Architecture Bodies )
Mt khai bo Entity -c dng m t giao tip bn ngoi ca mt phn t
(component), n bao gm cc khai bo cc cng u vo, cc cng u ra ca phn
t . Phn thn ca kin trc -c dng m t s thc hin bn trong ca thc
th .
Packages: Cc ng gi ch ra thng tin dng chung, m cc thng tin ny
-c s dng bi mt vi Entity no .
Configuration: nh cu hnh, n cho php gn kt cc th hin ca phn t
no cn dng ca mt thit k no c dng mt cu trc v -a cc th hin
ny vo trong cp Entity v Architecture.
N cho php ng-i thit k c th th nghim thay i cc s thc thi khc
nhau trong mt thit k. Mi mt thit k dng VHDL bao gm mt vi n v thvin, m mt trong cc th- vin ny -c dch sn v ct trong mt th- vin thit k.
79
80
81
c )
D <= C + 1; -- ( Cu lnh sai : C l cng u ra nn khng th -c c cho
u vo ).
end process;
end bhv;
* V d v khai bo Entity:
A
COUT
FULL_ADDER
CIN
SUM
Cc
cng ny c kiu d liu l kiu Bit, cn cc cng u ra SUM v COUT cng mang
kiu d liu l kiu BIT. Ngn ng VHDL dng din t giao din ny nh- sau:
Entity FULL_ADDER is
port ( A, B, CIN : in BIT;
SUM, COUT : out BIT );
End FULL_ADDER ;
Chng ta c th iu khin cu trc cng nh- thi gian ca mt Entity bi vic
s dng cc hng generic. V d sau s ch ra vic iu khin ny, trong v d ny
hng N -c dng ch ra s bt ca mt b cng. Trong qu trnh m phng hoc
qu trnh tng hp, gi tr thc t cho mi hng dng chung generic c th b thay
i.
entity ADDER is
generic (N : INTEGER := 4);
82
M : TIME := 10ns);
port ( A, B : in BIT_VECTOR (N -1 downto 0 );
CIN :in BIT;
SUM : out BIT_VECTOR (N-1 downto 0);
COUT : out BIT );
end ADDER;
Giao din m t b cng ny nh- sau:
A (3)
B (3)
COUT
A (2)
B (2)
A (1)
B (1)
A (0)
B (0)
CIN
FULL _ ADDER
SUM (3)
SUM (2)
SUM (1)
SUM (0)
83
end [ architecture_name ];
3.1.2.1. Kin trc theo kiu hnh vi hot ng ( Behavioral ):
Mt kin trc kiu hnh vi hot ng ch ra cc hot ng m mt h thng
ring bit no phi thc hin trong mt ch-ng trnh, n ging nh- vic din t
cc qu trnh hot ng, nh-ng khng cung cp chi tit m thit k -c thc thi
nh- th no. Thnh phn ch yu ca vic din t theo kiu hnh vi trong VHDL l
process. D-i y l v d ch ra kiu din t theo kiu hnh vi ca mt b cng vi
tn l FULL_ADDER.
84
85
L1
L2
X1
SUM
A1
CARRY
package EXAMPLE_PACK is
type SUMMER is ( MAY, JUN, JUL, AUG, SEP);
component D_FLIP_FLOP
port (D, CK:in BIT;
Q, QBAR: out BIT)
end component;
constant PIN2PIN_DELAY:TIME:=125ns;
function IN2BIT_VEC(INT_VALUE:INTEGER)
return BIT_VECTOR;
end EXAMPLE_PACK;
v d ny tn ca package -c khai bo l EXAMPLE_PACK. N c cha
86
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.all
Entity RX is.........
Mnh library DESIGN_LIB cho php th- vin thit k DESIGN_LIB -c
php dng trong phn m t ny, iu c ngha l tn DESIGN_LIB c th -c
s dng. Mnh use tip theo s ly tt c cc khai bo c trong Package
EXAMPLE_PACK vo trong khai bo Entity ca RX. C ngha l ta c th chn
la cc khai bo t trong mt cc khai bo ca mt ng gi vo trong mt n v
thit k khc. V d :
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.D_FLIP_FLOP;
use DESIGN_LIB.EXAMPLE_PACK.PIN2PIN_DELAY;
architecture RX_STRUCTURE of RX is.........
Hai mnh use v d ny nhm to ra khai bo cho D_FLIP_FLOP v khai
bo hng cho PIN2PIN_DELAY -c php s dng trong thn kin trc.
3.1.3.2. Phn khai bo thn Package.
S khc bit gia khai bo Package v thn Package c cng mc ch nhkhai bo ca mt Entity v phn thn kin trc Architecture ca chng. C php
khai bo ca Package -c khai bo nh- sau:
package package_name is
{package_declarative_item}
end [package_name ];
package body package_name is
{package_declarative_item}
87
end [package_name]
Mt thn package -c dng l-u cc nh ngha ca mt hm v th tc,
m cc hm v th tc ny chng -c khai bo trong phn khai bo package
t-ng ng. V vy phn thn package lun -c kt hp vi phn khai bo ca
chng, hn na mt phn khai bo package lun c t nht mt phn thn package
kt hp vi chng.
V d : package EX_PKG is
subtype INT8 is integer range 0 to 255;
constant zero : INT8:=0;
procedure Incrementer (variable Count : inout INT8);
end EX_PKG;
package body EX_PKG is
procedure Incrementer (variable Data : inout INT8) is
begin
if (Count >= MAX ) then
Count:=ZERO;
else Count:= Count +1;
end if;
end Incrementer;
end EX_PKG;
88
{configuration_item}
end for;
Vi mt Entity ca b cng FULL_ADDER nh- gii thiu phn trn, v
d ny ta c th s dng chng trong php nh cu hnh nh- sau:
configuration FADD_CONFIG of FULL_ADDER is
For STRUCTURE
for
HA1,
HA2
HALF_ADDER
use
entity
burcin.HALF_ADDER(structure);
for OR1: OR_GATE use Entity burcin.OR_GATE;
end for;
end FADD_CONFIG;
y tn ca php nh cu hnh l tu , v d ny ta ly tn l
FADD_CONFIG, cn vi dng lnh For STRUCTURE ch ra kin trc -c nh
cu hnh v -c s dng vi thc th Entity FULL_ADDER. Gi s rng chng ta
dch hai thc th HALF_ADDER v OR_GATE thnh th- vin vi tn l burcin
v s dng chng trong v d trn.
89
Package my_pkg is
constant delay: time:=10ns;
end my_pkg;
Tip n chng ta gi my_pkg s dng chng trong thit k d-i y:
90
91
type
DAY
is
TUESDAY,WEDNESDAY,THURDAY,FRIDAY);
type STD_LOGIC is ('U','X','0','1','Z','W','L','H','_');
(MONDAY,
92
93
d-ng.
- BIT_VECTOR : -c dng miu t mt mng cc gi tr kiu BIT.
- STRING : Mt mng cc k t, mt gi tr kiu chui -c i km bi du
ngoc kp.
- REAL: -c dng m t cc kiu s thc, di hot ng t-1.0E+38 n
+1.0E+38.
- Kiu thi gian vt l : M t cc gi tr thi gian -c dng trong m phng.
C mt vi kiu d liu -c nh ngha trong gi STANDARD nh- sau:
94
V d :
type A1 is array ( 0 to 31) of INTEGER;
type Bit_Vector is arrray (NATURAL range <>) of BIT;
type STRING is array (POSITIVE range <>) of CHARACTER;
A1 l mt mng gm ba hai phn t m trong mi phn t l mt kiu
nguyn. Mt v d khc ch ra kiu Bit_vector v kiu String -c to ra trong chun
cc gi STANDARD.
V d : subtype B1 is BIT_VECTOR ( 3 downto 0);
variable B2 : BIT_VECTOR (0 to 10);
Di ch s xc nh s phn t trong mng v h-ng ca chng ( low to high |
high to low ).
VHDL cho php khai bo cc mng nhiu chiu c th dng khai bo
cc mu RAM v ROM. Xem v d d-i y:
type Mat is array (0 to 7, 0 to 3) of BIT;
constant ROM : MAT : = (( '0', '1', '0', '1'),
('1', '1', '0', '1' ),
('0', '1', '1', '1' ),
('0', '1' , '0', '0' ),
('0', '0' ,'0' , '0'),
('1', '1' , '0', '0' ),
('1', '1' , '1', '1' ),
('1', '1' , '0', '0' );
X := ROM (4,3);
Bin X s ly gi tr '0' -c t m.
95
96
Library IEEE;
USE IEEE.STD_LOGIC_1164.all;
vi kiu
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_BIT.all;
use IEEE.NUMERIC_STD.all;
3.3.8. Cc kiu con .
VHDL cung cp cc cc kiu con m cc kiu con ny chng -c nh ngha
trong cc nh- cc tp ph trong mt kiu khc. Bt c u c mt khai bo kiu
th c th xut hin mt nh ngha kiu con. Kiu NATURAL v kiu
POSITIVE l mt kiu ph hay kiu con ca kiu nguyn v chng c th -c
dng vi bt k mt hm nguyn no.
V d :
97
Mc -u
tin thp
Cc ton t
Cc ton hng
nht
.
and
Logical_operator
or
nand
Cng kiu
Cng kiu
Cng kiu
nor
Cng kiu
xor
Cng kiu
Cng kiu
/=
Cng kiu
<
Cng kiu
<=
Cng kiu
>
Cng kiu
>=
Cng kiu
.
.
Relational
operator
concatenation_op
erator
&
+
Cng kiu
arithmetic_operat
Cng kiu
arithmetic_operat
Bt k kiu s no
Bt k kiu s no
or
or
arithmetic_operat
or
Mc -u
tin cao
arithmetic_operat
or
nht
Logical_operator
Cng kiu
Cng kiu
mod
integer
rem
integer
**
Kiu m integer
abs
Bt k kiu s no
not
Cng kiu
98
Kiu ton t logic khng chp nhn cc ton hng l cc kiu tin nh ngha
nh- kiu BIT, BOOLEAN v cc kiu mng cc bit, cc ton hng cn phi l cng
kiu v cng di.
V d :
99
3.5.1. Kiu ch .
Cc kiu ch c th chia ra thnh hai nhm chnh :
- Kiu v h-ng
. Kiu k t
. Kiu BIT
. Kiu chun STD_LOGIC
. Kiu Boolean
. Kiu s thc
. Kiu nguyn
. Kiu thi gian
- Kiu mng
. Kiu chui
. Kiu BIT_VECTOR
. STD_LOGIC_VECTOR
3.5.1.2. Kiu ch k t .
Kiu ch k t ch ra mt gi tr bng vic s dng mt k t n v km theo
mt du ngoc n. Nhn chung VHDL khng quan tm n cc tr-ng hp ch
th-ng v ch hoa, xong vi kiu ch k t cn phi phn bit ch th-ng v ch
hoa. V d : 'a' hon ton khc vi kiu 'A' trong kiu ch k t. Kiu ch k t c
100
101
" C s_n # s
102
3.5.3.Kiu INDEX.
Kiu INDEX -c s dng ch ra mt phn t no trong mt mng. C
php s dng ca khai bo ny nh- sau:
array_name (expression)
Vi array_name l mt tn ca mt hng hay mt bin no nm trong mt
mng. Cn expression phi tr v gi tr nm trong di ch s ca mng .
V d :
type memory is array ( 0 to 7 ) of INTEGER range 0 to 123;
variable DATA_ARRAY : memory;
variable ADDR : INTEGER range 0 to 7;
variable DATA: INTEGER range 0 to 123;
DATA:= DATA_ARRAY ( ADDR );
103
-- Tr v gi tr l 10.
A1' right
-- Tr v gi tr 0.
A1' high
-- Tr v gi tr l 10.
A1' low
-- Tr v gi tr l 0.
-- Tr v gi tr l 11.
3.5.6. Kiu tp hp :
Kiu tp hp c th -c dng gn gi tr cho mt i t-ng thuc kiu
mng hoc kiu Record trong khi khi to khai bo hoc trong cc pht biu gn.
V d : type color_list ( red, orange, blue, white );
type color_array is array (color_list) of BIT_VECTOR ( 1 downto 0 );
variable X : color_array;
X := (" 00 " , " 01 " , " 10 " ," 11 " );
X := ( red => "00" , blue => "01" , orange => "10" , white => "11" );
Trong dng th hai, chng ta nh ngha mt mng m s cc phn t ca
chng ( di ch s ) -c -a ra bi color_list. T color_list chng ta c mt mng
gm bn phn t v mng color_array cng s bao gm bn phn t, m mi phn
t ny li -c nh ngha bi kiu Bit_Vector. Hn na chng ta s dng di ch s
ca mng color_list s c di t 0 n 3, v vic nh ngha ca mng ny ch ch ra
di ch s ch khng ch ra kiu ca phn t trong mng.
104
105
106
107
...
PZ: process(A);
-- PZ l nhn ca qu trnh
variable V1,V2 : INTEGER;
begin
V1:=A-V2;
-- statement 1
Z<= -V1;
-- statement 2
V2:= Z+V1*2; -- statement 3
end process PZ;
Gi s mt s kin xy ra trn tn hiu A ti thi im T1 v bin V2 -c gn
gi tr l 10, trong pht biu th 3, sau mt s kin xy ra trn tn hiu A ti thi
im T2, gi tr ca V2 -c s dng trong pht biu 1 s cng l 10. Mt bin cng
c th -c khai bo bn ngoi mt qu trnh hoc mt ch-ng trnh con. Mt bin
c th -c c v cp nht bi mt hoc c th nhiu qu trnh, nhng bin ny
-c gi l shared variable (Bin chia s).
108
109
4
3
1 ns
3 ns
4 ns
5 ns
V d :
..........
process (.....)
Begin
S <= transport 1 after 1 ns, 3 after 3 ns, 5 after 5 ns;
S <= transport 4 after 4 ns;
end process;
Nh- v d v biu trn ta thy cng vic th t- cn thc hin tr-c cng
vic th 5, nh-ng trong phn ch-ng trnh th pht biu ca cng vic th 5 li -c
thc hin tr-c cng vic th t-. Hnh v d-i y m t pht biu Transport, sau 3s
n s -c bt sng v sng trong khong thi gian ng bng thi gian bt cng
tc.
b.Inertial Delay.
Inertial Delay ( G- chm do qun tnh ), l gi tr mc nh ca VHDL. N
110
111
Transport Delay
S <= A after 20 ns
S
10ns
20ns
30ns
40ns
10ns
20ns
30ns
40ns
112
Mt pht biu if -c dng chn la nhng pht biu tun t cho vic thc
thi da trn gi tr ca biu thc iu kin. Biu thc iu kin y c th l mt
biu thc bt k m gi tr ca chng phi l kiu lun l.
Dng thng th-ng ca pht biu if l:
if boolean-expression then
sequential-statements
{elsif boolean-expression then
sequential -statement }
{else
sequential-statement}
enf if;
V d1:
if sum <=100 then --<= is less-than-or-equal-to operator.
SUM:=SUM+10;
end if;
V d 2:
signal IN1, IN2, OU : STD_LOGIC;
process (IN1, IN2)
begin
if IN1 = '0' or IN2 = '0' then
OU <= '0' ;
elsif IN1 = 'X' or IN2 = 'X' then
OU <= '1';
else
OU <= '1' ;
end if;
end process;
V d 3:
113
-- branch 1
-- branch 2
-- -- C th c nhiu nhnh
{when others => sequential-statement}
-- last branch
end case;
Pht biu case la chn mt trong nhng nhnh cho vic thc thi da trn gi
tr ca biu thc. Gi tr biu thc phi thuc kiu ri rc hoc kiu mng mt chiu.
Cc chn la ( Choices ) c th -c din t nh- mt gi tr n, hoc mt di gi
tr bng vic s dng du " | " hoc s dng mnh khc. Tt c cc gi tr c th
c ca biu thc phi -c th hin trong pht biu case ng mt ln. Cc mnh
khc c th -c s dng bao qut tt c cc gi tr, v nu c, phi l nhnh cui
cng trong pht biu case. Mi mt chn la phi c cng kiu vi kiu ca biu
thc. Mt th d cho pht biu case:
V d 1:
type WEEK_DAY is (MON, TUE, WED, THU, FRI, SAT, SUN);
type DOLLARS is range 0 to 10;
variable DAY: WEEK_DAY;
114
null
115
dng pht biu ny l trong pht biu if hoc trong pht biu case.
V d : Variable A, B : INTEGER range 0 to 31 ;
Case A is
when 0 to 12 =>
B:= A;
when others =>
Null;
End Case;
116
v bin s dng trong vng lp for s chuyn giao cho nh danh vng lp. Vng
ca vng lp FOR cng c th l vng ca mt kiu lit k.
V d 2:
. . . .
117
next;
else
null;
end if;
K:=K+1;
end loop;
Khi pht biu next -c thc thi, qu trnh thc hin s nhy n phn cui
ca vng lp (pht biu cui cng K: =K+1) sau gim gi tr ca nh danh vng
lp j, v thc hin li t u.
V d 2:
118
V d 2 :
process -- Khng sensitivity list
variable TEMP1, TEMP2:BIT;
119
begin
TEMP1:=A and B;
TEMP2:=C and D;
TEMP1:=TEMP1 or TEMP2;
Z<=not TEMP1;
wait on A, B, C, D; -- Thay th cho sensitivity-list u Process .
End process.
V d 3: Hai Process trong v d d-i y ch ra hai process c pht biu Wait
on. Process bn tri s lm cho Process treo ngay sau khi Start v ch cho n khi c
s kin xut hin trn tn hiu SigA. Cn Process bn phi s thc hin ba cu lnh
v sau ri vo trng thi ch n khi xut hin s kin trn tn hiu SigB.
120
121
- Khai bo bin .
- Khai bo hng .
- Khai bo cc kiu.
- Khai bo cc kiu con.
- Khai bo cc b danh Alias.
- Cc mnh USE.
Mt sensitivity list ( Tp cc s kin thay i trng thi cn x l trong mt
qu trnh ) c cng ngha vi mt Process c cha pht biu wait, m pht biu
wait ny l pht biu cui cng trong mt process v chng c dng sau:
Wait
on sensitivity list ;
Mt process c chc nng ging nh- mt vng lp v hn m trong n c cha
ton b cc pht biu tun t -c ch ra trong vng lp . V vy mt pht biu
process cn phi c hoc mt sensitivity list hoc mt pht biu wait on hoc c hai.
V d 1:
architecture A2 of example is
signal i1, i2, i3, i4, and_out, or_out : bit;
begin
pr1 : process (i1, i2, i3, i4)
begin
and_out <= i1 and i2 and i3 and i4;
end process pr1;
pr2 : process (i1, i2, i3, i4)
begin
or_out <= i1 or i2 or i3 or i4 ;
end process pr2;
end A2
V d 2:
122
123
V d 2:
architecture A2 of example is
signal i1, i2, i3, i4, and_out, or_out : bit;
begin
process (i1, i2, i3, i4)
begin
and_out <= i1 and i2 and i3 and i4;
end process ;
process (i1, i2, i3, i4)
begin
or_out <= i1 or i2 or i3 or i4 ;
end process ;
end A2
V d 3:
architecture A3 of example is
signal i1, i2, i3, i4, and_out, or_out : bit;
begin
process
begin
and_out <= i1 and i2 and i3 and i4;
or_out <= i1 or i2 or i3 or i4;
wait on i1, i2, i3, i4;
end A3;
Ba v d trn y l t-ng -ng nhau.
124
mt ch. Ngoi tr biu thc cui cng, cc biu thc cn li phi c mt iu kin
chc chn, cc iu kin ny -c nh gi theo th t. Nu mt iu kin -c
nh gi l TRUE th biu thc t-ng ng -c s dng, ng-c li cc biu thc cn
li s -c s dng. Nh rng ch mt biu thc -c s dng ti mt thi im . C
php ca cu lnh ny nh- sau:
target <= {expression [ after time_expression ] when condition else}
expression [ after time_expression ];
Mt pht biu gn tn hiu c iu kin c th -c m t bi mt pht biu
process m process c cha pht biu IF. Bn c th s dng pht biu gn tn hiu
c iu kin trong mt process .
V d 1:
architecture A1 of example is
signal a, b, c ,d : integer ;
begin
a <= b when ( d >10 ) else
c when ( d >5 ) else
d;
end A1;
V d 2:
architecture A2 of example is
signal a, b, c ,d : integer ;
begin
process (b, c, d)
begin
if ( d > 10) then
a <= b
elsif ( d >5 ) then
a <=c;
else
a <= d;
125
end if;
end process;
end A2;
V d 3: S dng cc pht biu c iu kin.
126
Z <= a when 0 | 1 | 2,
b when 3 to 10,
c when others;
V d 2 :
process ( SEL, a, b, c )
case SEL is
when 0 | 1 | 2| =>
Z <= a;
when 3 to 10 =>
Z <= b;
when others =>
Z <= C;
end case;
end process ;
Hai v d trn y l hon ton t-ng -ng nhau.
127
3.7.5. Cc li gi th tc ng thi.
Mt li gi th tc ng thi chnh l mt li gi th tc m n -c thc thi
bn ngoi mt process, n ng c lp trong mt kin trc architecture. Li gi th
tc ng thi bao gm :
- C cc tham s IN, OUT, INOUT.
128
- C th c nhiu hn mt gi tr tr v
- N -c xem nh- mt pht biu.
- N t-ng -ng vi mt process c cha mt li gi th tc n.
Hai v d d-i ay l t-ng -ng nhau.
V d 1:
architecture .................
begin
procedure_any (a,b) ;
end..........;
V d 2:
architecture ................
Begin
process
begin
procedure_ any (a,b);
wait on a,b;
end process ;
end .............;
129
-- temp = 61
end process;
Tham s chuyn vo hm -c hiu mc nh l mt hng s, v khng c khai
bo ca class.
b. Th tc v cc c tr-ng ca chng.
- Chng -c gi nh- mt li pht biu.
- C th tr v khng hoc mt hoc nhiu i s.
- Cc tham s chuyn giao cho th tc c th l mode in, out, v inout.
130
131
132
-- S kt hp theo tn.
133
end DUMMY_ARCH;
Pht biu process t-ng -ng vi li gi mt th tc ng thi nh- sau:
process
begin
INT_2_VEC (D_ARRAY,START,STOP,SIGNAL_VALUE);
-- Phn th hin ca cc li gi th tc tun t
wait on SIGNAL_VALUE;
-- Ch s kin trn SIGNAL_VALUE v xem chng nh- mt tn hiu vo.
end process;
134
3.8. Cc ng gi ( Packages ).
Bn c th ng gi ct cc ch-ng trnh con, cc kiu d liu, cc hng
...th-ng dng s dng chng trong cc thit k khc. Mt package bao gm hai
phn chnh: Phn khai bo v phn thn package, phn khai bo ch ra giao tip cho
package . C php ca khai bo package nh- sau:
package package _name is
{package _declarative_item}
end [package _name];
Phn package _declarative_item c th l bt k kiu no sau y:
- Khai bo kiu.
- Khai bo cc kiu con.
- Khai bo tn hiu.
- Khai bo cc hng.
- Khai bo b danh ALIAS.
- Khai bo cc thnh phn.
- Khai bo cc ch-ng trnh con.
- Cc mnh USE.
Ch ! khai bo tn hiu trong package c mt s vn cn l-u trong khi
tng hp, bi v mt tn hiu khng th -c chia s bi hai Entity. V vy nu
mun dng chung khai bo tn hiu bn phi khai bo tn hiu ny l tn hiu ton
cc.
Phn thn ca package ch ra hot ng thc t ca mt package. Phn thn
ca package phi lun c tn trng vi phn khai bo. C php ca khai bo ny
nh- sau:
package body package _name is
{package _body_declarative-item}
end [package _name] ;
135
136
137
Sum
FULL_Adder
Cout
Cin
Cin
N1
SUM
B
N3
Cout
N2
138
Begin
O <= I0 xor I1;
End BHV;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity OR2_gate is
port ( I0, I1 : in STD_LOGIC ;
O : out STD_LOGIC );
End OR2_gate;
Architecture BHV of OR2_gate is
Begin
O <= I0 xor I1;
End BHV;
th hin cc component ny trong mt thit k, ta khai bo chng nh- sau:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity FULL_ADDER is
port (A, B, Cin : in STD_LOGIC;
Sum, Cout : out STD_LOGIC);
End FULL_ADDER;
component AND2_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
end component;
component OR2_gate
port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
end component;
signal N1, N2, N3: STD_LOGIC;
139
begin
U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1);
U2 :AND2_gate port map ( A, B, N2);
U3 :AND2_gate port map ( Cin, N1, N3);
U4 :XOR_gate port map ( Cin, N1, Sum);
U5 :OR2_gate port map ( N3, N2, Cout);
end IMP;
140
X (3)
Y (3)
X (2)
Y (2)
X (1)
Y (1)
X (0)
Y (0)
'0'
Cout
FA (3)
FA (2)
FA (1)
FA (0)
Z (3)
Z (2)
Z (1)
Z (0)
component FULL_ADDER
port ( A, B, Cin : in STD_LOGIC ;
Sum, Cout : out STD_LOGIC );
end component ;
begin
141
Y (3)
X (2)
Y (2)
X (1)
Y (1)
X (0)
Y (0)
Cout
FA (3)
FA (2)
FA (1)
HA (0)
Z (3)
Z (2)
Z (1)
Z (0)
142
HA: HALF_ADDER port map ( X (I), Y(I), Z (I), TMP ( I+1 ));
end generate ;
G2: if I >= 1 and I <= 3 generate
FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 ));
end generate ;
end generate ;
Cout <= TMP ( 4 );
end IMP;
143
end component;
signal N1, N2, N3: STD_LOGIC;
for U1 : XOR_gate use entity work.XOR_gate (BHV);
for others : XOR_gate use entity work.XOR_gate (BHV);
for all : AND2_gate use entity work.AND2_gate (BHV);
for U5 : OR2_gate use entity work.OR2_gate (BHV);
begin
U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1);
U2 :AND2_gate port map ( A, B, N2);
U3 :AND2_gate port map ( Cin, N1, N3);
U4 :XOR_gate port map ( Cin, N1, Sum);
U5 :OR2_gate port map ( N3, N2, Cout);
end IMP;
DOUT
Combinational
Logic
register
clock
144
Data_In
SET
Data_out
S
CLR
145
Data_In
Data_out
S
SET
en
CLR
Data_out
RST
Thay v -ng Data_out -c gn bng ' 0 ', chng ta c th gn '1' cho -ng
Preset khng ng b.
SET
CLK
CLR
Data_out
146
Data_In
'0'
MUX
SET
Data_out
S_RST
CLK
CLR
Data_In
SET
Data_out
CLK
CLR
A_RST
147
Q1
PB
FF
CLK
FF
Q2
PB.Pulse
Entity PULSER is
port ( CLK, PB : in bit;
PB_PULSER : out bit );
end PULSER;
architecture BHV of PULSER is
signal Q1, Q2 : bit;
begin
process ( CLK, Q1, Q2 )
begin
if ( CLK'event and CLK = ' 1' ) then
Q1 <= PB;
Q2 <= Q1;
end if;
PB_PULSE <= ( not Q1 ) nor Q2;
end process ;
end BHV;
148
Dout (3)
Dout (2)
Q
S
Dout (1)
Dout (0)
Q
R
Din (3)
Din (2)
Din (1)
Din (0)
CLK
ASYNC
149
Din
FF
FF
FF
Dout
FF
CLK
3.11.8. Cc b m khng ng b.
B m khng ng b l b m m trng thi ca n thay i khng b iu
khin bi cc xung ng b ng h.
Cch m t b m ny nh- sau:
Count (0)
1
CLK
FF
Count (1)
FF
Count (2)
Count (3)
FF
RESET
FF
150
3.11.9. Cc b m ng b.
Nu tt c cc Flip - Flop ca b m -c iu khin bi tn hiu clock
chung th chng -c gi l b m ng b.
Cch vit chng nh- sau:
signal CLK, RESET, load, Count, Updown : Bit;
signal Datain : integer range 0 to 15;
signal Reg : integer range 0 to 15: = 0;
process ( CLK, RESET )
begin
if RESET = '1' then Reg <= 0;
elsif ( CLK'event and CLK = '1' ) then
if ( Load = ' 1' ) then
Reg <= Datain;
else
if (Cout = '1' ) then
if Updown = '1' then
Reg <= ( Reg +1) mod 16;
else
Reg <= ( Reg -1 ) mod 16;
end if;
end if;
end if;
end if;
end process ;
151
OE
Din
Dout
3.11.21.M t Bus.
Mt h thng Bus c th -c xy dng vi cc cng ba trng thi thay v cc
cng multiplexers.
Ng-i thit k phi m bo khng c nhiu hn mt b m trng thi kch
hot ti bt k thi im no. Cc b m kt ni cn phi -c iu khin v vy
ch c b m ba trng thi truy cp -ng Bus trong khi cc b m khc duy tr
trng thi tr khng cao.
Thng th-ng cc php gn tn hiu tc th, chng hn nh- cc -ng Bus
trong v d d-i y khng -c php mc mt kin trc. Tuy nhin cc kiu
d liu STD_LOGIC v STD_LOGIC_VECTOR c th c nhiu -ng iu khin.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity BUS is
port (S : in STD_LOGIC_VECTOR ( 1 downto 0 );
OE : buffer STD_LOGIC_VECTOR ( 3 downto 0 );
R0, R1, R2, R3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
BusLine : out STD_LOGIC_VECTOR ( 7 downto 0 ) );
end BUS ;
152
S (0)
2 to 4
OE (1)
OE (2)
OE (3)
0
1
Decoder
S (1)
2
3
R0
R1
R2
R3
153
Ch-ng IV
Thit k b iu khin ng c b-c
4.1. Gii thiu tm tt
Vic ng dng iu khin cc m t b-c, thng th-ng -c kt hp vi cc
b vi x l to ra mt kh nng iu khin v tr vi chnh xc cao. Motor
b-c l thit b m n c th quay vi mt s chnh xc trn mi b-c. Cc loi
motor b-c in hnh th-ng quay vi gc quay l 150 hoc 7.50 trn mt b-c,
th-ng th motor -c ch ra s b-c cn thit quay ht mt vng 3600 ( Vi
motor b-c quay 150 trn mt b-c s quay 24 b-c trong mt vng). Vic iu
khin ng c b-c chnh l iu khin vic cung cp in p trn cc cun dy ca
chng. ch-ng ny tc gi xin trnh by mt v d n gin s dng CPLD, FPGA
v gii thiu b vi x l th-ng dng iu khin ng c b-c vi bn cun dy
pha. V d ny l mt v d n gin nhm lm quen v hiu cch lp trnh trn
cu trc cu CPLD v FPGA ch khng -a vo ng dng no c. Tuy nhin nu
mun pht trin v d ny thnh ng dng th vic trin khai cng rt d dng, v cc
b-c c bn ca thit k s -c tin hnh theo trnh t, v ch thm mt s thit b
n gin khc nh- Encoder hay cc mt quang l c th c mt vng iu khin kn
i vi v d ny .
154
VCC
VCC
IRF 630
VCC
IRF 630
Bit0
VCC
Bit1
VCC
Bit2
VCC
Bit3
IRF 630
IRF 630
Bit 3
Bit 2
Bit 1
Bit 0
155
Bit 3
Bit 2
Bit 1
Bit 0
iu khin motor b-c, b vi x l cn phi -a ra cc mu bit tun t nhhai bng va nu. o chiu quay ca ng c phi thc hin to mu bit tun t
theo th t ng-c li ca cc b-c. L-u , sc qun tnh ca ng c cn c mt
gi chm nht nh (thng th-ng khong t 5 n 15 ms) gia mi b-c.
D-i y xin gii thiu ch-ng trnh -c vit bng ngn ng C v np cho
chip vi iu khin h 89C51 hoc 89C2051 dng bn d-ng song song ca cng P1.
Nu dng thch anh khc th phi tnh gi tr np cho TH0 v TL0 khc,
ch-ng trnh sau iu khin cho motor quay 30 b-c lin tc sau o chiu quay.
y l ch-ng trnh v d dng tham kho tr-c khi b-c sang thc hin trn
CPLD v FPGA.
#include <c:\keil\c51\inc\reg51.h>
#include <c:\Keil\c51\inc\absacc.h>
void time()
{
TH0=0x9E; /* Thch anh 6Mhz*/
TL0=0x58; /* Np b m gi chm 50 ms */
TF0=0;
TR0=1;
while (TF0==0);
TR0=0;
}
/*-------------------------------------------------------------------------------*/
unsigned char steptab[] = {0x0a, 0x08, 0x09, 0x01, 0x05, 0x04, 0x06, 0x02};
//unsigned char steptab[] = {0x0a,0x09,0x05,0x06};
main()
156
{
unsigned char ptr =0;
unsigned char cntr;
bit DFLAG;
TMOD=0x21;
DFLAG=0;
while(1)
{
for (cntr=0;cntr<30;cntr++)
{
P1=steptab[ptr&0x7];
time();
if (DFLAG==0)
ptr++;
else
ptr--;
}
DFLAG=!(DFLAG);
}
}
157
Tn hiu
iu khin
Khi To Cc
Xung Ra Theo
Mu B-c
Cc mu bit
Tn hiu iu khin
Clock
Khi To Xung
Clock
158
ch-ng trnh StateCAD hoc vit trc tip bng VHDL). y tc gi xin gii thiu
ch-ng trnh -c vit bng VHDL. S m t trng thi ca modul to b-c c
dng nh- sau:
RESET
E = 0 & DIR = 0
E =1
Step_0
Step_1
E =1
E = 0 & DIR = 1
E = 0 & DIR = 0
E = 0 & DIR = 1
E = 0 & DIR = 1
E = 0 & DIR = 0
E = 0 & DIR = 1
E =1
Step_3
Step_2
E =1
E = 0 & DIR = 0
159
160
Init
COUNT 10M = 0, Clk_1ms = 0,
COUNT_xms = 0, Clk_Out =0
RESET = 1 ?
Yes
No
Clk_1ms?
Clk In ?
No
No
Yes
Yes
COUNT_xms = COUNT_xms + 1
COUNT_xms = DIV ?
No
No
COUNT 10M = 4000 ?
Yes
Yes
COUNT_xms = 0
Clk_Out = Not (Clk_Out)
COUNT 10M = 0
Clk_1ms = Not (Clk_1ms)
161
Init
Dout = "000", E =1, Dir =1
Yes
Reset = 1
No
Start = 0 ?
E=1
Cnt_Dir = 0 ?
E=0
Dir =1
Inc = 0 ?
Dout =Dout - 1
Yes
Yes
Yes
No
No
No
Dir = 0
Dout =Dout +1
Hnh 4.8. L-u thut ton Modul qut phm chc nng, Inc_Dec.vhd
162
163
164
mt thi gian cn thit c, tham kho, tm ti. Xong khi thc hin -c trn
n, th mi thy -c n rt -u vit, bi l chng ta c th to ch-ng trnh ca
chng ta vit ra thnh mt core (li), m khi c ln no ta c th s dng li
chng mt cch d dng. V mt iu quan trng na l chng ta -a mt vi
mch UART vo trong mt chp n m trong chip ny c th -c tch hp cng
nhiu cc vi mch khc na thc hin mt h thng phc tp ch trong mt chip.
y mi ch l mt ng dng s khai ban u, vi FPGA n cn c mt chng di
cc ti nguyn ch-a -c khai thc ht, bn c th to RAM trong chng, to mt
b vi x l trong chng hay bin chng thnh mt b DSP, hay cc b lc s chuyn
dng, b x l cc thut ton x l nh ... Vi v d nh b ny tc gi cng xin
-c trnh by, v d sao n cng l b-c i ban u trn nn ca cc chp mt
cao tc ln ny. Cng vi v d gii thiu, by gi ta khng iu khin bng
phm na m ta s dng ch-ng trnh iu khin. Ch-ng trnh ny -c vit
bng Visual Basic iu khin motor bng my tnh thng qua cng COM1. Trong
chip Spartan s -c vit mt b UART nhn d liu t my tnh PC -a sang.
1. Ch-ng trnh iu khin giao din phn mm Visual Basic
Mc ch ca chng ta l i thit k b UART kt hp vi modul iu khin
ng c b-c nh- gii thiu. Chnh v l do ny ch-ng trnh vit bng Visual
Basic -c vit n gin vi cc nt n thay cho phm trong v d tr-c. Nu
thm mt b-c na l chng ta c th ly d liu t mch phn hi ca ng c
x l trong my tnh. Tuy nhin lun vn ny tc gi ch cp n mt mc ch
c bn v vic ghp ni my tnh vi FPGA thng qua mt b UART -c vit
trong FPGA. Trn form ch-ng trnh, khi ta kch chut vo cc nt nhn ny th
ch-ng trnh s truyn cc Byte d liu qua cng COM 1 vi khun mu truyn t
sn l "9600,N,8,1". (Ch-ng trnh ny -c th nghim ghp ni vi b vi x l
89C51 v FPGA Spartan3 XC3S200 5ft256). Mi ln kch chut l mt ln ch-ng
trnh truyn mt Byte d liu, v th b UART -c vit trong bo mch Spartan-3 s
cng phi vit vi tc Baudrate l 9600 vi khun mu truyn nhn nh- trn.
Ch-ng trnh iu khin ny -c vit d-i dng mt Form n vi su nt nhn
nh- sau:
165
166
Else
MsgBox ("Start Command Button haven't been pressed")
End If
End Sub
-----------------------------------------------------------------------------------Private Sub cmdRight_Click()
If FLAG = True Then
command = &H52 'chatacter R
MSComm1.Output = Chr(command)
Else
MsgBox ("Start Command Button haven't been pressed")
End If
End Sub
-----------------------------------------------------------------------------------Private Sub CmdStart_Click()
FLAG = True
command = &H53 'character S
MSComm1.Output = Chr(command)
End Sub
-----------------------------------------------------------------------------------Private Sub cmdSTOP_Click()
FLAG = False
command = &H42 'character B = stop
MSComm1.Output = Chr(command)
End Sub
-----------------------------------------------------------------------------------Private Sub cmdUp_Click()
If FLAG = True Then
command = &H55 ' character U
MSComm1.Output = Chr(command)
Else
MsgBox ("Start Command Button haven't been pressed")
167
End If
End Sub
Private Sub Form_Load()
FLAG = False
MSComm1.CommPort = 1
MSComm1.Settings = "9600,N,8,1"
MSComm1.PortOpen = True
End Sub
-----------------------------------------------------------------------------------Private Sub Form_Unload(Cancel As Integer)
MSComm1.PortOpen = False
End Sub
d0
d1
d2
d3
d4
d5
d6
d7
Stop
Start
168
Start
d1
UART_RX
BAUD
RATE
TIMING
TXD
UART_TX
Led
Start/Stop
pin_rs232_rd
Modul UART
Cnt_Dir
Sec [3:0]
Modul Step_Motor
Inc/Dec
Clock
Led1
Reset
169
Init
TxD = 1, Bitpos=0, TbufL =0
Yes
Reset = 1
No
No
Enable= 1 ?
LoadS=1?
Yes
Yes
No
BitPos=0?
Yes
No
BitPos=1?
No
BitPos=10
Yes
Yes
TxD=1
No
Tbuff=DataIn
TbufL = 1,
Busy = TbufL or LoadA
TxD=0
TBufL=1?
Yes
Treg = Tbuff
BitPos = BitPos+1
TBufL= 0.
TxD =Treg(BitPos)
BitPos = BitPos+1
TxD =Treg(BitPos)
BitPos = 0
170
171
Init
RRegL = 0, Bitpos = 0
Reset = 1
Yes
No
ReadA =1 ?
No
Enable= 1 ?
No
RxAv = 1
Yes
RxAv = 0
Yes
BitPos=0?
No
No
BitPos= 2 - 9
No
BitPos=10
Yes
No
Yes
RxD = 0 ?
Yes
SampleCount = 0
Bitpos = 1
RRegL = 0
SampleCount =1 &
BitPos >= 2?
No
SampleCount = 3 ?
Yes
Yes
No
RReg = 1, Bitpos=0
DataO = RReg
SampleCount = 0
No
Yes
SampleCount = 3 ?
Yes
SampleCount =
SampleCount + 1
BitPos = BitPos+1
172
biu d-i y:
-- Start
-- Stop
-- Left
173
-- Right
-- Up
-- Down
Inc <='1' ;
when others =>
Start <= '1';
Cnt_Dir <= '1' ;
Inc <= '1';
end case;
end Process;
end arch;
Sau i tng hp v thc thi ch-ng trnh, ta s thu -c cc du tch mu
xanh, ch-ng trnh Project Navigator s thng bo rng vic thc thi trn thit b
khng c li nh- ( Hnh 4.22).
174
175
Nh- vy ton b ch-ng ny gii thiu vic thc hin iu khin Mtor vi
hai thit b ch khc nhau l CPLD v FPGA. V d ny -c cho chy trn thc
t vi m t -c chn l 7.50 b-c, in p cp cho ng c l 5V, -c th
nghim trn c hai board mch CPLD XC9572 v Spartan3-XC3s200 xem hnh 4.25
v hnh 4.26.
176
177
Ph lc ch-ng trnh 1
----------------------------
Top_Step.vhd
---------------------------
Inc_Dec.vhd-------------------------------
3
entity Inc_Dec is
Port ( Clk, Reset,Inc,Start,Cnt_Dir :Std_logic;
E,Dir,Led,Led1 : Out Std_logic;
DOut : Buffer std_logic_vector(2 downto 0));
end Inc_Dec;
----------------------------------------------------------architecture Behavioral of Inc_Dec is
Signal Dec : Std_logic;
----------------------------------------------------------begin
Dec <= NOT (Inc);
----------------------------------------------------------Process(Reset,Clk,Start)
begin
if Reset = '1' then
E <= '1';
elsif Clk'event and Clk = '1' then
if Start = '0' then
E <= '0';
Led1 <= '0';
elsif Start = '1' then
E <='1';
Led1 <= '1';
end if;
end if;
End Process;
----------------------------------------------------------Process (Clk,Cnt_Dir)
Begin
if Cnt_Dir='0' then
Dir <= '1';
led <='0';
else
Dir <= '0';
led <= '1';
end if;
End process;
----------------------------------------------------------Process(Clk, Inc, Dec, Reset)
begin
If Reset = '1' then
DOut <= b"000";
elsif Clk'event and clk='1' then
If Inc = '0' then
if Dout = "100" then
Dout <= "000";
else
Dout <= Dout + 1;
end if;
elsif Dec = '0' then
if Dout = "000" then
Dout <= "100";
else
Dout <= Dout - 1;
end if;
else
Dout <= Dout;
end if;
end if;
end process;
end Behavioral;
---------------------------
Clk_Generator.vhd---------------------
4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Clk_Generator
Port ( Clk,Reset
Div
Clk_Out
end Clk_Generator;
is
: in std_logic;
: in std_logic_vector(2 downto 0);
: Buffer std_logic);
SecGenerator.vhd---------------------
5
Sec : out std_logic_vector(3 downto 0));
end SecGenerator;
----------------------------------------------------------architecture Behavioral of SecGenerator is
-- Full Step Table : ( x"A", x"9" , x"5",x"6" )
-- Half Step Table : (x"A",x"8",x"9",x"1",x"5",x"4",x"6",x"2")
Type States is (Step_0, Step_1, Step_2,
Step_3,Step_4,Step_5,Step_6,Step_7);
Signal Next_State, Current_State : States;
begin
---------------------Process( Clk, Reset, E, Dir, Current_State )
Begin
if Reset = '1' then
-- Reset ='1' key Pressed
Next_State <= Step_0;
Sec
<= x"A";
elsif Clk'event and Clk = '1' and E = '0' then
Case Current_State is
When Step_0 =>
Sec <= x"A";
if DIR = '1' then
Next_State <= Step_1;
else
Next_State <= Step_7;
end if;
When Step_1 =>
Sec <= x"8";
if DIR = '1' then
Next_State <= Step_2;
Else
Next_State <= Step_0;
end if;
When Step_2 =>
Sec <= x"9";
if DIR = '1' then
Next_State <= Step_3;
Else
Next_State <= Step_1;
end if;
When Step_3 =>
Sec <= x"1";
if DIR = '1' then
Next_State <= Step_4;
Else
Next_State <= Step_2;
end if;
When Step_4 =>
Sec <= x"5";
if DIR = '1' then
Next_State <= Step_5;
Else
Next_State <= Step_3;
end if;
When Step_5 =>
Sec <= x"4";
if DIR = '1' then
Next_State <= Step_6;
Else
Next_State <= Step_4;
end if;
When Step_6 =>
Sec <= x"6";
if DIR = '1' then
Next_State <= Step_7;
6
Else
Next_State <= Step_5;
end if;
When Step_7 =>
Sec <= x"2";
if DIR = '1' then
Next_State <= Step_0;
Else
Next_State <= Step_6;
end if;
When Others =>
Next_State <= Step_0;
end Case;
end if;
end Process;
----------------------------------------------------------Process(Clk)
Begin
if Clk'event and clk = '1' then
Current_State <= Next_State;
end if;
end process;
end Behavioral;
Ph lc ch-ng trnh 2
4. SecGenerator.vhd
-------------------------------------
IO.vhd----------------------------
--------------------------------------------------- ---------------------------------------------- Author : PHAM TUAN HAI_ Lop Dieu Khien K15 --- Project
RS232 CONNECTION
--- -------------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity IO is
port( CLK : in std_logic;
Pushbtn : in std_logic;
rs232_rd: in std_logic;
rs232_td: out std_logic;
Led,Led1,pin_led: Out std_logic ;
Sec : out std_logic_vector(3 downto 0));
end IO;
------------------------------------------------------architecture arch of IO is
constant YES: std_logic := '1';
constant NO:
std_logic := '0';
constant HI:
std_logic := '1';
constant LO:
std_logic := '0';
signal sysClk
: std_logic;
signal sysReset : std_logic;
-- uart component
component uart
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130);
port(
CLK_I : in std_logic; -- clock
RST_I : in std_logic; -- Reset input
ADR_I : in std_logic_vector(1 downto 0);
DAT_I : in std_logic_vector(7 downto 0);
DAT_O : out std_logic_vector(7 downto 0);
WE_I : in std_logic; -- Write Enable
9
STB_I : in std_logic; -- Strobe
ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out std_logic;
IntRx_O : out std_logic;
BR_Clk_I : in std_logic;
TxD_PAD_O: out std_logic;
RxD_PAD_I: in std_logic);
end component;
--------------------------------------------------------------------component Top_step
Port ( Clk,Reset,Inc,Start,Cnt_Dir : in std_logic;
Sec : out std_logic_vector(3 downto 0);
Led,Led1 : Out std_logic );
End component;
---------------------------------------------------------------------------------------------------------------------- uart signals
signal uart_CLK_I : std_logic;
signal uart_RST_I : std_logic;
signal uart_ADR_I : std_logic_vector(1 downto 0);
signal uart_DAT_I : std_logic_vector(7 downto 0);
signal uart_DAT_O : std_logic_vector(7 downto 0);
signal uart_WE_I : std_logic;
signal uart_STB_I : std_logic;
signal uart_ACK_O : std_logic;
signal uart_IntTx_O : std_logic;
signal uart_IntRx_O : std_logic;
signal uart_BR_Clk_I : std_logic;
signal uart_TxD_PAD_O: std_logic;
signal uart_RxD_PAD_I: std_logic;
signal charBuf
:std_logic_vector(7 downto 0);
signal Inc,Start,Cnt_Dir:std_logic;
signal Step_Clk : std_logic;
signal Step_Reset : std_logic;
signal charAvail :std_logic;
-------------------------------------------------------------------------------BEGIN
sysClk
<= CLK;
sysReset <= Pushbtn;
uart_ADR_I <= "00";
--------------------------------------------------------------------------------------------------------------------------sysuart: uart generic map(BRDIVISOR => 1320)
port map(CLK_I => uart_CLK_I,
RST_I => uart_RST_I,
ADR_I => uart_ADR_I,
DAT_I => uart_DAT_I,
DAT_O => uart_DAT_O,
WE_I
=> uart_WE_I,
STB_I => uart_STB_I,
ACK_O => uart_ACK_O,
--process signals
IntTx_O
=> uart_IntTx_O,
IntRx_O
=> uart_IntRx_O,
BR_Clk_I => uart_BR_Clk_I,
TxD_PAD_O => uart_TxD_PAD_O,
RxD_PAD_I => uart_RxD_PAD_I );
---------------------------------------------------------sysstep:Top_Step
port map (Step_Clk,Step_Reset,Inc,Start,Cnt_Dir,Sec,Led,Led1);
10
-----------------------------------------------------------uart port connections/conversions
uart_CLK_I <= sysClk;
uart_RST_I <= sysReset;
Step_Reset
<= sysReset;
uart_BR_Clk_I <= sysClk;
Step_Clk
<= sysClk;
rs232_td
<= uart_TxD_PAD_O;
uart_RxD_PAD_I <= rs232_rd;
--------------------------------------------------------------------------------------------------------------------------------------------------------------process(Pushbtn,CLK,uart_IntRx_O, uart_IntTx_O,uart_DAT_O,charBuf,charAvail)
begin
if Pushbtn = '1' then
charBuf <= "00000000";
charAvail <= NO;
uart_ACK_O <= '0'
;
pin_led <= '1';
elsif CLK'event and CLK = '1' then
if(uart_IntRx_O = HI) then
charBuf <= uart_DAT_O;
charAvail <= YES;
uart_WE_I <= LO;
uart_STB_I <= HI;
uart_ACK_O <= uart_STB_I;
pin_led <= '1';
elsif(uart_IntTx_O=HI) then
if( charAvail=YES ) then
uart_DAT_I <= charBuf;
charAvail
<= NO;
uart_WE_I
<= HI;
uart_STB_I <= HI;
uart_ACK_O <= uart_STB_I;
end if;
-- pin_led <= '0';
else
-- charBuf <= "00000000";
uart_STB_I <= LO;
uart_ACK_O <= uart_STB_I;
pin_led <= '0';
end if;
end if;
end process;
-----------------------------------------------------process (Pushbtn,charBuf,CLK)
Begin
if Pushbtn = '1' then
Start <= '1' ;
Cnt_Dir <= '1';
Inc <= '1';
elsif CLK'event and CLK = '1' then
case charBuf is
when x"53" =>
-- Start
Start <= '0';
when x"42" =>
-- Stop
Start <= '1';
when x"4C" =>
-- Left
Cnt_Dir <= '1';
when x"52" =>
-- Right
Cnt_Dir <= '0';
when x"55" =>
-- Up
Inc <= '0';
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when x"44" =>
Inc <='1' ;
when others =>
Start <= '1';
Cnt_Dir <= '1' ;
Inc <= '1';
end case;
end if;
end Process;
end arch;
---------------------------------
-- Down
UART.vhd-----------------------------
---------------------------------------------------------------- Title
: UART
---- Project
: UART
---- Clock
: 50MHz Using Clock of Board XC3s200
---- Author
: Pham Tuan Hai_Lop Dieu Khien K15
--------------------------------------------------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity UART is
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130);
port (
CLK_I : in std_logic;
RST_I : in std_logic;
ADR_I : in std_logic_vector(1 downto 0);
DAT_I : in std_logic_vector(7 downto 0);
DAT_O : out std_logic_vector(7 downto 0);
WE_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
-- process signals
-- Transmit interrupt: indicate waiting for Byte
IntTx_O : out std_logic;
IntRx_O : out std_logic;
BR_Clk_I : in std_logic;
TxD_PAD_O: out std_logic;
RxD_PAD_I: in std_logic);
end UART;
-- Architecture for UART for synthesis
architecture Behaviour of UART is
-----------------------------------------------------------component Counter
generic(COUNT: INTEGER range 0 to 65535);
port (
Clk
: in std_logic; -- Clock
Reset
: in std_logic; -- Reset input
CE
: in std_logic; -- Chip Enable
O
: out std_logic); -- Output
end component;
-----------------------------------------------------------component Rx
port (
Clk
: in std_logic;
Reset : in std_logic;
Enable : in std_logic;
-- Async Read Received Byte . ReadA =1 then no thing to do, ReadA=0 => read
ReadA : in Std_logic;
RxD
: in std_logic;
RxAv
: out std_logic;
DataO : out std_logic_vector(7 downto 0));
12
end component;
-----------------------------------------------------------component Tx
port (
Clk
: in std_logic;
Reset : in std_logic;
Enable : in std_logic;
-- Asynchronous Load signal =1 then transfer Data in input to Buffer, BufL=1
LoadA : in std_logic;
TxD
: out std_logic;
Busy
: out std_logic;
DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component;
------------------------------------------------------------- Signals of uart
signal RxData : std_logic_vector(7 downto 0);
signal TxData : std_logic_vector(7 downto 0);
signal SReg
: std_logic_vector(7 downto 0);
signal EnabRx : std_logic; -- Enable RX unit
signal EnabTx : std_logic; -- Enable TX unit
-- Data Received =1 Buffer contains a received byte ,=0 Buffer empty or idle
signal RxAv
: std_logic;
-- Transmiter Busy =1 is Busy , =0 Accept a byte to transmit
signal TxBusy : std_logic;
signal ReadA : std_logic; -- Async Read receive buffer
signal LoadA : std_logic; -- Async Load transmit buffer
signal Sig0
: std_logic; -- gnd signal
signal Sig1
: std_logic; -- vcc signal
-----------------------------------------------------------BEGIN
sig0 <= '0';
sig1 <= '1';
-----------------------------------------------------------------------------Uart_Rxrate : Counter
generic map (COUNT => BRDIVISOR)
port map (BR_CLK_I, sig0, sig1, EnabRx);
----------------------------------------------------------------------------Uart_Txrate : Counter
generic map (COUNT => 8)
port map (BR_CLK_I, Sig0, EnabRx, EnabTx);
-----------------------------------------------------------------------------Uart_Tx : Tx
port map (BR_CLK_I, RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData);
Uart_Rx : Rx
port map (BR_CLK_I, RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData);
-----------------------------------------------------------------------------IntTx_O <= not TxBusy;
-- Flag signal TxBusy=1 Transmiter is Busy ,or IntTx_0 = 0 is Busy
IntRx_O <= RxAv;
-- RxAv =1 one Byte Received
-- RxAv =0 Receiver Buffer empty
SReg(0) <= not TxBusy;
SReg(1) <= RxAv;
SReg(7 downto 2) <= "000000";
------------------------------------------------------------------------------- Clocked on rising edge. Synchronous Reset RST_I
-----------------------------------------------------------------------------WBctrl : process(CLK_I, RST_I, STB_I, WE_I, ADR_I)
13
variable StatM : std_logic_vector(4 downto 0);
begin
if Rising_Edge(CLK_I) then
-- System Clock rising
if (RST_I = '1') then
-- if no Reset
ReadA <= '0';
-- ReadA Signal =0
LoadA <= '0';
-- LoadA Signal =0
else
-- When reset = 0 occured
-- Write Byte to Tx
if (STB_I = '1' and WE_I = '1' and ADR_I = "00") then
-- Get input connect to TxData input signal of Transmiter
TxData <= DAT_I;
-- Async transmit buffer Load signal , load data into Transmiter
LoadA <= '1';
else LoadA <= '0';
end if;
-- Read Byte from Rx
if (STB_I = '1' and WE_I = '0' and ADR_I = "00") then
-DAT_O <= RxData;
-- Out Data to Bus
-- Async receive buffer Read signal connects to ReadA input of Receiver
ReadA <= '1';
-- Signal is used to read buffer, ReadA=1 =>
Read
else ReadA <= '0';
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------ACK_O <= STB_I;
DAT_O <=
RxData when ADR_I = "00" else
SReg when ADR_I = "01" else
"00000000";
end Behaviour;
--------------------------------------
Rx.vhd---------------------------
--------------------------------------------------------------- Title
: UART
---- Project
: UART
---- Clock
: 50MHz
---- Author
: Pham Tuan Hai
--------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity Rx is
port (
Clk
: in std_logic;
Reset : in std_logic;
Enable : in std_logic;
ReadA : in Std_logic;
RxD
: in std_logic;
RxAv
: out std_logic;
DataO : out std_logic_vector(7 downto 0));
end Rx;
-----------------------------------------------------------------------------architecture Behaviour of Rx is
signal RReg : std_logic_vector(7 downto 0);
signal RRegL: std_logic;
begin
------------------------- RxAv process---------------------------RxAvProc : process(RRegL,Reset,ReadA)
14
begin
if ReadA = '1' or Reset = '1' then
RxAv <= '0';
elsif Rising_Edge(RRegL) then
RxAv <= '1';
end if;
end process;
----------------------- Rx Process--------------------------------RxProc : process(Clk,Reset,Enable,RxD,RReg)
variable BitPos : INTEGER range 0 to 10;
variable SampleCnt : INTEGER range 0 to 3;
begin
if Reset = '1' then
RRegL <= '0';
BitPos := 0;
elsif Rising_Edge(Clk) then
if Enable = '1' then
case BitPos is
when 0 =>
RRegL <= '0';
if RxD = '0' then
SampleCnt := 0;
BitPos := 1;
end if;
when 10 =>
BitPos := 0;
RRegL <= '1';
DataO <= RReg;
when others =>
if (SampleCnt = 1 and BitPos >= 2) then
RReg(BitPos-2)<=RxD ;
end if;
if SampleCnt = 3 then
BitPos := BitPos + 1;
end if;
end case;
-if SampleCnt = 3 then
SampleCnt := 0;
else
sampleCnt := SampleCnt + 1;
end if;
-end if;
end if;
end process;
end Behaviour;
------------------------------------
Tx.vhd-----------------------------
---------------------------------------------------------------- Title
: UART
---- Project
: UART
---- Clock
: 50MHz
---- Author
: Pham Tuan Hai
--------------------------------------------------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity Tx is
port (
Clk
: in std_logic;
Reset : in std_logic;
Enable : in std_logic;
15
LoadA : in std_logic;
TxD
: out std_logic;
Busy : out std_logic;
DataI : in std_logic_vector(7 downto 0));
end Tx;
--------------------------------------------------------------------architecture Behaviour of Tx is
--------------------------------------------------------------------component synchroniser
port (
C1 : in std_logic;
C : in std_logic;
O : out Std_logic);
end component;
signal TBuff : std_logic_vector(7 downto 0);
signal TReg : std_logic_vector(7 downto 0);
signal TBufL : std_logic;
signal LoadS
: std_logic;
------------------------------------------------------------------------------begin
-- Begin of Architech
-- Synchronise Load on Clk
SyncLoad : Synchroniser port map (LoadA, Clk, LoadS);
Busy <= LoadS or TBufL;
-- Tx process
----------------------------------------------------------------TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
variable BitPos : INTEGER range 0 to 10;
begin
if Reset = '1' then
TBufL <= '0';
BitPos := 0;
TxD <= '1';
elsif Rising_Edge(Clk) then
if LoadS = '1' then
TBuff <= DataI;
TBufL <= '1';
end if;
if Enable = '1' then
case BitPos is
when 0 =>
TxD <= '1';
if TBufL = '1' then
TReg <= TBuff;
TBufL <= '0';
BitPos := 1;
end if;
when 1 =>
TxD <= '0';
BitPos := 2;
when others =>
TxD <= TReg(BitPos-2);
-- Serialisation of TReg
BitPos := BitPos + 1;
end case;
if BitPos = 10 then
-- bit8. next is stop bit
BitPos := 0;
end if;
end if;
end if;
end process;
end Behaviour;
-------------------------------
COUNTER.vhd---------------------------
16
--------------------------------------------------------------- Title
: UART
---- Project
: UART
---- Clock
: 50MHz
---- Author
: Pham Tuan Hai
--------------------------------------------------------------------------------------------------------------------------library IEEE,STD;
use IEEE.std_logic_1164.all;
entity Counter is
generic(Count: INTEGER range 0 to 65535); -- Count revolution
port (
Clk
: in std_logic; -- Clock
Reset
: in std_logic; -- Reset input
CE
: in std_logic; -- Chip Enable
O
: out std_logic); -- Output
end Counter;
------------------------------------------------------------------------------------------------------------------------------architecture Behaviour of Counter is
begin
counter : process(Clk,Reset)
-- Variable Cnt is using temple count variable
variable Cnt : INTEGER range 0 to Count-1;
begin
if Reset = '1' then
Cnt := Count - 1;
O <= '0';
elsif Rising_Edge(Clk) then
if CE = '1' then
-if Cnt = 0 then
O <= '1';
Cnt := Count - 1;
else
O <= '0';
Cnt := Cnt - 1;
end if;
-else O <= '0';
end if;
end if;
end process;
end Behaviour;
-------------------------- Synchroniser.vhd------------------------------------------------------------------------------- Title
: UART
---- Project
: UART
---- Clock
: 50MHz
---- Author
: Pham Tuan Hai
--------------------------------------------------------------------------------------------------------------------------library IEEE,STD;
use IEEE.std_logic_1164.all;
entity synchroniser is
port (
C1: in std_logic;
-- Asynchronous signal
C : in std_logic;
-- Clock
O : out std_logic); -- Synchronised signal
end synchroniser;
17
------------------------------------------------------------------architecture Behaviour of synchroniser is
signal C1A : std_logic;
signal C1S : std_logic;
signal R : std_logic;
begin
RiseC1A : process(C1,R)
begin
if Rising_Edge(C1) then
C1A <= '1';
end if;
if (R = '1') then
C1A <= '0';
end if;
end process;
------------------------------------------------------------------SyncP : process(C,R)
begin
if Rising_Edge(C) then
if (C1A = '1') then
C1S <= '1';
else C1S <= '0';
end if;
if (C1S = '1') then
R <= '1';
else R <= '0';
end if;
end if;
if (R = '1') then
C1S <= '0';
end if;
end process;
O <= C1S;
end Behaviour;
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