M8257 PROGRAMMABLE DMA CONTROLLER Military Military Temperature Range: @ Terminal Count and Modulo 128 —55°C to + 125°C (Tease) Outputs a ‘4-Channel DMA Controller w Single TTL Clock m Priority DMA Request Logic m Single +5V Supply m Channel Inhibit Logic 1m Auto Load Mode ‘The Intel M8257 is a 4-channel direct memory access (DMA) controller. It is specifically designed to simplify the transfer of data at high speeds for the Intel microcomputer systems. Its primary function is to generate, upon a peripheral request, a Sequential memory address which will allow the peripheral to read or write data directly to or from memory. Acquisition of the system bus is accomplished via the CPU's hold function. The M8257 has priority logic that resolves the peripherals requests and issues a composite hold request to the CPU. It maintains the DMA cycle count for each channel and outputs a control signal to notify the peripheral that the programmed number of DMA cycles is complete. Other output control signals simplify sectored data transfers. The M8257 represents a significant savings in component count for DMA-based microcomputer systems and greatly simplifies the transfer of data at high speed between peripherals and memories. aoe x ain Ete = aoe = Terra | [EY = | a : U ake = = cooees-1 5 Figure 1. Block Diagram arowesoe rear [ har w ena wo roam | [or stom ‘ess_| fe —= mf fa a sense Figure 2. Pin Configuration ty 1990 17-15 ‘Order Number 003065-003intel M8257 ABSOLUTE MAXIMUM RATINGS* Case Temperature NOTICE: This isa production data sheet. The specii- cations are subject to change without notice, Under Biast") eg Ce viacmmyramten rice eae Storage Temperature . 65°C to + 150°C These are avets range ony: Gparion Sond the ehh Hespoct to Ground sree 7050 +7 ended exposure heyord ihe “Operating Coneltions” Power Dissipation. .. see OW ao OPERATING CONDITIONS ‘Symbol Parameter min Max Units To Case Temperatura (Instant On) = 55 +125 *C Voo Digital Supply Voltage 450 550 | Vv D.C. CHARACTERISTICS (Over Specified Operating Conditions) ‘Symbol Parameter Min Max Unit ‘Comments Vu Input Low Vottage =05 08 v Vir Input High Voltage 22 | Voo+os | v | Vou ‘Output Low Voltage 0.45 V_| ton = £6mA Vou ‘Output High Voltage 24 Veo V__| low = — 150 nA for AB, OB and AEN lon = —80 WA for Others Vis FRG Output High Voltage 33 Veo V_| tow = =80 pA loc Veo Current Drain 150 mA in Input Leakage 210 BA | VssS Vins Voo Tort ‘Output Leakage During Float =10 HA | Vsg + 0.45 s Vout = Voc CAPACITANCE Tc = 25°C, Voc = GND = OV ‘Symbol rameter Min [Typ | Max | Unit Comments Ow Input Capacitance 10 PF Yo = 1 MHz Gyo 1/0 Capacitance 20 pF | Unmeasured Pins Retumed to GND A.C. CHARACTERISTICS—DMA (MASTER) MODE (Over Specified Operating Conditions) TIMING REQUIREMENTS ‘Symbol Parameter Min Max Unit Tey ‘Cycle Time (Period) 0.320 4 HS To ‘Glock Active (High) 2120) 08 Toy ns Tos DRQT Setup to @ | (St, S4) 120 ns Tou DRQ | Hold from HLDA T (4) o ns Tas HLDAT or 1 Setup to 61 (St, S4) 100 | ns Tas READY Setup Time to 6 T (S3, Sw) 30 ns. Tra READY Hold Time from @ 7 (S3, Sw) 30 ns 17-16intel M8257 A.C. CHARACTERISTICS—DMA (MASTER) MODE (Over Specified Operating Conditions) TIMING RESPONSES (Csymbot Parameter Min Max [Unit Too HRQT or 1 Delay from 6 T (SI, $4) 180 | ns (Measured at 2.0V)(") Toa: HROT oF | Delay from 6 T (SI, $4) 270 | ns (Measured at 3.3¥)) Trew ‘AEN T Delay from 6.1 (S1)(") 300 | ns Taet ‘AEN | Delay from 0 T (Si) 200 [ns Trea ‘Adr(AB)(Active) Delay from AEN T (S14) 20 ns Teaas | _Adr(AB)(Active) Delay trom 8 1 (S1)2) 270_| ns Taran | _Adr(AB)(Float) Delay trom @ T (SN) 200_| ns Tas ‘Adr(AB)(Stable) Delay from 0 T(S1)2) 250_| ns Taw ‘Adr(AB)(Stable) Hold from 6 7 (S12) Tasm — 50 ns TAH ‘Adr(AB)(Vatid) Hold from Fid T (S1, Sn) 60, ns TaHw. ‘Adr(AB) Valid) Hold trom Wr T (S1, SiN 300 ns Trane | _Adr(DB\Active) Delay from @ T (S1)2) 300 [ns TAFOB Adr(DB) (Float) Delay from 4 T ($2)(2) Tsrt + 20 250 ns Tass “Adr(DB) Setup to AdrStb | (S1-S2)4) 4100 ns TaHs ‘Adtr(DB)(Valid) Hold from AdrStb | (S2)(4 50 ns. Ts ‘AdiStb T Delay from 6 T (S1)0") 200 | ns Ts ‘AdrStb | Delay from 6 f ($2) 160 | _ns Tew | _AdrStb Width (S1-82)(4 Tey — 100) ns Tasc. a) or Wi(Ext) | Delay from AdrStb | (S2)(4) 70 ns Toc Ad J or Wr(Ext) | Delay from Adr(DB) 20 ns. Floaty(s2y Tak DAGKT or | Delay from @ | (S2, S1) and 270 | ns TC/Mark T Delay from 8 f ($3) and TC/Mark | Delay from 6 T (S4)(tV6 Too. Fd 1 or Wi(Ext) | Delay from 6 T ($2) and 250) ns Wr J Delay from 6 T (S3)216) Toot Fd T Delay fromé 4 (S1, SI) and 200 | ns WiT Delay from 6 t (S4)(2) TEAC Fid or Wr(Active) from 0 T (S1)2) 300_| ns Tare Fd or Wi(Float) from 0 T (SN) 170_|_ ns Tawa Fra Width (S2-S1 or SI(4) 2Tey + To ns Twwm | Wr Width (S3-S4) Toy — 50 ns Twwme | WrExt) Width (S2-S4)4) 2Tcy — 50 ns NOTES: 4.Load = 1 TTL. 5. ATax < 50 m5. 2! Load = 1 TTL + 50 pF. 6 AToct < 508 9. Load = 1 TTL + (RU = 8.3K), Vou = 33V. 7. aTpcr < 50 08. 4. Tracking Parameter WATintel M8257 A.C. CHARACTERISTICS—PERIPHERAL (SLAVE) MODE (Over Specified Operating Conditions) ‘M8080A BUS PARAMETERS READ CYCLE ‘Symbol Parameter Min Max [unit ‘Comments Tar Adr or SS | Setup toRD 1 o ns Tra Adr or CS T Hold from AD T 0 ns Tao Data Access from AD | ° 300 ns (Note 2) Tor DB — Float Delay trom RD T 20 150 ns Tar FD wiath 250 ns WRITE CYCLE ‘Symbol Parameter Min Max Unit ‘Comments Taw. Adr Setup to WA | 20 ns Twa Adr Hold from WA T 35 ns Tow Data Sotup to WAT 200, ns Two Data Hold from WAT 10 ns Tw WR Wiath 175 as OTHER TIMING ‘Symbol Parameter Min [Max [unit | Comments Trstw__| Reset Pulse width 300 08 Trsto Power Supply T (Vcc) Setup to Reset | 500 Hs it? Signal Rise Time 20 ns Tr Signal Fall Time 20 ns instal Reset to First OWA 2 tov Nores: 1. All timing measurements are made at the following reference voltages unlose specitied otherwise: 1 2.0 ‘TRACKING PARAMETERS. Suppose the following timing equation is being eval uated, Signals labeled as Tracking Parameters (footnotes 4-7 under A.C. Specifications) are signals that fol Tagny + Tawar < 150 ns (ow similar paths through the slicon die, The propa- {gation speed of these signals varies in the manufac- and only minimum specifications exist for Ta and Tp. turing process but the relationship between all these _f Taquny is Used, and if Ta and Tp are tracking pa- parameters is constant. The variation is less than or rameters, Taqax) can be taken as Tain) + 50 ns. ‘equal to 50 ns. Tagan + Taqany" + 50 ns) < 150.ne “i Tp and Ta are tracking paramotors, 17-18intel ner A.C. TESTING INPUT, OUTPUT WAVEFORM. A.C, TESTING LOAD CIRCUIT InpuvOurput 000866-9 coaees-« [AC. Testing: inputs are Driven at 2.4V fora Log "1" and 048 = 180 oF for 8 Logic "0" Tering Measuromerts are Made at 20V for a _ Incados Jig Capacitance ‘and 08V or a Logic" WAVEFORMS NOT READY SEQUENCE ceo sc Don tant Ommintel M8257 WAVEFORMS—DMA MODE CONSECUTIVE CYCLES AND BURST MODE SEQUENCE i steledatelolelelelalele dads oon965-7 NOTE: ‘The clock waveform is duplicated for clarity. The M8257 requires only one clock input. 17-20intel M8257 WAVEFORMS—PERIPHERAL MODE WRITE RESET READ 17-21