KIM TRA CUI K

GV: H Vit Vit, B mn : KTMT

CU TRC MY TNH

Thi gian: 90 pht

c php s dng ti liu trong thi gian lm bi

Cu 1: (1)
Pht biu cc Hazard trong on m MIPS sau khi chy trn b x l pineline 5 stages:
-

Ph thuc no l Data Hazard cn gii quyt bng Forwarding.

Ph thuc no l Data Hazard cn gii quyt bng stall (bubble) v forwarding.

Add $3, $4, $2
Sub $5, $3, $1
Lw

$6 , 200($3)

Add $7, $3, $6

Li gii:

C nhng Data Hazard sau v cch gii quyt:

Gia lnh

V lnh

Thng qua thanh ghi

Cu 2: (1) Xt on m MIPS sau khi chy trn b x l pinelined 5 stages:

Sw

$6, 0($7)

Lw

$8, 0($7)

Add

$9, $8, $2

Li gii:
1. Pht hin nhng Hazard v cch gii quyt ca b x l:

Gii quyt bng

2. Compiler c th thay i on m trn trnh vic phi chn thm 1 bubble nh th no ?

Cu 3: (1) Cho a ch word, cho thm 1 Block = 8 hay 16 works g , theo kiu (direct- mapped, fully)
Word address

Memory Block address

Hit or Miss type

1
134
121
1
135
213
162
161
2
44
41
221
Ni dung sau cng ca Cache:
Block
Data at Memory block Address
0
1
2
3
4
5
6
7

Block
8
9
10
11
12
13
14
15

Cu 4: (1) Cho h thng nh sau:

a. Direct-mapped: Hit Time: 1 cycle, Hit Rate: 80 %
b. 2-way set Associative: Hit Time: 2 cycles, Hit Rate: 90 %
c. Full Associative: Hit Time: 3 cycles, Hit Rate: 95 %
Kiu thc hin no cho h thng nh nhanh nht ?

Data at Memory block Address

Li gii: Tnh thi gian truy cp trung bnh ln lt cho 3 kiu cache :
a.

b.

c.

Nh vy: Cache L1 thc hin theo kiu .

Cu 5: (1) Cho h thng nh sau:

Level

Hit Time

L1

1 cycle

Hit Rate
002/

Bi ni ging nh bi trong v thy

dy. tnh t di tnh ln

a.
b.

Gim Miss Rate i mt na.

Tng gp i Miss Rate.

Li gii:
a. Tnh thi gian truy cp trung bnh ln lt vi gi tr miss rate ch cn mt na cho Main
Memory, L2 v L1:
Main Memory:
L2 Cache :

L1 Cache :

Nh vy gim Miss Rate i mt na vi l tt nht.

b. Tnh thi gian truy cp trung bnh ln lt vi gi tr miss rate tng gp i cho Main Memory,
L2 v L1:
Main Memory:
L2 Cache :

L1 Cache :

Nh vy tng gp i Miss Rate vi l tt nht.

Cu 6: (1) Tnh ton tng s bit cn thit thc hin i vi tng b nh cache c kch c 16 words
c thc hin khc nhau sau y ( b nh nh a ch theo word v s dng a ch 32-bit)
a. Direct mapped, block size: 1 word, write-back:

b. Direct mapped, block size: 4 word, write-back:

c. 2-way set associative, block size: 1 word, write-through:

d. Full associative, block size: 1 word, write-back, fetch on write miss:

Cu 7: (1)
Word Address

Memory block Address

Hit or Miss Type

1
4
8
5
20
17
39
56
9
11
4
43
5
6
9
17

Ni dung sau cng trong cache:

Set
Data at Memory block address
0
(8)
1
2
3
4
5
6
7

Compulsory

Data at Memory block address

(56)

Cu 8: (1)
p dng Miss Rate t cu 7. Cho thi gian stall time tnh theo chu k ca 3 level. Mi level cho chu k truy
cp vo chng ( n v l cycles). Tnh thi gian truy cp trung bnh ca mi level.
Cu b l tnh hiu sut.
Cu 9: (1) Tm m my (nh phn) cho 2 lnh ca MIPS : Shift Left Logical (sll) v No Operation (nop). C
nhn xt g khi so snh 2 lnh ny ?
Li gii:
Sll $10, $15, 20:
Nop :

Nhn xt:

Cu 10: (1) Thit k Datapath v Control cho 2 lnh sll v nop ca b x l single cycle ( Lu v cc gi
tr ca tn hiu iu khin cn thit)