MC LC

Li M u ...................................................................................................... 1
Chng 1 TNG QUAN V CORTEX ........................................................... 3
1.1. Cc phin bn kin trc ARM ..................................................................... 3
1.2 B x l Cortex v n v x l trung tm Cortex ........................................... 4
1.3 n v x l trung tm Cortex (Cortex CPU) ................................................ 5
1.3.1 Kin trc ng ng (Pipline) ................................................................... 5
1.3.2 M hnh lp trnh (Programmers model) ................................................. 5
1.3.2.1 Thanh ghi XPSR .................................................................................... 6
1.3.3 Cc ch hot ng ca CPU ................................................................. 7
1.3.4 Tp lnh Thumb-2.................................................................................... 8
1.3.5 Bn b nh (Memory Map) ................................................................. 9
1.3.6 Truy cp b nh khng xp hng (Unaligned Memory Accesses) ......... 11
1.3.7 Di Bit (Bit Banding) ............................................................................. 12
1.4 B x l Cortex .......................................................................................... 13
1.4.1 Bus ......................................................................................................... 14
1.4.2 Ma trn Bus ............................................................................................ 14
1.4.3 Timer h thng (System timer) ............................................................... 14
1.4.4 X l ngt (Interrupt Handling)............................................................... 15
1.4.5 B iu khin vector ngt lng nhau (Nested Vector Interrupt
Controller)........................................................................................................ 15
1.4.5.1 Nhp v thot khi mt ngoi l ca NVIC (NVIC Operation
Exception Entry And Exit) ............................................................................... 16
1.4.5.2

Cc ch x l ngt cao cp (Advanced Interrupt Handling

Modes)............................................................................................................. 17
1.4.5.2.1 Quyn u tin ngt (Interrupt Pre-emption) ..................................... 17
1.4.5.2.2 K thut Tail Chaining trong NVIC ............................................... 17
1.4.5.3 Cu hnh v s dng NVIC.................................................................. 19
1.4.5.3.1 Bng vector ngt (Exception Vector Table)...................................... 19
1.5 Cc ch nng lng .............................................................................. 24

1.5.1 Cch i vo ch nng lng thp ca CPU Cortex ............................ 24

1.5.2 Khi h tr g li CoreSight ................................................................ 26
Chng 2 KIN TRC H THNG CA ARM CORTEX ........................ 28
2.1 Cu trc b nh ........................................................................................... 28
2.2 Ti a hiu nng.......................................................................................... 29
2.2.1 Vng Kha Pha (Phase Lock Loop) .......................................................... 30
2.2.2 Cu hnh cho bus ...................................................................................... 32
2.2.3 Flash Buffer ............................................................................................. 33
2.2.4 Direct Memory Access ............................................................................. 34
Chng 3 NGOI VI ..................................................................................... 39
3.1 Ngoi vi a dng ......................................................................................... 39
3.1.1 Cc cng I/O a dng ............................................................................... 39
3.1.1.1 Chc nng thay th (Alternate Function) ............................................ 41
3.1.1.2 Event Out .............................................................................................. 42
3.1.2. Ngt ngoi (EXTI) ................................................................................. 42
3.1.3 ADC ........................................................................................................ 43
3.1.3.1 Thi gian chuyn i v nhm chuyn i ............................................ 44
3.1.3.2 Analogue WatchDog............................................................................. 46
3.1.3.3 Cu hnh ADC ...................................................................................... 47
3.1.3.4. Dual mode ........................................................................................... 48
3.1.4.1. C hai khi ADC cng hot ng cng ch Regular hoc Injected
......................................................................................................................... 49
3.1.4.2. C hai khi cng hot ng 2 ch Regular v Injected xen k ...... 49
3.1.4.3. Hot ng xen k nhanh v chm Regular............................................ 50
3.1.4.4. Ch kch hot thay th ..................................................................... 50
3.2.1. Khi Capture/Compare ........................................................................... 52
3.2.2 Khi Capture ........................................................................................... 53
3.2.3 Ch PWM Input .................................................................................. 54
3.2.4 Ch PWM........................................................................................... 55
3.2.5 Ch One Pulse..................................................................................... 56

3.3 ng b ho cc b nh thi...................................................................... 56
3.4 RTC v cc thanh ghi Backup ..................................................................... 58
3.5 Kt ni vi cc giao tip khc ...................................................................... 59
3.5.1 SPI ........................................................................................................... 59
3.5.2 I2C ........................................................................................................... 60
3.5.3 USART .................................................................................................... 61
3.5.4 CAN ........................................................................................................ 63
3.5.5 USB ......................................................................................................... 65
Chng 4 LP TRNH IU KHIN NG C BC S DNG
ARM-STM32F103 ......................................................................................... 67
4.1 Gii thiu Kit STM32 STM32F103 ......................................................... 67
4.1.1 Mch CPU .............................................................................................. 68
4.1.2 Mch giao tip RS232 qua USART1 ..................................................... 69
4.1.3 Mch cp ngun v USB ....................................................................... 69
4.1.4 Mch giao tip vi LCD, np v g ni chng trnh qua JTAG, cc
mch giao tip CAN/ PS2 ............................................................................... 70
4.1.5 Mch th nh SD/MMC qua giao tip SPI ............................................ 70
4.2 iu khin ng c bc vi Kit STM32 STM32F103 ......................... 70
4.2.1.Thit k mch Motor Driver: ................................................................. 70
4.2.2. Chng trnh iu khin Step Motor: ................................................... 71
Kt Lun......................................................................................................... 74
Ti liu tham kho: ....................................................................................... 75

Li M u
Ngy nay vi s pht trin ca ngnh in t v ng dng in t
gip s sng to ca con ngi tr thnh hin thc. Cc lnh vc ca cuc
sng u p dng nhng thit b in t v dng nh nhn u trong gia nh
chng ta cng c thit b in t. Ngnh in t v ng dng in t to
ch ng v khng nh c tm quan trng ca mnh i vi nhu cu ca
con ngi.
Vi nhng ng dng cho cc h thng nhng ngy cng tr nn ph
bin: t nhng ng dng n gin nh iu khin mt cht n giao thng
nh thi, m sn phm trong mt dy chuyn sn xut, iu khin tc
ng c in mt chiu, thit k mt bin qung co dng Led ma trn, mt
ng h thi gian thc .n cc ng dng phc tp nh h thng iu khin
robot, b kim sot trong nh my hoc h thng kim sot cc my nng
lng ht nhn. Cc h thng t ng trc y s dng nhiu cng ngh
khc nhau nh cc h thng t ng hot ng bng nguyn l kh nn, thy
lc, rle c in, mch in t s, cc thit b my mc t ng bng cc cam
cht c kh. Cc thit b, h thng ny c chc nng x l v mc t ng
thp so vi cc h thng t ng hin i c xy dng trn nn tng ca
cc h thng nhng.
Trong nhiu nm trc, cc dng vi iu khin 8051 c sinh vin
dng nhiu vi tnh nng n gin, d s dng; AVR c s dng nhiu
trong cc cuc thi Robocon nh tc s l kh cao, n nh; PIC vi u th
tc cao, chi ph thp hn cng c nghin cu, s dng nhiu, c bit
trong cc cuc thi lp trnh tay ngh khu vc v th gii. Nhng trong mt vi
nm tr li y, c mt dng vi iu khin mi, cng ngy cng nm v tr
quan trng trong cc lnh vc i hi tc x l cao nh in t vin thng,
sn xut cc dng din thoi di ng smartphone, gim st, an ninh l
h vi iu khin ARM. Vi rt nhiu th h ra i, vi nhiu tnh nng , cng
dng khc nhau.

Vi nhiu tnh nng vt tri ca ARM v xu th la chn dng vi iu

khin mi Vit Nam nn trong ti nghin cu khoa hc ny, di s gip
ca Thy Nguyn Huy Dng, em thc hin ti nghin cu ng dng
lp trnh iu khin ng c bc s dng chip ARM Cortex M3
STM32F103RC.

Chng 1
TNG QUAN V CORTEX
B x l Cortex l th h li nhng k tip t ARM. Cortex tha k cc u
im t cc b x l ARM trc , n l mt li x l hon chnh, bao gm
b x l trung tm Cortex v mt h thng cc thit b ngoi vi xung quanh,
Cortex cung cp phn x l trung tm ca mt h thng nhng. p ng
yu cu kht khe v a dng ca cc h thng nhng, b x l Cortex gm c
3 nhnh, c biu hin bng cc k t sau tn Cortex nh sau:
Cortex-A : b vi x l dnh cho h iu hnh v cc ng dng ca
ngi dng phc tp. H tr cc tp lnh ARM, Thumb v Thumb2.
Cortex-R : b x l dnh cho cc h thng i hi khc khe v tnh thi
gian thc. H tr cc tp lnh ARM, Thumb, v Thumb-2.
Cortex-M : b x l dnh cho dng vi iu khin, c ti u ha cho
cc ng dng nhy cm v chi ph. Ch h tr tp lnh Thumb-2.
Con s nm cui tn Cortex cho bit mc hiu sut tng i, vi 1 l thp
nht v 8 l cao nht. Hin nay dng Cortex-M c mc hiu sut cao nht l
mc 3. STM32 da trn b x l Cortex-M3.
1.1. Cc phin bn kin trc ARM

Hinh 1.1.Cc phin bn kin trc ca li ARM

Tnh n thi im hin ti th phin bn kin trc mi nht ca li ARM

l ARMv7 (Trc c ARMv4, ARMv5, ARMv6). B x l Cortex-M3 da
trn kin trc ARMv7 M v c kh nng thc hin tp lnh Thumb-2.
1.2 B x l Cortex v n v x l trung tm Cortex

Hnh 1.2. Kin trc vi x l ARM Cortex-M3

Thut ng b x l Cortex (Cortex processor) v n v x l trung tm
Cortex (Cortex CPU) s c s dng phn bit gia nhng li Cortex
hon chnh v b x l trung tm RISC ni (internal RISC CPU).
4

1.3 n v x l trung tm Cortex (Cortex CPU)

Trung tm ca b x l Cortex l mt CPU RISC 32-bit. CPU ny c
mt phin bn c n gin ha t m hnh lp trnh (programmers model)
ca ARM7/9 , nhng c mt tp lnh phong ph hn vi s h tr tt cho cc
php ton s nguyn, kh nng thao tc vi bit tt hn v kh nng p ng
thi gian thc tt hn.
1.3.1 Kin trc ng ng (Pipline)
CPU Cortex c th thc thi hu ht cc lnh trong mt chu k n. Ging
nh CPU ca ARM7 v ARM9, vic thc thi ny t c vi mt ng ng
ba tng. Tuy nhin Cortex-M3 kh nng d on vic r nhnh gim thiu
s ln lm rng (flush) ng ng.

Hinh 1.3. Kin trc ng ng ca ARM Cortex-M3

1.3.2 M hnh lp trnh (Programmers model)
CPU Cortex l b x l da trn kin trc RISC, do h tr kin trc np
v lu tr (load and store architecture). thc hin lnh x l d liu, cc
ton hng phi c np vo mt tp thanh ghi trung tm, cc php tnh d liu
phi c thc hin trn cc thanh ghi ny v kt qu sau c lu li trong
b nh.

Hinh 1.4. Kin trc load v store ca ARM Cortex-M3

Tp thanh ghi ny bao gm mi su thanh ghi 32-bit.

Cc thanh ghi R0-R12 l cc thanh ghi n gin, c th c dng
cha cc bin ca chng trnh.
Thanh ghi R13 c dng nh l con tr ngn xp (stack pointer).
Trong CPU Cortex c hai ngn xp c gi l main stack v process
stack.
Thanh ghi R14 tip theo c gi l thanh ghi lin kt (link register).
Thanh ghi ny c s dng lu tr cc a ch tr v khi mt
cuc gi th tc (call a procedure) c thc hin. iu ny cho php
CPU Cortex thc hin rt nhanh vic nhp v thot khi mt th tc
(fast entry and exit to a procedure).
Thanh ghi R15l bm chng trnh (Program Counter)

Hinh 1.5. M hnh lp trnh ca ARM Cortex-M3

1.3.2.1 Thanh ghi XPSR
Ngoi tp thanh ghi trung tm cn c mt thanh ghi ring bit c
gi l thanh ghi trng thi chng trnh (Program Status Register). XPSR cha
mt s cc vng chc nng quan trng nh hng n vic thc thi ca CPU
Cortex.

Hinh 1.6. Thanh ghi trng thi chng trnh ca CPU Cortex
6

 Nm bit u l nhng c m iu kin v c gn bit hiu (aliased)

nh thanh ghi trng thi chng trnh ng dng. Bn c N, Z, C,
V (Negative, Zero, Carry v Overflow) s c thit lp v xa ty
thuc vo kt qu ca mt lnh x ld liu. Bit Q l c s dng bi
cc lnh ton hc DPS ch ra rng mt bin t gi tr ti a hoc
gi tr ti thiu ca n.
Ging nh tp lnh ARM32-bit, cc lnh Thumb-2 ch c thc hin
nu m iu kin ca lnh ph hp vi trng thi ca cc c trong
thanh ghi trng thi chng trnh ngdng (Application Program
Status Register). Nu m iu kin ca lnh khng ph hp, th lnh i
ngang qua ng ng nh l mt lnh NOP (lnh ny khng lm g c).
iu ny m bo rng cc lnh i qua ng ng mt cch trn tru v
gim thiu lm rng ng ng.
1.3.3 Cc ch hot ng ca CPU
B x l Cortex c hai ch hot ng: ch Thread v ch
Handler. CPU s chy ch Thread trong khi n ang thc thi ch
nn khng c ngt xy ra v s chuyn sang ch Handler khi n ang thc
thi cc ngt c bit (exceptions).

Ngoi ra, CPU Cortex c th thc thi

m trong ch c quyn hoc khng c quyn (privileged or nonprivileged mode). Trong ch c quyn, CPU c quyn truy cp tt c cc
lnh. Trong ch khng co c quyn, mt s lnh b cm truy cp (nh lnh
MRS v MSR cho php truy cp vo xPSR v cc trng ca n). Ngoi ra,
vic cp cc thanh ghi iu khin h thng trong b vi x l Cortex cng b
cm. Cch s dng ngn xp (stack) cng c th c cu hnh. Ngn xp
chnh (main stack-R13) c th c s dng bi c hai ch Thread v
Handler. Ch Handler c th c cu hnh s dng ngn xp qu trnh
(process stack-R13 banked register).

Hnh 1.7.M hnh hot ng ca ch Thread v Handler

Sau khi reset, b x l Cortex s chy trong cu hnh phng
(flat configuration). C hai ch Thread v Handler c thc thi trong
ch c quyn (privileged mode), do , khng c s gii hn no v
quyn truy cp vo bt k ti nguyn ca b x l. C hai ch Thread v
Handler u s dng ngn xp chnh.
1.3.4 Tp lnh Thumb-2
Cc CPU ARM7 v ARM9 c th thc thi hai tp lnh: ARM 32-bit v
Thumb 16-bit. iu ny cho php ngi pht trin ti u ho chng
trnh ca mnh bng cch la chn tp lnh no c s dng cho th tc
khc nhau: lnh 32-bit tng tc x l v lnh 16-bit nn m chng
trnh. CPU Cortex c thit k thc thi tp lnh Thumb-2, l mt s pha
trn ca lnh 16-bit v 32-bit. Tp lnh thumb-2 ci tin 26% mt m so
vi tp lnh ARM 32-bit v 25% hiu sut so vi tp lnh Thumb 16-bit. Tp
8

lnh Thumb2 c mt s lnh nhn c ci tin, c th thc hin trong mt

chu k n v kh nng thc hin php chia bng phn cng v ch mt t 27 chu k.

Hnh 1.8. th biu din hiu nng ca b x l Cortex

im chun b x l Cortex (Cortex

processor

benchmark) cho mt

mc thc hin l 1,25 DMIPS/MHz, cao hn so vi ARM7 (0.95

DMIPS/MHz vi tp lnh ARM v 0.74 DMIPS/MHz vi tp lnh Thumb) v
ARM9
1.3.5 Bn b nh (Memory Map)
B x l Cortex-M3 l mt li vi iu khin c tiu chun ha, nh
vy n c mt bn b nh cng c xc nh. Mc d c nhiu bus ni, bn
b nh ny l mt khng gian a ch 4 Gbyte tuyn tnh. Bn b nh
ny l chung cho tt c cc thit b da trn li Cortex.

Hnh 1.9.Bn b nh tuyn tnh 4Gbyte ca b x l Cortex-M3

Mt Gbyte b nh u tin c chia u cho mt vng m (code
region) v mt vng SRAM (SRAM region). Khng gian m c ti u ha
thc thi t bus I-Code. Tng t, SRAM c ni n bus D-Code. Mc d
m c th c np v thc thi t SRAM, cc lnh s c ly bng cch s
dng bus h thng, v vy phi chu thm mt trng thi ch (an extra wait
state). Tc l m chy trn SRAM s chm hn so vi t b nh Flash trn
chip (on-chip) nm trong vng m. Vng 0,5 Gbyte tip theo ca b nh l
vng ngoi vi trn chip, tt c thit b ngoi vi c cung cp bi nh sn
xut vi iu khin s c t ti vng ny. Vng 1 Mbyte u tin gm c
SRAM (mu vng nht) v vng ngoi vi (mu hng nht) c nh a ch
theo bit, s dng mt k thut c gi l di bit (bit banding). T tt c
SRAM v cc thit b ngoi vi ngi dng (user peripherals) trn STM32 c
t ti vng ny, v tt c cc v tr b nh ca nhng vng ny trn STM32
10

u c th c thao tc theo word-wide hoc bitwise. Khng gian a ch 2

Gbyte tip theo c phn cho b nh ngoi- nh x SRAM v thit b
ngoi vi (external RAM v external Device). Vng 0,5 Gbyte cui cng
c phn cho cc thit b ngoi vi bn trong ca b x l Cortex v mt khu
vc dnh cho cc ci tin trong tng lai ca nh sn xut chip cho b x l
Cortex. Tt c cc thanh ghi ca b x l Cortex c t v tr c nh cho
tt c vi iu khin da trn li Cortex. iu ny cho php m chng trnh
d dng c chuyn gia cc bin th STM32 khc nhau v cc vi iu khin
da trn li Cortex ca cc nh sn xut chip khc.
1.3.6 Truy cp b nh khng xp hng (Unaligned Memory Accesses)
Tp lnh ARM7 v ARM9 c kh nng truy cp cc bin c du v
khng du c kch thc byte, half word (thng l 2byte) v word (thng
l 4byte). iu ny cho php CPU h tr cc bin s nguyn m khng cn
n th vin phn mm h tr, thng c yu cu i vi vi iu khin 8 v
16-bit. Tuy nhin, cc phin bn CPU ARM trc gp bt li ch, n ch
c th truy cp d liu kch thc l word hoc half word. iu ny hn ch
kh nng ca trnh lin kt ca trnh bin dch (compiler linker) trong vic
ng gi d liu vo SRAM v nh vy mt s SRAM s b lng ph (Vic
lng ph ny c th ln n 25% ty thuc vo s kt hp ca cc bin c s
dng). B x l Cortex-M3 c th truy cp b nh khng xp hng, vic
m bo rng SRAM c s dng mt cch hiu qu.

Hnh 1.10.Kh nng truy cp b nh khng xp hng ca b x l Cortex-M3

so vi cc phin bn CPU ARM trc
11

CPU Cortex c cc ch nh a ch cho word, half word v byte,

nhng c th truy cp b nh khng xp hng (unaligned memory). iu ny
cho php trnh lin kt ca trnh bin dch t do sp xp d liu chng trnh
trong b nh. Vic b sung h tr tnh nng di bit (bit banding) vo CPU
Cortex cho php cc c chng trnh c ng gi vo mt bin word hoc
half-word hn l s dng mt byte cho mi c.
1.3.7 Di Bit (Bit Banding)
Cc phin bn CPU ARM7 v ARM9 trc ch c th thc hin thao
tc bit trn b nh SRAM v vng nh thit b ngoi vi bng cch dng cc php
ton AND v OR. iu ny i hi thao tc c sa i ghi (READ
MODIFY WRITE operation), thao tc ny s tn nhiu chu k thc hin
thit lp v xo cc bit ring bit v cn nhiu khng gian m cho mi bit.

Hnh 1.11.Thao tc c sa i ghi ca ARM7 v ARM9 v k thut di bit

ca b x l Cortex-M3
K thut di Bit cho php b x l Cortex-M3 thao tc cc bit trong khi vn
gi c s lng bng bn dn mc ti thiu.
khc phc nhng hn ch trong cc thao tc bit CPU ARM7 v
ARM9, c th a ra cc lnh chuyn dng thit lp hoc xo bit, hoc mt
b x l Boolean y , nhng iu ny s lm tng kch thc v s phc
tp ca CPU Cortex. Thay vo , mt k thut gi l di bit cho php thao tc
bit trc tip trn cc phn khng gian b nh ca cc thit b ngoi vi v
SRAM, m khng s cn bt k lnh c bit no. Cc khu vc nh a ch bit
12

ca bn b nh Cortex bao gm vng bit band (ln n 1Mbyte b nh

thc hoc cc thanh ghi ngoi vi) v vng bit hiu bit band (bit band Alias
region) chim n 32Mbyte ca bn b nh. Di Bit hot ng bng cch
nh x mi bit trong vng bit band ti mt a ch word trong vng Alias. V
vy, bng cch thit lp v xo a ch word c t bit hiu (aliased word
address) chng ta c th thit lp v xo cc bit trong b nh thc.

Hnh 1.12.Di bit ca vng b nh SRAM v cc ngoi vi

Di Bit c h tr trn 1Mb u tin ca khu vc SRAM v ngoi vi .
N bao gm tt c cc ti nguyn ca STM32.
K thut Bit Banding cho php thc hin thao tc bit ring l m khng cn
bt k lnh c bit no, iu ny gi cho kch thc tng th ca li Cortex
nh nht c th. Trong thc t, chng ta cn phi tnh ton a ch ca cc
word nm trong vng Bit Band Alias cho mt v tr b nh nht nh trong
khng gian b nh ca thit b ngoi vi hoc SRAM. Cng thc tnh ton
alias address nh sau:
a ch trong khu vc Bit Band Alias = Bit band alias base address + bit
word offset
bit word offset = Byte offset from bit band base x 0x20 + bit number x 4
1.4 B x l Cortex
B x l Cortex c to thnh t CPU Cortex kt hp vi nhiu thit b
ngoi vi nh Bus, system timer

13

1.4.1 Bus
B vi x l Cortex-M3 c thit k da trn kin trc Harvard vi bus
m v bus d liu ring bit . Chng c gi l cc bus Icode v Dcode. C
hai bus u c th truy cp m v d liu trong phm vi b nh t
0x00000000-0x1FFFFFFF. Mt bus h thng b sung c s dng truy
cp vo khng gian iu khin h thng Cortex trong phm vi 0x20000000 0xDFFFFFFF v 0xE0100000 - 0xFFFFFFFF. H thng g li trn chip ca
Cortex c thm mt cu trc bus c gi l bus ngoi vi ring.
1.4.2 Ma trn Bus
Bus h thng v bus d liu c kt ni vi vi iu khin bn ngoi
thng qua mt tp cc bus tc cao c sp xp nh mt ma trn bus. N
cho php mt s ng dn song song gia bus Cortex v cc bus ch (bus
master) khc bn ngoi nh DMA n cc ngun ti nguyn trn chip nh
SRAM v cc thit b ngoi vi. Nu hai bus ch (v d CPU Cortex v mt
knh DMA) c gng truy cp vo cng mt thit b ngoi vi, mt b phn x
ni s gii quyt xung t v cho truy cp bus vo ngoi vi c mc u tin cao
nht. Tuy nhin, trong STM32 khi DMA c thit k lm vic ha hp vi
CPU Cortex.
1.4.3 Timer h thng (System timer)
Li Cortex c mt b m xung 24-bit, vi tnh nng t ng np li
(auto reload) gi tr b m v to s kin ngt khi m xung zero. N c
to ra vi dng cung cp mt b m thi gian chun cho tt c vi iu khin
da trn Cortex. ng h SysTick c s dng cung cp mt nhp p
h thng cho mt RTOS, hoc to ra mt ngt c tnh chu k phc v
cho cc tc v c lp lch. Thanh ghi trng thi v iu khin ca SysTick
trong n v khng gian iu khin h thng Cortex-M3 cho php chn cc
ngun xung clock cho SysTick. Bng cch thit lp bit CLKSOURCE,
ng h SysTick s chy tn s ng bng tn s hot ng ca CPU.
Khi bit ny c xa, SysTick s chy tn s bng 1/8 CPU.

14

Hnh 1.13. Cc thanh ghi trng thi v iu khin ca SysTick

ng h SysTick c ba thanh ghi. Gi tr hin ti v gi tr ti (current value
v reload value) nn c khi to vi chu k m. Thanh ghi trng thi v
iu khin c mt bit cho php (ENABLE bit) bt u chy b m thi
gian v mt bit TICKINT cho php tn hiu ngt.
1.4.4 X l ngt (Interrupt Handling)
Mt trong nhng ci tin quan trng ca li Cortex so vi cc CPU ARM
trc l cu trc ngt ca n v x l cc ngt ngoi l (exception handling).
1.4.5 B iu khin vector ngt lng nhau (Nested Vector Interrupt
Controller)
NVIC (Nested Vector Interrupt Controller) l mt n v tiu chun bn
trong li Cortex. iu ny c ngha l tt c cc vi iu khin da trn li
Cortex s c cng mt cu trc ngt, bt k nh sn xut chip l ST, Atmel,
Luminary hoc NXP...

Hnh 1.14. Cu trc ca NVIC trong b x l Cortex

15

NVIC cng c thit k c mt tr khi p ng ngt rt thp. y

l mt c im ca chnh bn thn b NVIC v ca tp lnh Thumb-2, n cho
php thc thi cc lnh nhiu chu k (multi-cycle instructions) nh lnh ti v
lu tr nhiu d liu ( load and store multiple instruction) c th c ngt khi
ang thc thi. Do tr khi p ng ngt l xc nh, vi nhiu c im
x l ngt tin tin, n h tr rt tt cho cc ng dng thi gian thc.
Nh tn gi ca n,NVIC c thit k h tr cc ngt lng nhau
(nested interrupts) v trnSTM32 c16 cp u tin ngt.
Mc d NVIC l mt n v t chun bn trong li Cortex, gi cho s
bng bn dn mc ti thiu, s ng tn hiu ngt i vo NVIC c th cu
hnh khi vi iu khin c thit k. NVIC c mt ngt khng che mt n
(non-maskable interrupt) v hn 240 ng tn hiu ngt bn ngoi v c th
c kt ni vi ngoi vi ngi dng. Ngoi ra cn c thm 15 ngun ngt bn
trong li Cortex, c s dng x l cc ngt ni ngoi l trong li Cortex.
B NVIC ca STM32 c tng hp vi ti a l 43 ng ngt che mt
n (maskable interrupt lines).
1.4.5.1 Nhp v thot khi mt ngoi l ca NVIC (NVIC Operation
Exception Entry And Exit)
Khi mt ngt c sinh ra bi mt thit b ngoi vi, NVIC s kch khi
CPU Cortex phc v ngt. Khi CPU Cortex i vo ch ngt ca n, n s
y mt tp cc thanh ghi vo vng ngn xp (stack). Thao tc ny c thc
hin trong vi chng trnh (microcode), v vy khng cn vit thm bt k lnh
no trong m ng dng. Trong khi khung ngn xp (stack frame) ang c
lu tr, a ch bt u ca trnh dch v ngt c ly v trn bus
Icode (instruction bus). V vy, thi gian t lc ngt c sinh ra cho ti khi
lnh u tin ca trnh dch v ngt c thc thi ch c 12 chu k.

16

Hnh 1.15. Stack frame trong ch ngt

Khi kt thc qu trnh phc v ngt, khung ngn xp c khi phc t
ng bi vi chng trnh (microcode), song song vi thao tc th a ch tr
v c ly v, chng trnh nn c th tip tc thc hin ch sau 12 chu k.

Hnh 1.16. p ng thi gian khi mt ngt bt k xy ra ca Cortex-M3

1.4.5.2

Cc ch x l ngt cao cp (Advanced Interrupt Handling

Modes)
Vi kh nng x l mt ngt n rt nhanh, NVIC c thit k x l
hiu qu nhiu ngt trong mt ng dng i hi khc khe tnh thi gian thc.
NVIC c mt s phng php x l thng minh nhiu ngun ngt, sao cho
tr gia cc ngt l ti thiu v m bo rng cc ngt c mc u tin cao
nht s c phc v u tin.
1.4.5.2.1 Quyn u tin ngt (Interrupt Pre-emption)
NVIC c thit k cho php cc ngt c mc u tin cao s dnh quyn
u (pre-empt) so vi mt ngt c mc u tin thp hn ang chy.
1.4.5.2.2 K thut Tail Chaining trong NVIC
Nu mt ngt c mc u tin cao ang chy v ng thi mt ngt c mc
17

u tin thp hn cng c kch hot, NVIC s dng mt phng php gi l

Tail Chaining m bo thi gian tr l ti thiu gia cc ln phc v ngt.
Nu hai ngt c nng ln, ngt c mc u tin cao nht s c phc trc
v s bt u thc hin ch sau 12 chu k xung nhp k t lc xut hin ngt.
Tuy nhin, khi n cui trnh phc v ngt CPU Cortex khng tr v chng
trnh ng dng nn, v vy m stack frame ca ngt ny khng c khi phc,
thay vo ch c a ch ca hm phc v ngt c mc u tin cao nht k
tip c ly v.

Hnh 1.17. p ng thi gian khi hai ngt xy ra ng thi ca Cortex-M3

iu ny ch mt 6 chu k xung nhp v sau trnh phc v ngt k
tip c th bt u c thc thi. Vo cui cc ngt ang ch, ngn xp
c khi phc v a ch tr v c ly, tip chng trnh ng dng nn
c th bt u thc thi ch trong 12 chu k xung nhp. Nu mt ngt c mc u
tin thp xut hin trong khi mt ngt khc ang thc thi chun b thot khi
trnh phc v ngt, thao tc POP (ly d liu t ngn xp) s b b qua v con
tr stack s c cun v gi tr ban u c th tip tc lu tr stack frame
ca ngt mi xut hin, s c mt tr 6 chu k xung nhp cho ti khi a ch
ca ISR mi c ly v. iu ny to ra mt tr t 7-18 chu k xung
nhp trc khi trnh phc v ngt mi c th bt u c thc hin.

Hnh 1.18. p ng thi gian khi hai ngt xy ra ln lt ca Cortex-M3

18

Trong mt h thng thi gian thc thng xut hin tnh hung, trong
khi mt ngt c mc u tin thp ang c phc v, th ch c mt ngt c
mc u tin cao hn xut hin. Nu tnh hung ny xy ra trong qu trnh
PUSH d liu ln ngn xp, NVIC s chuyn sang phc v ngt u tin cao
hn. Vic PUSH d liu ln ngn xp c tip tc v s c ti thiu 6 chu k
xung nhp ti thi im ngt u tin cao hn xut hin, cho ti khi a ch ca
ISR mi c ly v.

Hnh 1.19. p ng thi gian khi ngt u tin cao n sau ca Cortex-M3
Sau khi ngt u tin cao hn thc hin xong, ngt u tin thp ban u s c
ni ui (tail chain) v bt u thc hin sau 6 chu k xung nhp.
1.4.5.3 Cu hnh v s dng NVIC
s dng NVIC cn phi qua ba bc cu hnh. u tin cu hnh
bng vector cho cc ngun ngt cn mun s dng. Tip theo cu hnh cc
thanh ghi NVIC cho php v thit lp cc mc u tin ca cc ngt trong
NVIC v cui cng cn phi cu hnh cc thit b ngoi vi v cho php ngt
tng ng.
1.4.5.3.1 Bng vector ngt (Exception Vector Table)
Bng vector ngt ca Cortex bt u di cng ca bng a ch. Tuy
nhin bng vector bt u ti a ch 0x00000004 thay v l 0x00000000 nh
ARM7 v ARM9, bn byte u tin c s dng lu tr a ch bt u
ca con tr ngn xp (stack pointer).

19

Type
No

Exception Type

Priority

of

Descriptions

Priority
1

Reset

fixed

Reset

3(Highest)
2

NMI

-2

fixed

Non-Maskable Intertupt

Hard Fault

-1

fixed

Default fault if other hander

not implemented

MemManage

settable MPU violation or access to

Fault
5

illegal locations

Bus Fault

settable Fault if AHB interface receives

error

Usage Fault

settable Exceptions due to program

errors

7-10 Reserved

N.A

N.A

11

SVCall

settable System Service call

12

Debug Monitor

settable Break points watch points,

external debug

13

Reserved

N.A

N.A

14

PendSV

settable Pendable request for System

Device

15

SYSTICK

settable System Tick Timer

16

Interrupt # 0

settable External Interrupt # 0

256 Interrupt # 240

247

settable

settable External Interrupt # 240

Hnh 1.20. Bng vector ngt ca Cortex-M3

Mi vector ngt c rng l bn byte v gi a ch bt u ca trnh phc
v ngt tng ng, 15 vector ngt u tin l cc ngt c bit ch xy ra trong
li Cortex, bao gm reset vector, non-maskable interrupt, qun l fault v
error, debug exceptions v ngt timer ca SysTick. Tp lnh Thumb-2 cng bao
20

gm lnh gi dch v h thng (system service call), khi c gi, n s to

ra mt ngt c bit. Cc ngt ngoi vi ngi dng bt u t vector 16,
c nh ngha bi nh sn xut v c lin kt n thit b ngoi vi.
Sau khi cu hnh xong bng vector ngt v nh ngha cc ISR
(Interrupt Service Routine), chng ta c th cu hnh NVIC x l ngt
ca timer SysTick qua hai bc: thit lp mc u tin ngt v sau cho
php ngt ngun. Cc thanh ghi NVIC nm trong vng iu khin h thng
ca Cortex-M3 v ch c th truy cp khi CPU ang chy ch c quyn
(privileged mode).

Hnh 1.21. Cc thanh ghi trng thi v iu khin ca NVIC

Cc ngt c bit bn trong Cortex c cu hnh thng qua cc thanh ghi
iu khin v thanh ghi cu hnh mc u tin ca h thng, trong khi cc
thit b ngoi vi ngi dng c cu hnh bng cch s dng cc thanh ghi
IRQ (Interrupt Request). Ngt ca SysTick l mt ngt c bit bn trong
Cortex v c x l thng qua cc thanh ghi h thng. Mt s ngt c bit
khc bn trong li Cortex lun trng thi cho php, bao gm cc ngt reset
v NMI (Non-Maskable Interrupt), tuy nhin ngt ca timer h thngSysTick li khng c kch hot bn trong NVIC. cu hnh ngt cho
SysTick, chng ta cn phi cu hnh cho SysTick chy v cho php ngt bn
trong SysTick:

Mc u tin ca mi exception (ngt c bit) bn trong Cortex c th

21

c ci t thng qua cc thanh ghi cu hnh mc u tin trong h thng.

Mc u tin ca cc exception nh Reset, NMI v hard fault c c
nh m bo rng li Cortex s lun lun sn sng cho mt exception
c bit trc. Mi exception c mt trng 8-bit nm trong ba thanh ghi v
mc u tin ca h thng. Tuy nhin STM32 ch thc hin 16 mc u
tin, nh vy ch c bn bit ca trng ny c dng. Mt iu quan trng
cn lu l mc u tin c thit lp bi bn bit c trng s cao nht.
Mi thit b ngoi vi c iu khin bi cc khi thanh ghi IRQ. Mi ngoi
vi c mt bit cho php ngt. Nhng bit nm trn hai thanh ghi cho php ngt
c chiu di l 32-bit. Bn cnh cng c cc thanh ghi tng ng cm bt
k mt ngun ngt. Ngoi ra NVIC cng bao gm cc thanh ghi bo
ch (pending) v kch hot (active) cho php xc nh tnh trng hin ti ca
mt ngun ngt.

Hnh 1.22. Cu hnh ngt cho thit b ngoi vi

Ch : Mi ngun ngt c mt bit cho php bn trong NVIC v khi
ngoi vi tng ng.
C 16 thanh ghi ci t mc u tin ngt. Mi thanh ghi c chia
thnh bn trng c rng l 8-bit cu hnh mc u tin, mi trng
c ch nh cho mt vector ngt nht nh. STM32 ch s dng mt na
22

ca trng ny (4-bit c trng s cao nht) thc hin 16 mc u tin ngt.

Mc nh cc trng ny xc nh 16 mc u tin vi mc 0 l cao
nht v 15 l thp nht. Ngoi ra c th sp sp cc trng u tin thnh cc
nhm (group) v nhm con (subgroup). iu ny khng to thm bt k
mc u tin no, nhng gip chng ta d qun l cc mc u tin khi chng
trnh ng dng c mt s lng ln cc ngt bng cch lp trnh trng
PRIGROUP trong thanh ghi iu khin reset v ngt mc ng dng.

Hnh 1.23. Thanh ghi iu khin reset v ngt mc ng dng

PRIGROU

Binary Point

Preemting Priority

P (3 Bits)

(group.sub)

(Group Priority)

Sub-Priority

Bits

Levels

Bits

Levels

011

4.0

Gggg

16

100

3.1

Gggs

101

2.2

Ggss

110

1.3

Gsss

111

0.4

Ssss

16

Hnh1.24. Cu hnh mc u tin thnh cc group v subgroup

Trng PRIGROUP gm 3-bit cho php chia trng 4-bit trong cc
thanh ghi ci t mc u tin thnh cc nhm v nhm con. V d, tr
gi ca PRIGROUP l 5 s to ra hai nhm, mi nhm vi 4 mc u tin.
23

Trong chng trnh ng dng , chng ta c th xc nh mt nhm cc ngt

c mc u tin cao v mt nhm c mc u tin thp. Bn trong mi nhm
chng ta c th xc nh cc mc cho nhm con nh mc thp, trung bnh,
cao v rt cao. Nh cp trn vic phn nhm s khng to ra thm
mc u tin no nhng cung cp mt ci nhn tru tng v cu trc ngt, iu
ny hu ch cho ngi lp trnh khi qun l mt s lng ln cc ngt. Vic
cu hnh ngt cho mt thit b ngoi vi cng ging vi cu hnh mt
exception bn trong Cortex. Trong trng hp ngt ca ADC, trc tin
chng ta phi thit lp vector ngt v cung cp hm phc v ngt-ISR:

Sau , ADC phi c khi to v cc ngt phi c cho php trong cc

thit b ngoi vi v cc NVIC:

1.5 Cc ch nng lng

CPU Cortex c mt ch ng (sleep mode), s t li Cortex vo ch
nng lng thp ca n v ngng thc thi cc lnh bn trong ca CPU
Cortex. Mt phn nh ca NVIC vn c hot ng bnh thng, do
ngt to ra t cc thit b ngoi vi ca STM32 c th nh thc li Cortex.
1.5.1 Cch i vo ch nng lng thp ca CPU Cortex
Li Cortex c th c t vo ch sleep ca mnh bng cch thc hin
lnh WFI (Wait For Interrupt) hoc WFE (Wait For S kin). Trong trng hp
thc thi lnh WFI, li Cortex s tip tc thc hin v phc v ngt ang ch x
l. Khi trnh phc v ngt-ISR kt thc, s c hai kh nng xy ra. Trc tin,
CPU Cortex c th tr v t ISR ny v tip tc thc hin chng trnh ng
24

dng nn nh bnh thng. Bng cch t bit SLEEPON EXIT trong thanh
ghi iu khin h thng, li Cortex s t ng i vo ch ng mt khi ISR
ny kt thc. iu ny cho php mt ng dng nng lng thp (trng thi h
thng lun ch sleep khi khng c s kin no xy ra) s hon ton c
iu khin bng ngt, li Cortex s c nh thc bi mt s kin (t ngt
bn trong hoc bn ngoi CPU Cortex), ch cn thc thi mt on m thch hp
v sau li i vo ch sleep, nh vy vi mt m chng trnh ti thiu
chng ta c th qun l hiu qu nng lng ca h thng.
Ngt WFE cho php li Cortex tip tc thc hin chng trnh t im m
n c t vo ch sleep. N s khng nhy n v thc thi mt trnh phc
v no. Mt s kin nh thc (wake-up) ch n gin n t mt thit b ngoi
vi d cho n khng c kch hot nh l mt ngt bn trong NVIC. iu ny
cho php mt thit b ngoi vi c th bo ng thc li Cortex v tip tc
thc thi chng trnh ng dng m khng cn mt trnh phc v ngt no. Cc
lnh WFI v WFE khng th gi trc tip t ngn ng C, tuy nhin thun li l
trnh bin dch cho tp lnh Thumb-2 cung cp sn cc macro c th c
s dng nh mt lnh C chun (inline C command):
__WFI
__WFE
Ngoi cc ch nng lng thp SLEEPNOW v SLEEPONEXIT,
li Cortex c th pht ra mt tn hiu SLEEPDEEP cho phn cn li ca h
thng vi iu khin.

Hnh 1.25. Thanh ghi iu khin h thng dng cu hnh

cc ch ng ca vi x l Cortex
iu ny cho php cc khi chc nng nh PLL (Phase Loop Lock) v
thit b ngoi vi c th ngng hot ng, STM32 c th i vo ch nng
25

lng thp nht ca n.

1.5.2 Khi h tr g li CoreSight
Tt c cc CPU ARM u trang b h thng g li ring ca n ngay trn
chip. CPU ARM7 v ARM9 CPU c ti thiu mt cng JTAG cho php mt
cng c g li chun kt ni vi CPU v ti chng trnh vo b nh RAM ni
hoc b nh Flash. Cng JTAG cng h tr iu khin ng c bn (thit lp
chy tng bc v cc breakpoint v.v) cng nh c th xem ni dung ca
cc v tr trong b nh. Ngoi ra CPU ARM7 v ARM9 cn c th cung cp
mt b theo di thi gian thc (real-time trace) thng qua mt thit b ngoi vi
g li c gi l ETM (embedded trace macro cell). Trong khi h thng g
li ny hot ng tt, th n bc l mt s hn ch. JTAG ch c th cung cp
thng tin g li cho cng c pht trin (nh Keil, IAR) khi CPU ARM dng
li, do khng c kh nng cp nht thi gian thc. Ngoi ra, s lng ca
breakpoints phn cng c gii hn ti hai im, mc d tp lnh ARM7 v
ARM9 h tr mt lnh breakpoint, c th c chn vo m chng trnh bng
cng c pht trin (gi l soft breakpoints). Tng t vi JTAG, b theo di
thi gian thc-ETM phi c trang b bi cc nh sn xut vi chi ph b sung.
Do vy ETM khng phi lc no cng c h tr. Vi li Cortex mi, ton b
h thng g li gi l CoreSight c gii thiu.
H thng g li Cortex CoreSight s dng giao din JTAG hoc SWD
(Serial Wire Debug). CoreSight cung cp chc nng chy kim sot v theo
di. N c th chy khi STM32 ang mt ch nng lng thp. y l
mt bc ci tin ln v chun g li JTAG.
H thng g li CoreSight c mt cng truy cp g li cho php kt ni
vi vi iu khin bng cng c JTAG. Cng c g li c th kt ni bng
cch s dng chun giao din JTAG 5 chn hoc giao din 2 dy ni tip.
Ngoi cc tnh nng g li ca JTAG, CoreSight c cha mt theo di d
liu v mt ETM.

26

Hnh 1.26. H thng g li CoreSight bn trong Cortex

Trong thc t, c cu g li CoreSight trn STM32 cung cp mt phin
bn thi gian thc c ci tin ca chun g li JTAG. H thng g li
STM32 CoreSight cung cp 8 breakpoints phn cng c th c t v xa
trong khi CPU Cortex ang chy. Ngoi ra b theo di Data Watch cho php
bn xem cc ni dung ca cc v tr nh trong khi CPU Cortex ang chy.
H thng CoreSight c th duy tr trng thi hot ng khi li Cortex i
vo ch ng. Ngoi ra cc timer ca STM32 c th c tm dng khi
h thng CoreSight tm dng CPU. iu ny cho php chng ta thc thi tng
bc m chng trnh v gi cho timer ng b vi h thng. Vi cc lnh
thc thi trn CPU Cortex, CoreSight ci thin ng k kh nng g li thi
gian thc ca STM32 so vi CPU ARM7 v ARM9 trc kia, trong khi vn
s dng cng mt phn cng chi ph thp.

27

Chng 2
KIN TRC H THNG CA ARM CORTEX
ARM Cortex STM32 gm nhn Cortex kt ni vi b nh FLASH
thng qua ng bus lnh chuyn bit. Cc bus d liu(Cortex Data
busses) v h thng (Cortex System busses) c kt ni ti ma trn busses
tc cao( ARM Advanced High Speed Busses- AHB). SRAM ni kt ni
vi AHB v ng vai tr l b DMA. Cc thit b ngoi vi c kt ni bng
2 h thng bus ngoi vi tc cao ( APB-ARM Advanced Peripheral Busses).
Cc bus APBs thng qua cc bus cu ni AHB-APBs kt ni vo h thng
AHB. Ma trn bus AHB s dng xung nhp ng h bng vi xung nhp ca
nhn Cortex. Tuy nhin thng qua b chia tn s AHB c th hot ng tn
s thp hn nhm tit kim nng lng.

Hnh 2.1 H thng Bus ni

Cu trc bus ni cung cp ng truyn chuyn bit dnh cho tp lnh
thc thi v ma trn bus ng d liu cho nhn Cortex v b iu khin DMA
truy cp ti nguyn trn vi x l.
2.1 Cu trc b nh
Bn cnh h thng bus ni a dng STM32 cn cung cp 4Gbytes khng
gian b nh lin tc dnh cho lp trnh. B nh c bt u t a ch
0x00000000 .On-chip SRAM bt u t a ch 0x20000000 v tt c SRAM
ni u c b tr im bt u vng bit band. Vng nh thit b ngoi vi
c nh x t a ch 0x40000000 v vng bit band. Cc thanh ghi iu
khin ca nhn Cortex c nh x t a ch 0xE0000000.
28

Hnh 2.2 Cu trc b nh

Vng nh dnh cho flash c chia nh thnh 3 vng. Vng th nht
gi l User Flash bt u t a ch 0x00000000. K tip l System Memory
hay cn gi l vng nh ln. Vng ny c ln 4Kbytes thng thng s
c nh sn xut ci t bootloader. Cui cng l vng nh nh bt u
t a ch 0x1FFFFF80 cha thng tin cu hnh dnh cho STM32.
Bootloader thng c dng ti chng trnh thng qua USART1 v
cha vng User Flash.
2.2 Ti a hiu nng
Ngoi vic h tr 2 b to xung nhp ngoi STM32 cung cp thm 2
b to xung nhp ni. Sau khi reset ng h to xung ca nhn Cortex, b to
xung nhp tc cao( High Speed Internal Oscillator) hot ng mc thp
8MHz. B to xung ni cn li l Low Speed Internal Oscillator hot ng
mc 32768KHz. B xung nhp tc thp ny thng c dng cho ng
h thi gian thc v watchdog.

29

Hnh 2.3 STM32 bao gm 2 b to xung nhp ni v 2 b to xung nhp ngoi

thm vo l b vng kha pha( Phase Lock Loop-PLL).
Nhn Cortex c th c cp xung nhp t b to dao ng ni v ngoi,
ng thi t PLL ni. Nh trn hnh 2.3, PLL c th ly dao ng t b to
dao ng tc cao ni v ngoi. C mt vn l i vi b to dao
ng ni tc cao xung nhp khng hot ng chnh xc 8MHz do khi
s dng cc thit b ngoi vi nh: giao tip serial hay s dng nh thi thi
gian thc th nn dng b to dao ng ngoi tc cao. Tuy vy, cho d s
dng b dao ng no i na th nhn Cortex lun phi s dng xung nhp to ra
t b PLL. Tt c thanh ghi iu khin PLL v cu hnh bus u c b tr
nhm RCC ( Reset and Clock Control).

2.2.1 Vng Kha Pha (Phase Lock Loop)

Sau khi h thng reset STM32 nhn xung nhp t b to dao ng
HIS. Ti thi im cc b to dao ng ngoi s b tt. Bc u tin
STM32 hot ng mc xung nhp cao nht l bt b to dao ng HSE v ch
cho n khi i vo hot ng n nh.
30

on m sau m t cch cu hnh CPU ca STM32 hot ng mc

xung nhp cao nht

B to dao ng ngoi c th c kch hot thng qua cc thanh ghi

iu khin RCC_Control. S c 1 bit trng thi c bt khi chng i vo hot
ng n nh. Mt khi b to dao ng ngoi hot ng n inh, n c th
c chn l u vo cho b PLL. Xung nhp ra c to bi PLL c xc
nh bng cch thit lp cc bi s nguyn

trong thanh ghi cu hnh

RCC_PLL. Trong trng hp xung nhp u vo ca PLL l 8MHz khi

cn cu hnh bi s nhn cho PLL l 9 to xung nhp 72MHz u ra.
Khi b to dao ng ngoi v PLL hot ng n nh, bit iu khin trng thi
s bt ln, khi dao ng c to bi PLL s c cp cho nhn CPU
Cortex ca STM32.

31

on m cu hnh STM32 s dng dao ng t PLL

2.2.2 Cu hnh cho bus

Khi PLL c chn l b to dao ng cho h thng, Cortex CPU s
hot ng mc 72MHz. cho ton b cc phn cn li ca h thng hot
ng mc ti u ngi dng cn phi cu hnh AHB v APB thng qua cc
thanh ghi cu ni.

32

2.2.3 Flash Buffer

Khi xem xt kin trc h thng ca STM32 chng ta c th thy nhn
Cortex
kt ni vi Flash thng qua ng d liu chuyn bit I-Bus. Bus d liu ny
hot ng cng tn s vi CPU, do vy nu CPU ly dao ng t PLL th bus
d liu s hot ng mc xung nhp cao nht 72Mhz. Cortex CPU s truy
cp vo Flash c mi 1.3ns. Khi mi hot ng, nhn STM32 s dng b to
dao ng ni, do thi gian truy cp Flash l khng ng k. Tuy nhin khi
PLL c kch hot v s dng to dao ng cho CPU, thi gian truy cp
vo Flash rt chm khong 35ns, iu ny lm gim hiu nng ca h thng.
Cortex CPU hot ng xung nhp cao nht 72MHz vi thi gian trng
thi ch l 0 b nh Flash c trang b b 2 nh m 64-bit. Hai b nh m
ny c th thc thi cc lnh c ghi d liu 64-bit trn Flash v chuyn cc
lnh 16 hay 32 bit cho nhn Cortex thc thi. K thut ny hot ng tt i
vi cc lnh thuc tp lnh Thumb-2 v cc tp lnh c kh nng d bo ch
dn(Branch Prediction) ca Cortex pipeline. H thng b m Flash c
qun
l bi cc thanh ghi cu hnh Flash. Cng vi vic kch hot b m tin x
l,chng ta phi iu chnh s trng thi ch khi Flash c 8 bytes lnh t b
nh Flash. tr c thit lp nh sau:
0< SYSCLK <24MHz 0 waitstate
24< SYSCLK <48MHz 1 waitstate
48<SYSCLK <72MHz 2 waitstate
Thi gian trng thi ch ny gia b m tin x l vi b nh Flash khng
tc
ng n nhn Cortex CPU. Khi CPU ang thc thi cc lnh na u ca b
33

m th cc lnh na sau ca b m s c tin x l v ti ln nhn s

l ngay tip theo, iu ny lm ti u ha hiu nng x l ca Cortex CPU.
2.2.4 Direct Memory Access
STM32 c 7 knh DMA c lp dng chuyn d liu t: b nh sang b
nh, ngoi vi ti b nh, b nh ti ngoi vi v ngoi vi ti ngoi vi. Trong
trng hp trao i d liu gia b nh v b nh, tc d liu ph thuc tc
ca knh DMA qun l n. Cn vi giao tip d liu vi ngoi vi, th tc
ph thuc vo b iu khin ca ngoi vi v hng d liu di chuyn.
Cng vi chuyn d liu theo lung, b DMA ca STM32 cn h tr b m
vng. V hu ht cc ngoi vi hin nay khng c b nh FIFO, mi b DMA
s lu d liu vo trong b nh SRAM. B DMA ca STM32 c thit k
dnh cho trun cc loi d liu tc cao v nh.

Mi thao tc b nh DMA bao gm 4 giai on.

Qu trnh truyn d liu gm 4 giai on: ly mu v phn x, tnh
ton a ch, truy cp ng truyn, v cui cng l hon tt. Mi giai on
thc hin trong 1 chu k lnh, ring truy cp ng truyn mt 5 chu k lnh.
giai on truy cp ng truyn thc cht l giai oan d liu c
truyn, mi t (word) s mt 3 chu k lnh. B DMA v CPU c thit k
cng lc c th hot ng m khng tranh chp ti nguyn ln nhau. Gia 2
knh DMA khc nhau, s c s u tin mc hot ng, da trn b phn
x s quyt nh knh DMA c mc u tin cao hn s c ly ti nguyn
trc. Nu 2 knh DMA c cng mc u tin, li ang trng thi ch
truy cp ti nguyn, th knh DMA c s th t nh hn s c s dng
ti nguyn trc.

34

B DMA c thit k cho truyn d liu tc v kch thc nh.

B DMA ch s dng bus d liu khi giai on truy cp ng truyn.
B DMA c th thc hin vic phn x ti nguyn v tnh ton a ch
trong khi b DMA khc ang giai on truy cp ng trun nh m t
hnh trn. Ngay khi b DMA th nht kt thc vic truy cp ng truyn, b
DMA 2 c th ngay lp tc s dng ng trun d liu. iu ny va lm
tng tc truyn d liu, ti a ha vic s dng ti nguyn.

giai on Bus Access CPU s c 3 chu k rnh. Khi chuyn d liu t

vng nh sang vng nh iu ny s m bo nhn Cortex-M3 s dng
60% dung lng ca ng truyn d liu cho d b DMA vn hot ng
lin tc.
Trong trng hp trao i d liu t vng nh sang vng nh mi knh
DMA ch s dng ng truyn d liu giai on Bus Access v 5 chu k
35

CPU chuyn 2 bytes d liu. Trong 1 chu k c v 1 chu k ghi, 3

chu k cn li c b tr xen k nhm gii phng ng d liu cho nhn
Cortex.
iu c ngha l b DMA ch s dng ti a 40% bng thng ca
ng d liu. Tuy nhin giai on Bus Access hi phc tp trng hp d
liu truyn gia thit b ngoi vi hoc gia ngoi vi v b nh do lin quan
n AHB v APB. Trao i trn bus AHB s dng 2 chu k xung nhp ca
AHB, trn bus APB s s dng 2 chu k xung nhp ca APB cng thm 2 chu
k xung nhp ca AHB. Mi ln trao i d liu, b DMA s s dng bus
AHB, bus APB v 1 chu k xung nhp AHB. V d chuyn d liu t bus SPI
ti SRAM chng ta s s dng:
SPI n SRAM s dung DMA = SPI transfer(APB) + SRAM
transfer(AHB) + free cycle(AHB)
= (2 APB cycles + 2 AHB cycles) + (2 AHB cycles) + (1 AHB cycle) =
(2 APB cycles) + (5 AHB cycles)
* Lu : Qu trnh trn ch p dng cho cc nhn Cortex s dng ng
I-bus np lnh cho nhn x l.

STM32 c 7 b DMA c lp vi nhau

Vic s dng DMA rt n gin. u tin l kch hot ng h xung nhp

Mt khi c cp ngun khi DMA s c iu khin bi 4 thanh ghi

in khin. 2 thanh ghi iu khin a ch ch v ngun ca ngoi vi v vng
36

nh. Kch thc d liu truyn v cu hnh tng quan DMA c lu trong 2
thanh ghi cn li.

Mi b DMA c 4 thanh ghi iu khin, 3 ngun tn hiu interrupt:

hon tt, hon tt mt na, li.
Mi knh DMA c th c gn vi mt mc u tin: rt cao, cao, trung
bnh
v thp. Kch c ca d liu c truyn c th iu chnh ph hp cho
ngoi vi v vng nh. Ngoi vic s dng DMA vi ch vng lp ch,
chng ta c th dng ngt theo di qu trnh chuyn d liu. C ba loi ngt
h tr cho DMA: hon thnh chuyn d liu, hon thnh mt na, v li. Sau
khi cu hnh hon tt, chng ta kch hot Channel Enable Bit thc hin qu
trnh chuyn d liu. V d sau m t qu trnh chuyn d liu gia 2 vng nh
trn SRAM:

on m trn, ta s dng TIM2 o thi gian (tnh theo chu k) chuyn d

liu t 2 vng nh kch thc 10 word. Vi DMA qu trnh chuyn tiu tn
37

220 chu k, vi cch s dng CPU tiu tn 536 chu k.

Hnh 3.4 Mi knh DMA c gn vi ngoi vi nht nh. Khi c kch hot,
cc thit b ngoi vi s iu khin b DMA tng ng.
Kiu truyn d liu t b nh sang b nh thng hay c dng
khi to vng nh, hay chp cc vng d liu ln. Phn ln tc v DMA hay
c s dng chuyn d

liu gia ngoi vi v vng nh. s dng

DMA, u tin ta khi to thit b ngoi vi v kch hot ch DMA trn thit
b ngoi vi , sau khi to knh DMA tng ng.

38

Chng 3
NGOI VI
Chng ny s gii thiu cc thit b ngoi vi trn cc phin bn ARM
Cortex STM32. Gm 2 loi: ngoi vi a dng v ngoi vi giao tip. Tt c
ngoi vi trn STM32 c thit k v da trn b DMA. Mi ngoi vi u c
phn iu khin m rng nhm tit kim thi gian x l ca CPU.
3.1 Ngoi vi a dng
Ngoi vi a dng trn STM32 bao gm: cc cng I/O a dng, b iu
khin ngt ngoi, b chuyn i ADC, b iu khin thi gian a dng v m
rng, ng h thi gian thc, v chn tamper.
3.1.1 Cc cng I/O a dng
STM32 c 5 cng I/O a dng vi 80 chn iu khin.

Mi chn iu khin c th cu hnh nh l GPIO hoc c chc nng

thay th khc. Hoc mi chn c th cng lc l ngun ngt ngoi.
Cc cng I/O c nh s t A->E v mc p tiu th 5V. Nhiu
chn ngoi c th c cu hnh nh l Input/Output tng tc vi cc thit b
ngoi vi ring ca ngi dng nh USART hay I2C. Thm na c th cu
hnh cc chn ny nh l ngun ngt ngoi kt hp vi cng GPIO khc.

39

Mi cng GPIO u c 2 thanh ghi 32-bit iu khin. Nh vy ta c 64bit cu hnh 16 chn ca mt cng GPIO. Nh vy mi chn ca cng GPIO
s c 4 bit iu khin: 2 bit s quy nh hng ra vo d liu: input hay
output, 2 bit cn li s quy nh c tnh d liu.

Configuration

CNF1

CNF0

Analog Input

Input Floating(Reset state)

Input Pull-up

Input Pull-down

Output Push-Pull

00:Reserved

Output Open-drain

01:10Mhz

AF Push-Pull

10:2Mhz

AF Open-drain

11:50Mhz

40

MOD1

MOD0

00

Hnh 3.1 Cu trc cng I/O

Sau khi cng c cu hnh, ta c th bo v cc thng s cu hnh bng
cch kch hot thanh ghi bo v. Trong thanh ghi ny, mi chn trong cng
u c mt bit bo v tng ng trnh cc thay i v cc 4 bit cu
hnh. kch hot ch bo v, ta ghi ln lt gi tr 1,0,1 vo bit 16:

Sau c li bit 16 lin tc 2 ln, nu gi tr tr v ln lt l 0 v 1 th

thit lp kha hon thnh

d dng c v ghi d liu trn cng GPIO, STM32 cung cp 2 thanh

ghi Input v Output data. K thut bit banding c h tr nhm thc hin
cc thao tc bit trn thanh ghi d liu. Thanh ghi 32-bit Set/Reset, vi 16 bit
cao nh x ti mi chn ca cng iu khin reset khi c thit lp gi tr
1. Tng t vy 16 bit thp iu khin Set khi c gn gi tr 1.
3.1.1.1 Chc nng thay th (Alternate Function)
Chc nng thay th cho php ngi dng s dng cc cng GPIO vi
41

cc ngoi vi khc. thun tin cho thit k phn cng, mt thit b ngoi vi
c th c nh x ti mt hay nhiu chn ca vi x l STM32.

S dng cc tnh nng thay th ca STM32 c iu khin bi cc thanh

ghi Remap & Debug I/O. Mi thit b ngoi vi( USART, CAN, Timers, I2C
v SPI) c 1 hoc 2 trng bit iu khin nh x ti cc chn ca vi iu
khin. Mt khi cc chn c cu hnh s dng chc nng thay th, cc
thanh ghi iu khin GPIO s c s dng iu khin cc chc nng thay
th thay v tc v I/O. Cc thanh ghi Remap cn iu khin b JTAG. Khi h
thng khi ng, cng JTAG c kch hot tuy nhin chc nng theo di
d liu(data trace) vn cha khi ng. JTAG khi c th chuyn sang
ch debug, xut d liu theo di ra ngoi, hoc n gin ch s dng nh
cng GPIO.
3.1.1.2 Event Out
Nhn Cortex c kh nng to xung nhp nh thc cc khi vi iu
khin bn ngoi thot khi trng thi tit kim nng lng. Thng thng, xung
nhp ny s c ni vi chn Wake up ca vi x l STM32 khc. Lnh
SEV Thumb-2 khi c thc thi s to ra xung nhp Wake up ny. Thanh ghi
iu khin s kin ca STM32 cu hnh chn GPI no s xut xung nhp
Wake up.
3.1.2. Ngt ngoi (EXTI)
B iu khin ngt ngoi c 19 ngt v kt ni vo bng vector ngt thng
qua b NVIC. 16 ngt c kt ni thng qua cc chn ca cng GPIO v to
ngt khi pht khi c xung ln(rasing) hoc xung (falling) hoc c hai. 3 ngt
cn li c ni vi RTC alarm, USB wake up v Power voltage
detect.
NVIC cung cp bng vector ngt ring bit dnh cho cc ngt t 0-4,
42

ngt RTC, ngt Power detect v ngt USB wake up. Cc ngt ngoi cn li chia
lm 2 nhm 5-10, v 11-15 c cung cp thm 2 bng ngt b sung. Cc
ngt ngoi rt quan trng trong qun l tiu th nng lng ca STM32.
Chng c th c s dng nh thc nhn vi x l t ch STOP khi
c 2 ngun to xung nhp chnh ngng hot ng. EXTI c th to ra cc ngt
thot ra khi s kin Wait ca ch Interrupt v thot khi s kin Wait
ca ch Event.

Hnh 3.2 Ngt ngoi

16 ngt ngoi c th c nh x ti bt k chn no ca vi x l thng
qua 4 thanh ghi cu hnh iu khin. Mi ngt c iu khin bi trng 4 bit.
3.1.3 ADC
STM32 c th c 2 b chuyn i tn hiu tng t sang tn hiu s ty vo
cc phin bn.

43

Hnh 3.3 Mch ADC trong STM32

B ADC c th c cung cp ngun ring t 2.4V n 3.6V.
Ngun cung cp cho b ADC c th c kt ni trc tip hoc thng qua cc
chn chuyn bit. B ADC c phn gii 12-bit v tn sut ly mu l
12Mhz. Vi 18 b ghp knh, trong 16 knh dnh cho cc tn hiu ngoi, 2
knh cn li dnh cho cm bin nhit v vn k ni.
3.1.3.1 Thi gian chuyn i v nhm chuyn i
B ADC cho php ngi dng c th cu hnh thi gian chuyn i ring
bit cho tng knh. C 8 mc thi gian chuyn i ring bit t 1.5 n 239.5
chu k.

Hnh 3.4 C 8 mc thi gian chuyn i

44

Mi b ADC c 2 ch chuyn i: thng thng(regular) v injected.

ch regular cho php mt hay mt nhm cc knh kt hp vi nhau thc thi
tc v chuyn i. Mt nhm knh ti a c th gm 16 knh. Th t chuyn
i trong nhm c th c cu hnh bi phn mm, v trong mt chu k
chuyn i ca nhm, mt knh c th c s dng nhiu ln. Chuyn i
regular c th c kch hot bng s kin phn cng ca Timer hay ngt
ngoi EXTI 1. Mt khi c kch hot, ch Regular c thc thi chuyn
i lin tc( continuos convertion) hoc khng lin tc.

Mt nhm knh hot ng ch Regular c th lin tc thc hin

qu trnh chuyn i, hoc ch chuyn i khi nhn tn hiu kch hot.
Khi mt nhm cc knh hon thnh vic chuyn i, kt qu c lu vo
thanh ghi kt qu v tn hiu ngt c to. V b ADC c phn gii l 12
bit v c lu trong thanh ghi 16 bit do d liu c th c canh l tri
hoc phi.

D liu c th c canh l tri hoc phi trong thanh ghi kt qu

B ADC1 c ring knh DMA chuyn d liu t thanh ghi kt qu sang
vng nh. Vi phng php ny, d liu t kt qu chuyn i ca mt nhm
cc knh ADC s c chuyn ton b ln vng nh ngay trc khi ngt c
pht sinh.

45

ADC1 s dng DMA chuyn d liu kt qu ca mt nhm

cc knh vo vng nh c khi to trn SRAM
Loi ADC th 2 l Injected ADC. Injected ADC l dy cc knh ADC, ti a
l 4 knh. Injected ADC c th c kch hot bng phn mm hoc tn hiu
phn cng. Khi c kch hot, Injected ADC vi mc u tin cao hn s tm
ngng cc knh Regular ADC ang hot ng. Cc knh Regular ADC ch tip
tc hot ng sau khi Injected ADC thc thi xong. V cu hnh hot ng ca
Injected tng t nh ca Regular, tuy nhin mi knh chuyn i ca Injected
c thanh ghi d liu ADC_JDRx tng ng.

Tng t nh Regular ADC, d liu thanh ghi ADC_JDRx c th c

canh l tri hoc phi, km theo l du nu d liu m
3.1.3.2 Analogue WatchDog
Ngoi 2 ch Regular v Injected, khi ADC cn c b sung
thm Analogue WatchDog. Khi ny h tr pht hin d liu tng t nm
ngoi vng hot ng bnh thng ca mt knh ADC cho trc. Khi c cu
hnh ngng trn v ngng di, nu tn hiu tng t u vo nm ngoi
vng trn, th ngt s c pht sinh. Ngoi vic gim st tn hiu in p
thng thng, Analogue Watchdog c th c dng pht hin in p
khc 0 V.
46

Hnh 3.5 Analogue Watchdog c th dng gim st mt hay nhiu knh ADC
vi vng ngng c cu hnh bi ngi dng
3.1.3.3 Cu hnh ADC

Cc thanh ghi ca khi ADC c tch ra thnh 6 nhm thanh ghi, trong
cc thanh ghi Status v Control xc nh ch hot ng ca ADC.
C hai thanh ghi iu khin ADC_CR1 v ADC_CR2 cu hnh hot ng
ca khi ADC.

47

 hm x l ngt ADC

Hoc chng ta c th s dng DMA thay v ngt

Chng ta kch hot ch DMA ca khi ADC

3.1.3.4. Dual mode

mt s phin bn, ST cung cp 2 khi ADC nhm p ng cc tc v
phc tp hn

Hnh 3.6 Phin bn c 2 khi ADC

48

Khi hot ng ch Dual, khi ADC2 ng vai tr ph i vi ADC1.

Khi kt hp ADC1 v ADC2, chng ta s c 8 ch hot ng
3.1.4.1. C hai khi ADC cng hot ng cng ch Regular hoc
Injected

Khi hot ng ch ny, cng lc khi ADC1 v ADC2 s chuyn

i d liu t 2 knh khc nhau. V d trong cc ng dng cn theo di cng
lc in p v cng dng.
3.1.4.2. C hai khi cng hot ng 2 ch Regular v Injected xen k

Nh hnh trn m t, c hai khi ADC hot ng cng mt ch ti

cng
thi im. Khi ch Injected c kch hot, c khi ADC1 v ADC2 tm
thi ri trng thi Regular thc thi chuyn i cc knh trong ch
Injected.

49

3.1.4.3. Hot ng xen k nhanh v chm Regular

ch xen k nhanh, mt knh c th lin tc chuyn i bi hai khi

ADC,
thi gian nh nht kch hot ln chuyn i k tip l 7 chu k xung nhp
ca ADC. ch xen k chm khong cch thi gian ti thiu l 14 chu k
xung nhp. Hai ch kt hp ny lm tng hiu sut chuyn i ca khi
ADC.
3.1.4.4. Ch kch hot thay th

Ban u phn cng s kch hot knh u tin trong nhm chuyn i
Injected ca khi ADC1, sau s kch hot tip nhm Injected ca ADC2. C
nh vy lin tc v xen k.
3.1.4.5. Kt hp ng b ha Regular v kch hot thay th

50

Nh ta thy trn, vic chuyn i ch Regular c c hai khi

ADC1 v ADC2 thc thi ng thi, ng b. Khi c kch hot bi hardware,
nhm Injected ca khi ADC1 c thc thi, ch Regular tm thi ngng v
hot ng tr li khi tc v thuc nhm Injected hon tt.
3.1.4.6. Kt hp ng b ha Injected v xen k Regular

Hai khi ADC1 v ADC2 hot ng ch Regular xen k nhau th

c kch hot chuyn sang hot ng ch ng b Injected. Lu l:
khi ch xen k Regular, c hai knh ADC1 v ADC2 c th chuyn i
chung trn cng mt knh, tuy nhin khi sang ch ng b Injected, th knh
c s dng ca ADC1 v ADC2 phi khc nhau.
3.1.5. B nh thi a nhim v nng cao
STM32 c bn khi nh thi. Timer1 l khi nng cao dnh cho iu
khin
ng c. 3 khi cn li m nhim chc nng a nhim. Tt c chng u c
chung kin trc, khi nng cao s c thm cc c tnh phn cng ring bit.
3.1.4.4. B nh thi a nhim
Tt c cc khi nh thi u gm b m 16-bit vi thanh ghi chia tn
s dao ng 16-bit(prescaler) v thanh ghi t np(auto-reload). B m ca
khi nh thi c th c cu hnh m ln, m xung hay trung tnh(ln
xung xen k nhau). Xung nhp cho ng h c th c la chn da trn 8
ngun khc nhau: t ng h chuyn bit c ly t ng h h thng, t xung
nhp chn ra ly t khi nh thi khc, hoc t ngun xung nhp ngoi. Khi
nh thi s dng cng chn ly xung nhp u vo thch hp, ngi dng
c th s dng chn ETR iu khin cng chn ny.

51

Hnh 3.7 4 khi nh thi vi cc thanh ghi 16-bit Prescaler,

16-bit Counter v Auto-reload. Xung nhp hot ng c th
ly t ng h h thng, tn hiu ngoi v cc khi nh thi khc
Mi khi nh thi c cung cp thm 4 knh Capture/Compare. Mi
khi nh thi cn c h tr ngt v DMA.
3.2.1. Khi Capture/Compare
Mi knh Capture/Compare c iu khin bi duy nht mt thanh ghi.
Chc nng ca thanh ghi ny c th thay i ty thuc cu hnh. ch
Capture, thanh ghi ny c nhm cc bit m nhn thit lp lc d liu u vo
v ch nh gi cc ng PWM. ch Compare, STM32 cung cp hm
chun so snh v b to xung PWM.

52

Mi mt knh Capture/Compare u c mt thanh ghi n cu hnh ch

hot ng. Bit Capture Compare Selection dng chn ch .
3.2.2 Khi Capture
Mt khi Capture c bn gm c bn knh vo cu hnh b pht
hin xung(Edge Detector). Khi mt xung ln(rising edge) hay xung cnh
xung( falling edge) c pht hin, b m hin thi ca s c cp nht
vo cc thanh ghi 16-bit Capture/Compare. Khi s kin capture xy ra b m
c th c khi ng li hoc tm ngng. Mt ngt DMA c th c s
dng trng hp ny.

53

Hnh 3.8 4 knh vo ca khi Capture c cc b lc d liu v pht hin

xung cnh ring. Khi s kin capture c n c th c dng
kch hot mt s kin DMA khc.
3.2.3 Ch PWM Input
Khi Capture c th c cu hnh dng 2 ng Capture u vo o tn
hiu PWM ngoi.

Hnh 3.9 Ch PWM Input

54

 ch o tn hiu PWM, 2 knh Capture c dng o chu k

Period v Duty ca sng PWM.

ch PWM s dng 2 knh Capture. thi im bt u chu k

PWM, b m c thit lp gi tr 0 v bt u m ln khi pht hin ra cc
tn hiu cnh ln(rising edge). Khi tn hiu cnh xung c pht hin(falling
edge) gi tr b m gi tr ca chu k Duty c tng thm.
3.2.4 Ch PWM
Mi khi Timer u c kh nng to cc xung nhp PWM. ch to
xung PWM, gi tr Period c lu trong thanh ghi Auto Reload. Trong khi
gi tr Duty c lu thanh ghi Capture/Compare. C hai kiu to xung
PWM, mt l canh l(edge-aligned) v canh l gia(centre-aligned). Vi edgealigned cnh xung ca tn hiu trng vi thi im thanh ghi reload cp nht
li gi tr. Vi

centre-aligned thi im thanh ghi reload cp nht li l

khong gia ca chu k Duty.

Mi khi Timer u c kh nng to ra cc xung PWM vi lch chu k

c th c cuhnh edge-aligned hoc centre-aligned tnh theo thi im
cp nht gi tr ca thanh ghi Reload.

55

3.2.5 Ch One Pulse

cc ch trnh by trn, ta thy xung nhp PWM c to c
dng dy cc tn hiu lin tip nhau. Khi Timer cn cung cp mt ch
hot ng ring cho php to duy nht mt xung PWM vi tn s, b rng
xung cng vi thi gian tr c kh nng c cu hnh mt cch linh ng.

3.3 ng b ho cc b nh thi
Mc d cc b nh thi hot ng hon ton c lp vi nhau, tuy
nhin chng c th c ng b ha tng i mt hay ton b.

56

Hnh 3.10 Mi khi Timer c u vo l cc xung s kin

t cc khi Timers khc.
Mi khi Timer 3 ng vo h tr cc xung s kin t 3 khi Timers
cn li. Ngoi ra chn Capture t Timer1 v Timer2(TIFP1 v TIFP2) cng
c a khi iu khin s kin ca mi Timer.

Hnh 3.11 Cu hnh cc khi Timer kt hp li to thnh mng cc Timer

57

 m hnh to thnh mt mng Timer, mt Timer ng vai tr

Master, cc Timer cn li ng vai tr l Slave.
3.4 RTC v cc thanh ghi Backup
STM32 bao gm 2 khi ngun chnh: ngun dnh cho nhn CPU, cc
thit b ngoi vi v ngun dnh cho khi d phng. Cng c thit k chung
vi khi d phng l 10 thanh ghi 16-bit, ng h thi gian thc RTC v
mt khi Watchdog c lp. Cc thanh ghi d phng n gin ch l 10 vng
nh lu cc gi tr d liu quan trng khi h thng i vo ch Standby
v ngun chnh ca h thng b ngt. ch tit kim nng lng, ng h
RTC v Watchdog c th c dng kch hot h thng hot ng tr li.
STM32 c mt ng h thi gian thc vi thanh ghi m 32-bit v gi tr tng
ln mt sau mi giy nu xung nhp u vo ca n l 32.768KHz. Khi cu
hnh xung nhp hot ng h thng, xung nhp ngun cho ng h RTC ny
c th c ly t 3 ngun: LSI, LSE, HSE vi gi tr chia l 128. B m
RTC c th to c 3 s kin: tng gi tr m, b m trn v ngt bo ng.
Ngt bo ng khi gi tr b m trng vi gi tr c cu hnh trong thanh
ghi Alarm.

58

Hnh 3.12 Khi RTC c th ly ngun xung nhp t LSI, LSE v HSE.
RTC c t trong khi d phng vi ngun cung Vbat v tn hiu
ngt Alarm c kt ni vi chn nhn xung EXTI17. iu c ngha khi
h thng vo trng thi hot ng ca mc nng lng thp, RTC vn hot
ng. V thng qua s kin Alarm, ton b h thng c th c kch hot
hot ng tr li ch bnh thng.
3.5 Kt ni vi cc giao tip khc
STM32 h tr 5 loi giao tip ngoi vi khc nhau. STM32 c giao din
SPI v I2C giao tip vi cc mch tch hp khc. H tr giao tip CAN
cho cc module, USB cho giao tip PC v giao tip USART.
3.5.1 SPI
H tr giao tip tc cao vi cc mch tch hp khc, STM cung cp 2
khi iu khin SPI c kh nng chy ch song cng(Full duplex) vi
tc truyn d liu ln ti 18MHz. Khi SPI tc cao nm trn APB2,
khi SPI tc thp nm trn APB1.Mi khi SPI c h thng thanh ghi cu
hnh c lp, d liu truyn c th di dng 8-bit hoc 16-bit, th t h tr
59

MSB hay LSB. Chng ta c th cu hnh mi khi SPI ng vai tr master

hay slave.

Hnh 3.13 Khi SPI

h tr truyn d liu tc cao, mi khi SPI c 2 knh DMA dnh
cho gi v nhn d liu. Thm vo l khi CRC dnh cho c truyn v nhn
d liu. Khi CRC u c th h tr kim tra CRC8 v CRC16. Cc c tnh
ny rt cn thit khi s dng SPI giao tip vi MMC/SD card.

Hnh 3.14 S dng SPI giao tip vi MMC/SD card.

3.5.2 I2C
Tng t nh SPI, chun I2C cng c STM32 h tr nhm giao tip
vi cc mch tch hp ngoi. Giao din I2C c th c cu hnh hot ng
60

ch slave, master hay ng vai tr b phn x ng trong h thng multimaster. Giao din I2C h tr tc truyn chun 100kHz hay tc cao
400kHz. Ngoi ra cn h tr 7 hoc 10 bit a ch. c thit k nhm n gin
ha qu trnh trao i vi 2 knh DMA cho truyn v nhn d liu. Hai ngt
mt cho nhn Cortex, mt cho nh a ch v truyn nhn

Hnh 3.15 Khi I2C

Thm na m bo tnh chnh xc d liu truyn, khi kim tra li d
liu( PAC - packet error checking) c tch hp thm vo giao din I2C cho
php kim tra m CRC-8 bit. Thao tc ny c thc hin hon ton t ng
bi phn cng.

3.5.3 USART
Mc d cc giao din trao i d liu dng ni tip dn dn khng cn
c h tr trn my tnh, chng vn cn c s dng rt nhiu trong lnh vc
nhng bi s tin ch v tnh n gin. STM32 c n 3 khi USART, mi
khi c kh nng hot ng n tc 4.5Mbps. Mt khi USART nm trn
APB1 vi xung nhp hot ng 72MHz, cc khi cn li nm trn APB2
hot ng xung nhp 36MHz.

61

Hnh 3.16 Giao din USART c kh nng h tr giao tip

khng ng b UARTS, modem cng nh giao tip hng ngoi v Smartcard.
Vi mch tch hp cho php chia nh tc BAUD chun thnh nhiu
tc khc nhau thch hp vi nhiu kiu trao i d liu khc nhau. Mi
khi USART c hai knh DMA dnh cho truyn v nhn d liu. Khi h
tr giao tip dng UART, USART cung cp nhiu ch giao tip. C th
trao i d liu theo kiu ch hafl-duplex trn ng truyn Tx. Khi h tr
giao tip modem v giao tip c s dng iu khin lung (hardware flow
control) USART cung cp thm cc tn hiu iu khin CTS v RTS.

Hnh 3.17 H tr giao tip ch hafl-duplex da trn mt ng truyn

Ngoi ra USART cn c th dng to cc giao tip ni (local
interconnect bus). y l m hnh cho php nhiu vi x l trao i d
liu ln nhau. USART cn c khi encoder/decoder dng cho giao tip hng
ngoi vi tc h tr c th t n 1115200bps, hot ng ch haflduplex NRZ khi xung nhp hot ng khong t 1.4MHz cho n 2.12Mhz.
thc hin giao tip vi smartcard, USART cn h tr chun ISO 7618-3.
62

Hnh 3.18 Giao tip smartcard v hng ngoi

Ngi dng c th cu hnh khi USART cho cc giao tip ng b tc
cao da trn 3 ng tn hiu ring bit nh SPI. Khi hot ng ch
ny, khi USART s ng vai tr l SPI master v c kh nng cu
hnh Clock Polarity/Phase nn hon ton c th giao tip vi cc SPI slave
khc.

Hnh 3.19 H tr giao tip ng b SPI

3.5.4 CAN
Khi iu khin CAN cung cp mt im giao tip CAN y h tr
chun CAB 2.0A v 2.0B Active v Passive vi tc truyn d liu 1 Mbit/s.
Ngoi ra khi CAN cn c khi m rng h tr giao tip truyn d liu
dng deterministic da trn th thi gian Time-trigger CAN(TTCAN).

63

Hnh 3.20 Khi iu khin CAN

Tn y ca CAN l bxCAN, trong bx l vit tt ca Base
eXtended. Mt giao din c bn CAN ti thiu phi h tr b m n truyn
v nhn d liu, trong khi cc giao din m rng cung cp nhiu b m.
bxCan l s kt hp gia hai kin trc trn. bxCan c 3 b m d liu cho
truyn v 2 b m nhn, cc b m ny thng c gi l mailbox(hp th).
Mi mailbox c t chc nh mt FIFO hng i
Mt im quan trng na ca CAN l lc gi tin nhn(receive message
filter). V giao thc CAN truyn d liu da trn a ch ch nhn, do gi
tin s c pht trn ton b mng, ch c im no c a ch ging nh
a ch nhn trn gi tin s dng gi tin . Lc gi tin gip cc im trn
mng CAN trnh x l cc gi tin khng phi ca mnh. STM32 cung cp 14
b lc(14 filters bank) c nh s t 0-13 cho php lc ton b cc gi tin
khng cn thit. Mi b lc gm 2 thanh ghi 32-bit CAN_FxR0 v
CAN_FxR1.

Hnh 3.21 Khi CAN c 3 mailbox cho truyn d liu vi nh nhn

thi gian t ng cho chun TTCAN

64

Mi b lc c th c cu hnh hot ng 4 ch lc c a
vo 2 nhm chnh l lc theo ID hoc theo nhm ID. Ch th nht l lc
da trn ID ca gi tin, nu cc gi tin no khng c ID ging hoc khng
ging nh ID c cu hnh trong b lc, n s b b qua. Ch th hai cho
php nhn gi tin trong cng mt nhm. Thanh ghi th nht cha ID ca gi tin,
thanh ghi th hai cha mt n,quy nh cc thnh phn trn vng ID ca
thanh ghi th nht m b lc da trn so snh lc hay khng lc gi tin.

CAN hot ng hai ch : bnh thng truyn nhn d liu v

ch khi to cu hnh thng s mng. Thm vo khi CAN c th s
dng ch tit kim nng lng Sleep Mode. Khi ch Sleep Mode,
ng h xung nhp cp cho CAN ngng hot ng, tuy nhin thanh ghi
mailbox vn hot ng. iu ny cho php CAN c kch hot da trn
cc hot ng mng. C hai ch ph khi CAN hot ng ch truyn
nhn d liu thng thng. Ch Silent, khi CAN ch nhn d liu khng
th truyn d liu, ngi ta hay s dng ch ny theo di mng v cc
gi tin truyn trong mng. Ch Loopback cho php ton b cc gi tin
chuyn c a vo ngay chnh b m nhn ca khi CAN . Ch ny
dng t kim tra hot ng ca phn cng CAN v phn mm iu khin.
3.5.5 USB
H tr giao tip Device USB vi tc Full Speed (12Mbps) c kh
nng kt ni vi mt giao din host usb. Khi giao din ny bao gm Layer1
v Layer2 m nhn chc nng truyn vt l(phisical layer) v truyn d liu
logic (data layer). Ngoi ra cn h tr y ch Suspend v Resume
nhm tit kim nng lng.
65

Vi 8 endpoint, c th hot ng di cc ch : Control, Interrupt,

Bulk hoc Isochronous. Vng m d liu 512 byte SRAM ca cc endpoint
c chia s vi giao din CAN. Khi c cu hnh, ng dng s chia vng m
ny thnh cc phn tng ng vi cc endpoint. Cc vng m ny m bo
d liu c truyn nhn lin tc trn mi endpoint.

66

Chng 4
LP TRNH IU KHIN NG C BC
S DNG ARM-STM32F103
4.1 Gii thiu Kit STM32 STM32F103
c tnh ca Kit:
1. MCU: STM32F103 ARM 32 bit CORTEX M3 with 384K
2. Program Flash, 64K Bytes RAM, USB, CAN, x2 I2C, x16 ADC, x2 DAC
3. x5 UART, x2 SPI, x12 TIMERS, up to 72Mhz operation
4. JTAG connector tiu chuan vi ARM 2x10 pin dnh cho viec lap trnh v
gh ri
5. USB connector
6. SD-MMC card, Audio, Microphone
7. user buttions x3
8. user leds x3
9. RS-232 connector
10. RESET button
11. status LED
12. 8 Mhz crystal oscillator
13. 32768 Hz crystal and RTC backup battery
14. extension headers for all uC ports
c tnh STM32F103RDT6:
- CPU clock up to 72Mhz
- FLASH 384KB
- RAM 64KB
- DMA x12 channels
- RTC
- WDT
- Timers x11+1
- SPI x2
- I2C x2
67

- USART x5
- USB x1
- CAN x1 (multiplexed with USB so both can't be used in same time)
- GPIO up to 51 (multiplexed with peripherials)
- 16 knh ADC 12-bit, DAC x2
- operating voltage 2.0-3.6V
- temperature -40C +85C
4.1.1 Mch CPU

Hnh 4.1Mch CPU

- Thch anh 8 MHz chn 8-9 to xung ng h cho cc hot ng ca h
thng.
- Thch anh 32.768 KHz chn 3-4 to xung dng cho ng h thi gian
thc v watchdog.

68

4.1.2 Mch giao tip RS232 qua USART1

Hnh 4.2 Giao tip RS232

4.1.3 Mch cp ngun v USB

Hnh 4.3 Mch cp ngun v USB

69

4.1.4 Mch giao tip vi LCD, np v g ni chng trnh qua JTAG, cc

mch giao tip CAN/ PS2

Hnh 4.4 Giao tip LCD, JTAG, PS2, CAN

4.1.5 Mch th nh SD/MMC qua giao tip SPI

Hnh 4.5 Giao tip vi th nh SD/MMC

4.2 iu khin ng c bc vi Kit STM32 STM32F103
4.2.1.Thit k mch Motor Driver:
- S dng Step Motor n cc- 6 dy c gc bc 1,80/ ngun cp 12V.
- Vi loi motor ny c th m dng bng IC- ULN 2003.
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- Mch Motor Driver ghp ni vi Kit qua cng PB (chn PB.12, PB.13,
PB.14, PB.15)
S Motor Driver nh hnh 4.6:

Hnh 4.6. Mch Motor Driver

4.2.2. Chng trnh iu khin Step Motor:
Chng trnh c vit trn Keil v4.2, s dng b th vin chun CMSIS
ca dng ARM Cortex-M3
#include "main.h"
GPIO_InitTypeDef GPIO_InitStructure;
/**
* @brief Configures the different system clocks.
* @param None
* @retval None
*/
void RCC_Configuration(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
}
/**
* @brief Inserts a delay time with resolution is 10 milisecond..
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* @param nCount: specifies the delay time length.

* @retval None
*/
void delay_ms(__IO uint32_t num)
{
__IO uint32_t index = 0;
/* xung dong ho he thong mac dinh la 72MHz */
for(index = (720000 * num); index != 0; index--)
{
}
}
/**
* @brief Main program.
* @param None
* @retval None
*/
int main(void)
{
/* cau hinh dong ho he thong */
RCC_Configuration();
/* cau hinh cac chan xuat */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15 | GPIO_Pin_14 |
GPIO_Pin_13 |
GPIO_Pin_12;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
while (1)
{
GPIO_Write(GPIOB,0xC000);
72

delay_ms(3);
GPIO_Write(GPIOB,0x6000);
delay_ms(3);
GPIO_Write(GPIOB,0x3000);
delay_ms(3);
GPIO_Write(GPIOB,0x9000);
delay_ms(3);
}
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t* file, uint32_t line)
{
/* User can add his own implementation to report the file name and line
number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */

/* vong lap vo han */

while (1)
{
}
}
#endif

73

Kt Lun
Nghin cu ny ban u cho thy c kt qu kh quan, to tin
cho pht trin cc ng dng vi ARM Cortex M3. pht trin ti ny, ti
xin a ra mt s u nhc im nh sau:
u, nhc im:
u im:
Gi thnh chip r so vi cc dng chip khc vi cng s ti nguyn nh
ARM.
Tc x l cao, n nh.
Tit kim nng lng
S lng ti nguyn ln, ph hp vi nhiu ng dng khc nhau
Nhc im
Nhiu thanh ghi, cu lnh kh di, gy kh nh cho ngi dng, d
nhm ln.
Th trng ARM Vit Nam cha rng, gy kh trong vic tm kim
ti liu v kh khn trong vic t mua chip, do vy vic nghin cu cha
c su.
Hng pht trin:
t mua KIT to iu kin nghin cu thc t trn module.
To cc module thc t to iu kin thun li cho sinh vin nghin
cu thc hnh vi cc ng dng thc t, d hnh dung.

74

Ti liu tham kho:

1/ ARM7TDMI (Rev 3)Technical Reference Manual. Copyright 19942001. All rights reserved. ARM DDI 0029G
2/ The Defi nitive Guide to the ARM Cortex-M3.
http://www.arm.com/

75