Mo Rong Port

Vi iu khin 8051
Mt s bi tp giao din vi ngoi vi
Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.
M rng port xut vi cc mch cht

U1
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
U2
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
X2
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
CS-01
11
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D0
D1
D2
D3
D4
D5
D6
D7
XUAT
RA
NGOAI
VI
2
3
4
5
6
7
8
9
CS-02
C
OC
11
1
74LS573
0
A13
A14
A15
/WR
D1
D2
D3
D4
D5
D6
D7
D8
U3
19
18
17
16
15
14
13
12
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
C
OC
74LS573
U5A
U4
A13 1
A14 2
A15 3
VCC
6
5
4
8031
CS-01
1
A
B
C
G1
G2B
G2A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
3
/WR
7402
U5B
CS-02
4
5
6
74LS138
0
7402
XUAT
RA
NGOAI
VI
M rng port xut vi cc mch cht

on chng trnh sau y s xut ni dung
ca nh 30H RAM bn trong ra ngoi vi
ghp vi U2 v xut ni dung ca nh 31H
RAM bn trong ra ngoi vi ghp vi U3.
MOV A, 30H
MOV DPTR, #0C000H
MOVX @DPTR, A
MOV A, 31H
MOV DPTR, #0E000H
MOVX @DPTR, A
Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051 .
M rng port nhp

Nhp t ngoi vi
U1
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
U2
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
X2
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
CS-I1
19
1
B1
B2
B3
B4
B5
B6
B7
B8
D0
D1
D2
D3
D4
D5
D6
D7
XUAT
RA
NGOAI
VI
A13
A14
A15
2
3
4
5
6
7
8
9
CS-I2
C
DIR
74LS245
/WR
A1
A2
A3
A4
A5
A6
A7
A8
U3
18
17
16
15
14
13
12
11
19
1
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
C
DIR
74LS245
U5A
U4
A13 1
A14 2
A15 3
VCC
6
5
4
8031
CS-I1
3
A
B
C
G1
G2B
G2A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
2
/RD
7432
U5B
CS-I2
6
4
5
74LS138
7432
XUAT
RA
NGOAI
VI
M rng port nhp

on chng trnh sau y s nhp d liu t
ngoi vi ghp vi U2 ri ct vo nh 40H
RAM bn trong v nhp d liu t ngoi vi ghp
vi U3 ri ct vo nh 41H RAM bn trong.
MOV DPTR, #8000H
MOVX A, @DPTR
MOV 40H, A
MOV DPTR, #0A000H
MOVX A, @DPTR
MOV 41H, A
M rng port vi PPI 8255

Byte thp ca bus a ch
DATA BUS
U1
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
U2
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
X2
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
ALE
11
1
A13
A14
A15
ALE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
C
OC
XUAT
RA
NGOAI
VI
D0
D1
D2
D3
D4
D5
D6
D7
34
33
32
31
30
29
28
27
/RD
/WR
A0
A1
74LS573
/RD
/WR
D1
D2
D3
D4
D5
D6
D7
D8
U3
19
18
17
16
15
14
13
12
U4
A13 1
A14 2
A15 3
VCC
6
5
4
8031
A
B
C
G1
G2B
G2A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
5
36
9
8
35
6
D0
D1
D2
D3
D4
D5
D6
D7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RD
WR
A0
A1
RESET
CS
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
0
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
74LS138
0
8255
4
3
2
1
40
39
38
37
18
19
20
21
22
23
24
25
14
15
16
17
13
12
11
10

Port A: a ch l 6000H.
Port B: a ch l 6001H.
Port C: a ch l 6002H.
Thanh ghi iu khin: a ch l 6003H.
8255A c 3 ch hot ng: ch 0, ch 1 v ch
2. PPI ny hot ng nhp/xut, trc tin ta phi
khi ng chn ch v xc nh vic nhp/xut
cho cc port ca 8255A. an chng trnh sau y s
khi ng 8255A theo yu cu sau:
Port A xut ch 1.
Port B nhp ch 0.
MOV DPTR, #6003H
MOV A, #10100010B
MOV @DPTR, A

an chng trnh sau y s nhp d liu t ngoi vi
qua port A, ghi kt qu vo nh 30H ca RAM bn
trong. Ly ni dung nh 31H ca RAM bn trong xut
ra ngoi vi qua port B v port C. Cc port A, B, C hot
ng ch 0.
MOV DPTR, #6003H
MOV A, #10010000B
MOVX @DPTR, A
MOV DPTR, #6000H
MOVX A, @DPTR
MOV 30H, A
MOV A, 31H
MOV DPTR, #6001H
MOVX @DPTR, A
MOV DPTR, #6002H
MOVX @DPTR, A

DATA BUS
U1
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
U2
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
X2
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
39
38
37
36
35
34
33
32
D0
D1
D2
D3
D4
D5
D6
D7
21
22
23
24
25
26
27
28
A8
A9
17
16
29
30
11
10
/RD
/WR
D0
D1
D2
D3
D4
D5
D6
D7
34
33
32
31
30
29
28
27
/RD
/WR
A8
A9
A13
A14
A15
5
36
9
8
35
6
D0
D1
D2
D3
D4
D5
D6
D7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RD
WR
A0
A1
RESET
CS
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
ALE
8031
8255
U4
A13 1
A14 2
A15 3
VCC
A
B
C
6
5
4
G1
G2B
G2A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
15
14
13
12
11
10
9
7
4
3
2
1
40
39
38
37
18
19
20
21
22
23
24
25
14
15
16
17
13
12
11
10

a ch port A: 6000H.
a ch port B: 6100H.
a ch port C: 6200H.
a ch ca thanh ghi iu khin : 6300H.
Hin th s
VCC
VCC
VCC
VCC
U1
C
OC
11
1
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
11
1
74LS138
U7A
/CS4 2
/WR
U8A
CS-01
1
/CS5 2
/WR
3
7402
U9A
CS-01
1
/CS6 2
/WR
3
7402
U10A
CS-01
1
/CS7 2
/WR
3
7402
CS-01
1
3
7402
74LS573
330 . 8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
U6
D1
D2
D3
D4
D5
D6
D7
D8
C
OC
74LS573
19
18
17
16
15
14
13
12
330 . 8
19
18
17
16
15
14
13
12
U5
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
A B C D E F G
7 6 4 2 1 9 10
D1
D2
D3
D4
D5
D6
D7
D8
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
74LS573
C
OC
C
OC
/CS0
/CS1
/CS2
/CS3
/CS4
/CS5
/CS6
/CS7
2
3
4
5
6
7
8
9
15
14
13
12
11
10
9
7
U4
11
1
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
G1
G2B
G2A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
DATA BUS
6
5
4
U3
D1
D2
D3
D4
D5
D6
D7
D8
U2
A B C D E F G
7 6 4 2 1 9 10
330 . 8
/WR
8031
A13 1
A14 2
A15 3
VCC
7 6 4 2 1 9 10
D0
D1
D2
D3
D4
D5
D6
D7
7 6 4 2 1 9 10
A B C D E F G
19
18
17
16
15
14
13
12
17
16
29
30
11
10
A B C D E F G
LED4
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
RD
WR
PSEN
ALE/P
TXD
RXD
A13
A14
A15
D1
D2
D3
D4
D5
D6
D7
D8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
LED3
D0
D1
D2
D3
D4
D5
D6
D7
INT0
INT1
T0
T1
21
22
23
24
25
26
27
28
74LS573
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
LED2
11
1
1
2
3
4
5
6
7
8
RESET
LED1
330 . 8
12
13
14
15
X2
D0
D1
D2
D3
D4
D5
D6
D7
X1
39
38
37
36
35
34
33
32
18
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
19
EA/VP
31
Hin th s
a ch ca cc IC cht nh sau:
U3: 8000H.
U4: A000H.
U5: C000H.
U6: E000H.
an chng trnh sau y hin th 4 s trn 4 LED 7an. Cc s hng ngn v hng trm ct trong nh
31H ca RAM bn trong, cn cc s hng chc v hng
n v ct trong nh 30H di dng s BCD.
Hin th s
S cn
hin th
M BCD
M 7 on
M xut ra port 0
D7D6D5D4D3D2D1D0
0000
C0H
0001
F9H
0010
A4H
0011
B0H
0100
99H
0101
92H
0110
82H
0111
F8H
1000
80H
1001
90H
Hin th s
ORG 0000H
CS4 EQU 8000H
CS5 EQU 0A000H
CS6 EQU 0C000H
CS7 EQU 0E000H
MOV A, 30H
ANL A, #0FH
ACALL BCDTO7SEG
MOV DPTR, #CS7
MOVX @DPTR, A
MOV A, 30H
SWAP A
ANL A, #0FH
ACALL BCDTO7SEG
Hin th s
MOV DPTR, #CS6
MOVX @DPTR, A
MOV A, 31H
ANL A, #0FH
ACALL BCDTO7SEG
MOV DPTR, CS5
MOVX @DPTR, A
MOV A, 31H
SWAP A
ANL A, #0FH
ACALL BCDTO7SEG
Hin th s
MOV DPTR, #CS4
MOVX @DPTR, A
BCDTO7SEG:
MOV DPTR, #LED7SEG_TABLE
MOVC A, @A+DPTR
RET
LED7SEG_TABLE:
DB 0C0H, 0F9H, 0A4H, 0B0H, 99H, 92H, 82H, 0F8H, 80H, 90H
END
Hin th s - phng php qut

VCC
10K
10K
10K
10K
U1
12
13
14
15
B0
B1
B2
B3
L0
L1
L2
L3
1
2
3
4
5
6
7
8
X2
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
1K
L3
1K
Q1
A1015
L2
1K
Q2
A1015
LED1
21
22
23
24
25
26
27
28
17
16
29
30
11
10
L1
1K
Q3
A1015
LED2
X1
39
38
37
36
35
34
33
32
U2
7
1
2
6
VCC
3
5
4
1
2
4
8
LT
RBI
BI/RBO
A
B
C
D
E
F
G
LED4
A B C D E F G
A B C D E F G
A B C D E F G
A B C D E F G
7 6 4 2 1 9 10
7 6 4 2 1 9 10
7 6 4 2 1 9 10
7 6 4 2 1 9 10
A B C D E F G
A B C D E F G
A B C D E F G
A B C D E F G
330 . 7
13
12
11
10
9
15
14
Q4
A1015
LED3
8031
B0
B1
B2
B3
L0
18
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
19
EA/VP
31
A
B
C
D
E
F
G
74247
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
(L3)
1
(L2)
1
(L1)
1
(L0)
0
4 bit ca s BCD hng chc.
4 bit ca s BCD hng trm.
4 bit ca s BCD hng ngn.
P1.0
(D3)
(D2)
(D1)
(D0)
4 bit ca s BCD hng n v.

ORG 0000H
MOV TMOD, #01H
MOV A, 30H
ANL A, #0FH
ORL A, #0E0H
MOV P1, A
ACALL DELAY
MOV A, 30H
SWAP A
ANL A, #0FH
ORL A, #0D0H
MOV P1, A
ACALL DELAY

MOV A, 31H
ANL A, #0FH
ORL A, #0B0H
MOV P1, A
ACALL DELAY
MOV A, 31H
SWAP A
ANL A, #0FH
ORL A, #70H
MOV P1, A
ACALL DELAY
SJMP AGAIN

DELAY:
MOV TH0, #HIGH(1000)

MOV TL0, #LOW(1000)
SETB TR0
JNB TF0, $
CLR TR0
CLR TF0
RET
END

DATA BUS
U1
31
19
18
9
L2
L3
12
13
14
15
1
2
3
4
5
6
7
8
U2
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
X2
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
D0
D1
D2
D3
D4
D5
D6
D7
39
38
37
36
35
34
33
32
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
CS
21
22
23
24
25
26
27
28
11
1
A13
A14
A15
/WR
A
B
C
D
E
F
G
DP
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
C
OC
74LS573
17
16
29
30
11
10
D1
D2
D3
D4
D5
D6
D7
D8
U4
A13 1
A14 2
A15 3
VCC
6
5
4
L1
L0
8031
A
B
C
G1
G2B
G2A
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U11A
/WR
2
CS
1
3
74LS138
7402
0
10K
1K
Q1
A1015
L2
Q2
A1015
LED1
10K
1K
L1
1K
Q3
A1015
LED2
L0
Q4
A1015
LED3
LED4
L3
10K
1K
10K
VCC
A B C D E F G
A B C D E F G
A B C D E F G
A B C D E F G
7 6 4 2 1 9 10
7 6 4 2 1 9 10
7 6 4 2 1 9 10
7 6 4 2 1 9 10
A B C D E F G
A B C D E F G
A B C D E F G
A B C D E F G

ORG 0000H
DONVI BIT P3.0
CHUC BIT P3.1
TRAM BIT P3.2
NGAN BIT P3.3
MOV TMOD, #01H
SETB DONVI
SETB CHUC
SETB TRAM
SETB NGAN

AGAIN:
MOV A, 30H
ANL A, #0FH
ACALL BCDTO7SEG
ACALL OUT
SETB NGAN
CLR DONVI
ACALL DELAY
MOV A, 30H
SWAP A
ANL A, #0FH
ACALL BCDTO7SEG
ACALL OUT

SETB DONVI
CLR CHUC
ACALL DELAY
MOV A, 31H
ANL A, #0FH
ACALL BCDTO7SEG
ACALL OUT
SETB CHUC
CLR TRAM
ACALL DELAY
MOV A, 31H
SWAP A
ANL A, #0FH
ACALL BCDTO7SEG
ACALL OUT
SETB TRAM
CLR NGAN
ACALL DELAY
SJMP AGAIN

BCDTO7SEG:
MOV DPTR, #LED7SDEG_TABLE
MOVC A, @A+DPTR
RET
OUT:
MOV DPTR, #0E000H
MOVX @DPTR, A
RET
DELAY:
MOV TH0, #HIGH(1000)
MOV TL0, #LOW(1000)
SETB TR0
JNB TF0, $
CLR TR0
CLR TF0
RET
END
Giao din vi ADC
Bat au
Khong cho phep

ngo ra (OE = 0)
Chon kenh tng t

(xac lap cac a
ch CBA)
Tao xung ALE
Tao xung Start
Ch bien oi xong
(tao tr hoan 120 s hoac
ch
EOC = 1)
Cho phep ngo ra
(OE = 1)
oc d lieu
Ket thuc
Giao din vi ADC

U1
U2
ANALOG
26
27
28
1
2
3
4
5
IN
VCC
12
16
CLK-AD
10
VCC
9
7
P3.4
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
D0
D1
D2
D3
D4
D5
D6
D7
REF+
REF-
A0
A1
A2
CLK
START
ALE
OE
EOC
B0
B1
B2
B3
B4
B5
B6
B7
17
14
15
8
18
19
20
21
P3.0
P3.1
P3.2
6
22
U3A
1
2
A
CLR
QA
QB
QC
QD
3
4
5
6
30p
19
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
12M
18
X2
30p
25
24
23
ADC0809
CLK12
31
CLK-AD
P3.3
9
CLK12
P3.2
P3.3
P3.4
B0
B1
B2
B3
B4
B5
B6
B7
12
13
14
15
1
2
3
4
5
6
7
8
74LS393
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
8031
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
P3.1
P3.0
Giao din vi ADC

ADC:
CLR P3.0
CLR P3.1
CLR P3.2
CLR P3.3
SETB P3.3
CLR P3.3
JNB P3.4, $
MOV 40H, P1
RET
; chn knh 0.
; to xung START v ALE.
; ch EOC ln 1.
; c ADC.
Giao din vi ADC

ADC:
CLR P3.0
CLR P3.1
CLR P3.2
CLR P3.3
SETB P3.3
CLR P3.3
ACALL DELAY120
MOV 40H, P1
RET
DELAY120:
PUSH 07H
MOV R7, #60
DJNZ R7, $
POP 07H
RET
; chn knh 0.
; to xung START v ALE.
; ch 120 s.
; c ADC.
; ct ni dung R7 vo stack.
; lp li 60 ln.
; lnh ny thc thi trong 2 s nn ta tr hon 120 s.
Giao din vi ADC

DATA BUS
U1
U2
ANALOG
26
27
28
1
2
3
4
5
IN
VCC
12
16
CLK-AD
10
OE
P1.3
9
7
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
D0
D1
D2
D3
D4
D5
D6
D7
REF+
REF-
A0
A1
A2
CLK
START
ALE
OE
EOC
D0
D1
D2
D3
D4
D5
D6
D7
17
14
15
8
18
19
20
21
31
30p
19
18
A
CLR
QA
QB
QC
QD
P1.0
P1.1
P1.2
6
22
CLK12
12
13
14
15
START
P1.0
P1.1
P1.2
P1.3
3
4
5
6
X1
X2
30p
25
24
23
U3A
1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
12M
ADC0809
CLK12
EA/VP
CLK-AD
1
2
3
4
5
6
7
8
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
8031
74LS393
0
U4
A13 1
A14 2
A15 3
VCC
6
5
4
U5A
A
B
C
G1
G2B
G2A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
/WR
2
1 START
3
7402
U5B
5
4
/RD
OE
74LS138
7402
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
A13
A14
A15
/RD
/WR
Giao din vi ADC

ADC:
CLR P1.0
; chn knh 0.
CLR P1.1
CLR P1.2
MOV DPTR, #4000H ; a ch ca ADC.
MOVX @DPTR, A
; to xung START v ALE (Y2
; v WR bng 0).
JNB P1.3, $
; ch EOC ln 1.
MOVX A, @DPTR
; c ADC (Y2 v RD bng 0).
MOV 40H, A
; ct vo nh 40H
RET
Giao din vi ADC

DATA BUS
U1
U2
ANALOG
26
27
28
1
2
3
4
5
IN
VCC
12
16
CLK-AD
10
OE
9
7
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
D0
D1
D2
D3
D4
D5
D6
D7
REF+
REF-
A0
A1
A2
CLK
START
ALE
OE
EOC
D0
D1
D2
D3
D4
D5
D6
D7
17
14
15
8
18
19
20
21
30p
19
18
P1.0
P1.1
P1.2
6
22
CLR
CLK12
12
13
14
15
START
U6A
P1.0
P1.1
P1.2
P1.3
2
7404
U3A
A
QA
QB
QC
QD
3
4
5
6
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
X2
30p
25
24
23
1
1
EA/VP
12M
ADC0809
CLK12
31
CLK-AD
1
2
3
4
5
6
7
8
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE/P
TXD
RXD
8031
74LS393
0
U4
A13 1
A14 2
A15 3
VCC
6
5
4
U5A
A
B
C
G1
G2B
G2A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
/WR
2
1 START
3
7402
U5B
5
4
/RD
OE
74LS138
7402
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
A13
A14
A15
/RD
/WR
Giao din vi ADC

ORG 0000H
LJMP MAIN
ORG 0003H
LJMP EXT0_ISR
ORG 0030H
MAIN:
CLR P1.0
CLR P1.1
CLR P1.2
MOV DPTR, #4000H
MOVX @DPTR, A
SJMP $
EXT0_ISR:
MOV DPTR, #4000H
MOVX A, @DPTR
MOV 40H, A
RETI
END
; chn knh 0.
; a ch ca ADC.
; to xung START v ALE (Y2 v WR bng 0).
; ch ngt.
; a ch ca ADC.
; c ADC (Y2 v RD bng 0).
; ct vo nh 40H
Giao din vi DAC

DATABUS
U1
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
U2
EA/VP
X1
X2
RESET
21
22
23
24
25
26
27
28
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
D0
D1
D2
D3
D4
D5
D6
D7
39
38
37
36
35
34
33
32
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
17
16
29
30
11
10
RD
WR
PSEN
ALE/P
TXD
RXD
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
CS
D1
D2
D3
D4
D5
D6
D7
D8
11
1
B0
B1
B2
B3
B4
B5
B6
B7
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
C
OC
74LS573
0
A13
A14
A15
U3
A13 1
A14 2
A15 3
VCC
/WR
A
B
C
6
5
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G1
G2B
G2A
8031
15
14
13
12
11
10
9
7
U4A
2
1 CS
/WR 3
7402
74LS138
0
2K7
U7
14
2K7
15
A8
A7
A6
A5
A4
A3
A2
A1
IOUT
IOUT
COMP
2
4
-12V
16
0.01u
VR+
VR-
V-
V+
13
DAC0808
2K7
0
0.01
VCC
4
1
5
12
11
10
9
8
7
6
5
B0
B1
B2
B3
B4
B5
B6
B7
0.01u
+12V
0
0 VCC -VCC
10K
6
ANALOG OUT
LM741
Giao din vi DAC

I FS
255
xI REF
256
V
I REF REF
R
I
I OUT REF x (giatr cua manh phan ngovao)
256
Vana log_ out 2.7k x I OUT

VREF
Vana log_ out 2.7k x
x (giat r ma8 bit )
256 x 2.7k
V
Cc dng lnh sau y s xut ra
Vana log_ out REF x (giat r ma8 bit )
256
Vanalog_out in p 4 V.
MOV DPTR, #8000H
MOV A, #(255 x 4 / 5)
MOVX @DPTR, A
Giao din vi bn phm my tnh

5V
LCD-HD44780
VSS
VEE
VDD
EN
RS
R/W
R3
1
2
3
4
5
6
7
8
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
19
18
9
30pF
12MHz
10k
VCC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
XTAL1
XTAL2
RST
EA/VPP
30pF
5V
5V
10uF
100
Reset
R1
R
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
P3.3
P3.1/TXD
P3.2/INTO
P3.0
P3.4/TO
P0.3
P0.4
P0.5
PSEN
20
31
P0.0/AD0
P0.1/AD1
P0.2/AD2
P3.7
P3.6
P3.5
P0.6/AD6
P0.7/AD7
GND
39
38
37
17
16
15
33
32
VCC
40
AT89C51
ALE/PROG
21
22
23
24
25
26
27
28
13
11
12
10
14
36
35
34
29
30
Key board
6
4
2
5
3
1
Giao din vi bn phm my tnh

Mo Rong Port

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Mo Rong Port

Uploaded by

Copyright:

Available Formats

Vi iu khin 8051

Mt s bi tp giao din vi ngoi vi

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

M rng port xut vi cc mch cht

M rng port xut vi cc mch cht

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051 .

M rng port nhp

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

M rng port nhp

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

M rng port vi PPI 8255

M rng port vi PPI 8255

M rng port vi PPI 8255

M rng port vi PPI 8255

M rng port vi PPI 8255

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Hin th s - phng php qut

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Hin th s - phng php qut

4 bit ca s BCD hng chc.

4 bit ca s BCD hng trm.

4 bit ca s BCD hng ngn.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Hin th s - phng php qut

Hin th s - phng php qut

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Hin th s - phng php qut

MOV TH0, #HIGH(1000)

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Hin th s - phng php qut

Hin th s - phng php qut

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Hin th s - phng php qut

Hin th s - phng php qut

Hin th s - phng php qut

Giao din vi ADC

Khong cho phep

Chon kenh tng t

Tao xung ALE

Tao xung Start

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Giao din vi ADC

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Giao din vi ADC

; to xung START v ALE.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Giao din vi ADC

; to xung START v ALE.

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Giao din vi ADC

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Giao din vi ADC

Giao din vi ADC

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Giao din vi ADC

Bin son: Tng Vn On, da theo ti liu Thit k h thng vi h 8051.

Giao din vi DAC

Giao din vi DAC