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    Design & Analysis of a Hysteretic Boost Power Factor Correction Ckt

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    11 views8 pages

    Design & Analysis of A Hysteretic Boost Power Factor Correction CKT

    Uploaded by

    ankurmalviya
    Design & Analysis of a Hysteretic Boost Power Factor Correction Ckt

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    © All Rights Reserved
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    Design and Analysis of Power Factor Cor: a Hysteretic Boost rection Circuit C. Zhou, R.B. Ridley, and F.C. Lee Abstract The design of an active unity power factor correction circuit with variable-hysteresis control for offline _Seitching power supplies is described, Design equations relating the boost inductor current ripple to the boost inductor selection and circuit performances are devel- ‘oped and ave verified with measurements. A computer- ‘aided design program is developed to select the optimal circuit components. Design guidelines for the low frequency feedback nerwork are presented using the switch model for the power factor correction circuit ‘Smalt-signat ransfer functions for open and closed-loop responses are derived. L.Introduction Conventional off-line switch-mode power supplies Graw pulsating ac line current, resulting in low power factor and high RMS line current, Switching power supplies with bridge rectifiers have less than 2 0,65 power factor. The harmonic current the converter gen- erates distom the ac line voltage and cause power distur- tances in an office environment. The high RMS line current also places @ high stress on the bridge rectifier and the energy storage capacitor. ‘With increasing demand for more power and beter power quality from a standard 110 - 220 VAC line, ower factor correction becomes an integral part of 2 switching power supply. During the past few years, several technical papers have been published on this subject 1-6]. Most ofthese papers introduced interesting topologies for power factor correction and various small-signal models. In this paper, the efforts will be concentrated on the design and optimization of a boost power factor circuit ith variable-hysteresis control. The boost topology is well suited for power facior correction since the boost Sndocior isin series with che ac power line. This results ‘in minimum conducted EMI at the line when the circuit ‘operates in continuous conduction mode. Fig. 1 shows the functional diagram of the boost power factor correc- tion circuit. A series resistor senses the inductor current, and a set of resistive dividers sense the rectified line voltage. The conwol circuit is designed so that the inductor curren follows the shape ofthe rectified ac line voltage. To regulate che load, the error amplifier senses the variations between the output voltage and the fixed 4 reference. This exor voliage is multiplied with the sensed rectified line voliuge 10 contol the inductor current amplitude, ‘An analysis of the boost power factor circuit with varable-hysteesis contol is performed. Equations for selecting the boost inductor and owrput Slter capacitor are derived. Approximated expressions of RMS inductor curren, RMS swixch cunent, and MOSFET switching logs ame derived 1 estimate che efficiency of the circuit. ‘A computer-aided design optiraization program is eveloped to select circuit components that will meet customer's efficiency and input-output requirements. “The design guidelines for the low-frequency feed- back compensator are presented based on the average stnall-signal power factor switch model £7}. The model provides a simple and nonterative way for the optim) 1 This work was suppor in part by the IBM Corporation, Endicou, NY, and the Virginia Center for Innovative Technology. 2 Presently with Delta Power Electronic Lab, Inc., Blacksburg, Virginia. © 1990 IEEE. Reprinted, with permission, from, and Exposition, San Antonio, 341 Proceedings of the IEEE Power Electronics Specialists Conference ei we selection of the control paramevers. Experimental results, have shown the accuracy of the model and its usefulness in practical design. Figure 2 Boost Inductor Current with Variable-Hysteresis Control (Wp sim (2) = (Vo Vp Sin igre o Vpsineoe Yo sdQ)= 1 @ 100% (3) where Vis the peak rectified ac line voltage and Vo is he de output voltage of the boost power factor circuit, With a specified inductor current ripple, 8, the transistor on- time is [8] Figure 1 Functional Diagram of an Active Boost “ Power Facior Correction Circuit o 2. Analysis of the Boost Power Factor Circuit ‘The boost inductor current waveform is shown in Fig. 2. The upper inductor curent referene i half sinusoid, denoted I intt, with a peak amplinade of /,. The lower current reference is a half sinusoid, denoted /-snax, with 2 peak amplitude of /c, The average inductor current, ‘which has only the 120 Hz component of inductor crarent, is aha simasid, denoted /sinew. The inductor curent ripple is Ssinat, where & is the peak current ripple. Since the inductor current switches at 3 much t higher rate than the Line voltage, the line voltage is sssimed constant in ech inductor curentewiching TUwe3 Pps ea eet cycle, Fig. 4 shows that, atthe start of a rectified line cycie, 3.1 Duty Cytte and Transistor On-Time the tansisiot turn-on time has to be longer in order for the inductor current to reach the upper current reference, Jpsinaw. At the end of the cectified line cycle, the From Fig. 3, the wansistor dury cycle can easily be inductor current switches extremely fast. In acual circuit implementation, the transistor is turned off atthe end of the cycle to avoid high-frequency switching, Transisior turn-on time, oy: in the middle of the rectified line cyele, is approximately constant and is expressed by [8] od o > ae ne e0e} ‘m8 n.008 Figure 4 Transistor On-time at Different Time Insuants Eq. 6 an important result, which tls us two things: (2)if the cireuitisrunning a the constant on-time, ron, the shape of the Peak inductor cument follows the line voltage automatically. This property also exists when the inductor curent operates in discontiquous current mode. By running the circuit in discontinuous mode with con- stant on-time, the contol circuit is greatly simplified. No current sense is required, and no need to use a multiplier in the control circuit. In the hysteresis contrl, the lower current reference, sin, is needed to turn the transis- tor back on, (2) For the variable-hysteresis control, the inducuor current is switching at a variable frequency. The total ‘number of switching cycles within a rectified line cycle can be determined. They are approximated by first cal- culating the total tansistor on-time within the rectified line cycle, Toy (8) r ds where Ts is the period of the half-line cycle. The number of switching cycles can approximated by dividing Eq, 7 and Eq. 6, Thus, we obtain an equivalent switching frequency of the circuit, to be used in the calculations of MOSFET switching loss and magnetic core loss (8) . M dda = T, o Tox Toy _120Vp Fea) Eee @¥,-%,) ®) 32. RMS Current ‘The values of the RMS inductor and RMS switch current are required when calculating transistor conduc- tion loss and inductor copper loss, They are evaluated by calculating their RMS values inane switching cycle, then integrating them over the rectified line cycle. From reference (8) 1 Vat a | th 38) ° i Fake) ‘igus (inductor) = Berge (10) From Eq. 9 and Eq. 10, the magnitudes of RMS transistor ccurrent and inductor current depend upon the inductor current rippie, & A power factor circuit operating in discomtinuous mode has the highest RMS transistor and inductor current, fayalite) = 3.3 Ouput Voltage Ripple The output voltage ripple, AV, is given by (8) as ale (e_ > avon, iana=d|E-ae) 0) ‘where Vj is the ourput voltage ripple, and Cy isthe filter capacitance. 3.4 MOSFET Switching Loss ‘The MOSFET switching loss P,, can be caleuated by integrating the energy losses daring he MOSFET tum-on rise-time and turn-off fallime periods. An ‘empirical solution is (8) Ver, VoP eo ys eae lett let) 2) where 1, is the MOSFET turn-on rise-time, and {, ig the MOSFET turn-off fall-ime. 343 2.5 Power Factor Analysis ‘The following equation defines the power-factor: iov(ende TeaaVines ax where i) and v(:) are the instantaneous line current and ‘voltage. [ys and Vays af the RMS values of line current and voliage. ‘The high-frequency switching ripple, Bsinay, reduces the power factor. Unity power factor cannot be achieved without sufficient input fering, The following expres- sion relates the power factor and inductor current ripple: f= e Tae ‘One problem associated with the variable hysteresis ‘control isthe very high switching frequency at the end of ‘arectified line cycle, where the voltage approaches zero. To avoid very fast switching action of the MOSFET, a ‘small dead time is invoduced. A certain delay atthe start Of the rectified line cycle also simplifies the circuit implementation. From Fig. 5, the power factor will decrease with the longer transistor off-time during that period. The length of the dead time is represented by a dead angle, 8. A simple expression relates the power factor and the amount of dead angle [8] pia : + sin 28) aa) a4) @ pay Figure 5 Rectified Line Currem with a Dead Angle Fig. 6 shows a plot of power factor versus the dead angle and current ripple. It shows that, a8 the inductor current ripple increases, the power factor gets worse. The lowest power factor is 086, when the correction circuit operates in discontinuous mode with a 200% current ripple. A small filter capacitor C;, placed right after the bridge rectifier. restores the power factot very close 10 unity. Notice tat the power factor changed litle when the dead angle was below 10-degrees. ‘uxt rae ore) Figure6 Power Factor at Various Dead Angles ‘The first harmonic component of the line current with ‘adead angle can be evaluated from Fourier imegral, as) ‘The sum of higher harmonic components is obisined by subwacting the fundamental, lgys(1). from the total RMS current fy. The 6tal harmonic distortion of the ‘current waveform shown in Fig. 5 is te ratio of the sum ‘of higher harmonic components 1 the fundamental, Jeus(1). Fig, 7 shows a plot of total harmonic distortion of the line current versus its dead angle. The total harmonic distortion is about 5% when its dead angle is 10 degrees. Deas Ang eet) Figure 7 Harmonic Distortion Versus Dead Angles 344 3. Computer-Aided Design of the Boost Power Stage ‘The boost inductor, Ly isthe mos difficult compo- nent to design in a power factor correction circuit. The ‘choice of inductor size and the amount of inductor current ripple will affect circuit efficiency and weight, ‘The size ofthe inpu filler also increases a 8 increases. ‘Annonlinear design optimization routine [9} was used develop a computer-aided design program with the ‘equations developed in this paper. The program enables a designer to select the optimal Ly and § without much rial-and-eror paper and bench work. Table 1 shows the design results of a 500 W. 300 V boost power factor correction circuit In this design, the required efficiency (including the bridge rectifier loss) is ‘95%, and the inductor curent ripple is 30%. From the table, the MOSFET takes 65% of the total power stage loss. Table I ( Cont. } ‘Curent Te | Upper carentreference [6.76] ee TIRMS) | RMS inducor euvenr | 218 | SS SSS i peroneal SS === * Magnetics 44022-EC core. ‘The power factor circuit can also be optimized over a ‘wide range of current ripple and efficiency. Fig. 8 shows a plot of inductance versus current ripple at 95% effi iency, As the current ripple increases, the inductance decreases. The smallest inductance occurs at the discontinuous mode. Therefore, running the circuit in the discontinuous mode sesults in che smaliest inductor size and power stage weight. The penalty is higher current ssuess and conduction loss. The input filter size also increases as the current ripple increases. Experiment has shown that 2 power factor circuit with smaller current ripple is suitable for high-power applications, when the noise generated by the inductor current and MOSFET ‘curren suress are the primary concem. The discontinuous ‘mode operation, on the other hand, is beuer suited for low ower application when the objectivesare small. core size and low-cost control circuits. Inccance (nt) current Rg) Figure 8 Inductance versus Inductor Current Ripple ar 95% Efficiency Tabled Boat Power Factor Cire Power Stage Design Result Tinant [rrv@ol] —Descurnon [wae] wa elie Vat | vac | Our | ve | ompmvaine | sve te | uptown | ow Vane | On Voiag Rip | 20VDE fimo | er | ieee |e feeclaom osc ee weno’ [t| tenmes | oma re 7% te | Comersin fase | Atte | en eee pe B_[Mesimon xan | 027 F_| windne ence | 19 F_| Wow flitmer [0 Wo | setticies | 10mm & c Capacitor 295 uF 345 Iracance (ty Figure 9 Inductance versus Boost Power Stage Efficiency at 30% Currens Ripple Fig. 9 shows a plot of inductance versus efficiency at the 30% current ripple. The efficiency of the power stage increases when the inductor size increases. Since the transistor takes most of the loss in the boost power factor circuit, the bigger inductor size means a smaller transis- tor switing loss. Therefore, up to a certain point, selecting a bigger inductor reduces the large transistor Joss and improves the efficiency of the power stage. 4. Experimental Results ‘A.boost power factor circuit with a 300 V output, $00 W ouput power was built [8]. The circuit uses a variable-hysteresis control method, with its inductor ccurent ripple adjustable from 10% to 200%. Fig. 10 shows the boost inductor curent with 30% current ripple and rectified line voltage. A small dead angle is intro- uced to avoid MOSFET high-frequency switching at 2210 line voltage. A 20 UF capacitor, C, is placed after the bridge rectifier to filter the high-frequency switching current pple. Fig. 11 shows the line voltage and current after fering. Figures 12 and 13 show the circuit wave- forms for 100% inductor curent ripple. This higher current ripple results higher curent stress and a bigger inpot fits. ‘Table I shows the experimental results for the 30% and 100% current ripple cases. The apparent power is the. product of total RMS line current and voliage. The real ower from the ac line is measured using a wattmeter. ‘Oupun power is the product of de ourput voltage and current, The measured circuit efficiency of 93.2% is lower than the 95% efficiency predicted by software. This is due 10 the snubber loss and resistive losses in she

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