:

.
/ .
,
.

.
,
.
,
.

:

.
,
.

.
, MSc, PhD

.
/ & , MSc

2005

.

.
, MSc, PhD
.
/ & , MSc

opusMAGNUM

/ 19972005
ISBN: 960-538-586-4
: 21/4
Copyright 2005

16 & , 26222 : 2610 367336, 367355 : 2610 361420
. 2121/1993,
, .

19

21

, , ..................................... 23
1.1

(Breadboard)................................................................................. 24

1.2

...................................................................................................... 26

1.3

........................................................................ 28

1.4

................................................................. 30

, , ..................................... 35
2.1

...................................................................................... 36

2.2

................................................................................. 39

Boole
, , ..................................... 47
3.1

...................................................................................... 48
3.1.1

Boole .................................................................................... 48

3.1.2

................................................................. 49

3.1.3

Karnaugh ................................ 50

3.1.4

................................................................. 52

3.1.5
3.2

......................................................... 53

................................................................................ 54

/
, , ..................................... 61
4.1

4.2

...................................................................................... 62
4.1.1

............................................................................................. 62

4.1.2

....................................................................................... 62

4.1.3

............................................................................... 63

4.1.4

.................................................................................... 64

4.1.5

............................................................. 65

4.1.6

.................................................... 65

4.1.7

............................................................................................ 66

4.1.8

...................................................................................... 66

4.1.9

............................................................................... 67

................................................................................ 69

/
, , ..................................... 75
5.1

5.2

...................................................................................... 76
5.1.1

........................................................................................ 76

5.1.2

.......................................................................................... 77

................................................................................ 79

/
, , ..................................... 85
6.1

...................................................................................... 86
6.1.1

6.2

7 ............................................................................. 86

................................................................................. 89

Flip-Flops
, , ..................................... 95
7.1

7.2

...................................................................................... 96
7.1.1

(Latch) ........................................................................... 97

7.1.2

FFs RS ............................................................... 98

7.1.3

FF D........................................................................................... 99

7.1.4

JK flipflop ......................................................................................... 100

7.1.5

flipflops ............................................................... 101

7.1.6

............................................................................ 101

............................................................................... 103

, , ................................... 109
8.1

.................................................................................... 110
8.1.1

................................................................. 110

8.1.2

................................................. 111

8.1.3

............................................ 114

8.1.4

.................................................................... 114

10

8.2

8.1.5

................................................... 114

8.1.6

.............................................. 116

8.1.7

......................................................... 116

.............................................................................. 118

, , ................................... 125
9.1

9.2

.................................................................................... 126
9.1.1

........................................ 127

9.1.2

/ ................... 127

9.1.3

/ ............... 129

9.1.4

/ ........... 129

9.1.5

/ ............... 131

.............................................................................. 134

139

10

, , ................................... 141
10.1 ........................................................................................................ 143
10.2 ISA CPU............................................................................................... 144
10.3 ................................................................................ 145
10.4 .................................................................... 148
10.5 ......................................................................................... 150
10.6 ......................................... 151

10.7 (Execute Cycle) ....................................... 153

10.7.1 CLR .............................................................. 153
10.7.2 ND ............................................................. 153
10.7.3 XOR ............................................................. 153
10.7.4 ADD ............................................................. 154
10.7.5 SUB............................................................... 154
10.7.6 LDA .............................................................. 155
10.7.7 NC ............................................................... 156
10.8 CPU ....................................................... 157
10.9 (Hardware) CPU ............................................ 158
11

/
, , ................................... 161
11.1 .................................................................................... 162
11.1.1 / (ALU).................. 162
11.1.2 ALU (AC) ........... 163
11.1.3 ALU ............................................................................ 165
11.2 ............................................................................... 168
12

, , ................................... 173
12.1 .................................................................................... 174
12.2 ............................................................................... 179

11

12

13

, , ................................... 187
13.1 .................................................................................... 188
13.1.1 ............................................................................. 188
13.1.2 ........................................................................................ 188
13.1.3
microsequencer.................................................................................. 190
13.1.4 ......................................................... 193
13.2 .............................................................................. 200
14

CPU
, , ................................... 207
14.1 .................................................................................... 208
14.1.1 ........................................................................................... 208
14.1.2 ........................................................................... 208
14.2 .............................................................................. 211

(Assembly)

215

15

, , ................................... 217
15.1 .......................................................................... 218
15.2 ................................................................................. 219

15.3 ............................................................................................... 220

15.4 ................................................. 222
15.5 ............................................................................. 226
16

, , ................................... 227
16.1 .................................................................................... 229
16.1.1 ................................................................................. 229
16.1.2 8085 ...................................................... 230
16.1.3 8085............................................... 232
16.2 ............................................................................... 234
17

, , ................................... 241
17.1 .................................................................................... 242
17.2 ............................................................................... 245
18

, , ................................... 251
18.1 .................................................................................... 253
18.2 ............................................................................... 255

13

14

19

/
, , ................................... 267
19.1 .................................................................................... 268
19.1.1 ................................................................................ 268
19.1.2 / ..................................................................... 269
19.1.3 ........................ 271
19.1.4 Booth .................................. 271
19.2 .............................................................................. 274
20

, , ................................... 283
20.1 .................................................................................... 284
20.1.1 .............................................................................................. 284
20.1.2 ....................................................................................... 286
20.1.3 ...................................................................... 287
20.1.4 postfix reverse polish................................... 288
20.2 .............................................................................. 291
21

/
, , ................................... 299
21.1 .................................................................................... 300
21.1.1 /.................................................................... 300
21.1.2 (bubblesort)................ 301
21.1.3 (binary search)................. 301

15

21.2 ............................................................................... 303

311

(data sheets)

313

VHDL

325

.1

.............................................................................................................. 325

.2

VHDL ............................................................... 327

.3

VHDL................................................ 328

.4

VHDL ......................................................... 329

.4.1

(comments) ............................................................................ 329

.4.2

(data objects) ............................................ 329

.4.3

(data types)........................................................... 330

.4.3.1 STD_LOGIC STD_LOGIC_VECTOR ..................... 330
.4.3.2 SIGNED UNSIGNED ................................................. 331
.4.3.3 INTEGER ............................................................................ 332
.4.3.4 BIT BIT_VECTOR ...................................................... 332

.4.4
.5

.6

(operators) .......................................................................... 333

VHDL........................................................... 335
.5.1

................................................................................... 335

.5.2

......................................................................................... 336

.5.3

................................................................................ 338

VHDL ..................................... 340

.6.1

(behavioral model) .................... 341

16

.6.1.1 PROCESS ............................................................. 343

.6.1.1.1 IF............................................................ 343
.6.1.1.2 CASE ..................................................... 346
.6.1.1.3 FOR LOOP........................................... 349
.6.2

(structural model) ................................ 351

.6.2.1 COMPONENT ..................................................... 353
.6.2.2 PORT MAP .......................................................... 354
.6.2.3 FOR GENERATE............................................... 355

.6.3

(dataflow model)................................... 356

.6.3.1
(Concurrent Signal Assignment) .......................................... 356
.6.3.2 (Conditional Signal Assignment)................................ 357
.6.3.3 SELECT ................................................................ 357

.6.4

PACKAGE.......................................................................... 359
.6.4.1 (package) .......................................... 360

.7

........................................ 362
.7.1

(clock) .......................................................................... 362

.7.1.1 falling_edge() rising_edge() .................. 362
.7.1.2 EVENT.................................................................. 362
.7.1.3 WAIT UNTIL....................................................... 363

.7.2

.................................. 363
.7.2.1 D flipflop ............................... 363
.7.2.2 D flipflop .................................. 365
.7.2.3 K 8 bits ...................................................... 365

.8

LPM .................................................. 367

17

.8.1

ROM ............................................................ 367

.8.2

*.mif............................................................................ 369

8085

373

.1

............................................................... 373

.2

................. 377
.2.1

................................................... 377

.2.2

( ) ...................... 377

.2.3

......................................................................... 380

.2.4

................................................................................ 383

.2.5

................................................................ 386

.2.6

.......................................................................... 387

.2.7

............................................................................... 389

.2.8

........................................................................................ 390

.2.9

/ ........................................................... 391

............................................................................................................. 393



, .
(-21) .
,
, .

( ),

.
.
/-, ,
( )
, ,
, , .
, VHDL
, / ,
, . ,
8085,
, , ,
. ( ), , , .
. . , . , . . . ,
. , , E.

20

. , .
.
. ,
20042005 . , . , . , . , . , .
, . , . , . , . - . , ,
, .
2005
.

. *
, MSc, PhD

. *

* . , , MSc, PhD.

,
.

, :
(breadboard)



.

(breadboard)

24

1:

1.1

(Breadboard)

(breadboard), 1.1. - -,
. -
. -
, ( ), 1.2. -
64 5 . -
, ( ). 1.2 -
.
-.
-
. -
.
+5 V . ,
. 1.3 - +5 V .
. , 1.3
+5 V, . 1.3 +5 V
.

1.1

1.1
(breadboard)

1.2
-

1.3

25

26

1:

1.2

() 9 V ( 1.4). ,
. +5 V. , , 9 V 5 V . 1.5.
.

1.4

1.5

9 V

9 V 5 V

L7805 1.5 (positive voltage regulator),

1.6. 1 , 9 V
, 3 , 5 V.
2 .

1.6
() L7805 ()

1.2

1.5 0.33 F 0.1 F. 1.7 .

, (0.33 0.1 ).

1.7

,
1.8. + .

1.8

27

28

1:

1.3

1 (2.4 V 5 V)
0 (0 V 0.4 V). 1.9. V
1 0.
220
( 1.10) (Light Emitting Diode LED) (D).
1.11 ,
.
(+) () . ,
(D) 1.9.

1.9

1.10

220

1.11
() ()

1.3

V 1,
(0 V) , . , V 0 (0 V),
.
,
, (LED) , ,
. , 5 V V , .

29

30

1:

1.4

(clock) (..
). , ,
, ,
, . 1.12. , 50% (50%
duty cycle). t1
(5 V) t2
(0 V). t1 t2 T (t1=t2=T/2), 1.12.
t1=t2=0.6 sec, =1.2 sec.
0.8 Hz.

1.12

LM555 1.13 (timer). (pins).

1 ( ). 2, 3 . 1 , 2 6, 4 8 5 V, 5 10 nF , -

1.4

6 820 nF ,
7 430 k 6, 6 1
5 V 3 .

1.13
() 555 ()

10 nF
820 nF, (10 n
820 n ). 430 k 1
1.12.
1.14. ,

.
.
, , ,
1.14. ( )
()
.
. ,
,
(
). ,
10105 =
1000000 = 1 , 5%. ,

31

32

1:

,
. , 430103 =
430000 = 430 k, 1%.

1.14

,
1.12 1.15. . , 1.15 . , +5 V
, .

1.4

1.15

33

NOT, AND, OR, NAND, NOR XOR.

, :


.

(data sheet)

36

2:

2.1

. (Integrated Circuit IC),
chip, .
,
(pins).

,
.

.
:
TTL

Transistor Transistor Logic

MOS

Metal Oxide Semiconductor

CMOS

Complementary MOS

TTL .

.
2.1

TTL
TTL

(Standard) TTL

74

7486

TTL

74H

74H86

TTL

74L

74L86

Schottky TTL

74S

74S86

Schottky TTL

74LS

74LS86

Schottky TTL

74AS

74AS86

74ALS

74ALS86

Schottky TTL

2.1

( ).

2.1

.
.

37

38

2:

, .
,
2.1. VCC GND ,
.
,
2.2. VCC GND
( 14 7 ).
, .. 2, 3 . , .. 2
2 , 3
3 . (, ) ().

2.2

2.2

2.2

NAND (7400),

NOR (7402),

NOT (7404),

AND (7408),

NAND (7410),

OR (7432),

XOR (7486).

.
1.

.
, ,
.
:

,
Vcc , (GND),
. , ,


.

2.

7404
( 1.2). , ,
+5 V (VCC) 0 V
(GND).

39

40

2:

3.

( 1, 1) . 0 1 (GND Vcc )

(LED), 1.
:

4.

7404

7408

7432

7400

7402

7486

AB

A+B

AB

A+B

7404
.
, .
, 2 , 7404
, 2 1
1 .

/

1
2
3
4
5
6
7
8
9

2.2

5.

41

1-4 :
7408, 7432, 7400, 7402, 7486.
:

(1-4) ,
7404
, , ,
, ( ) , , .

7408
. ;
;
; , ;

,
A

6.

 2:

42

2.2

7.

43

. . ;

8.

NOT, AND, OR, NOR XOR

NAND. 7400 (4

44

2:

). .
.
NAND
NAND

AND NAND

OR NAND

R NAND

XOR NAND

2.2

9.

45

( ) NOT, AND, OR,

NAND XOR NOR.
7402 (4 ).
.
NOR
NOR

AND NOR

OR NOR

AND NOR

XNOR NOR

46

2:

10. (.. NAND

NOR) ;
:

Boole

Boole
Karnaugh. ,
.

, :
Boole
Boole
Karnaugh
.

Boole



Karnaugh

 3: BOOLE

48

3.1

3.1.1

Boole

Boole
.
3.1

Boole

(OR)

(AND)

A+0=A

A1=A

A+ A =1

A A =0

A+B=B+A

AB = BA

3
( )
4
( )

A (B + C) = AB + BC

A + BC =
(A + B) (A + C)

A+A=A

AA=A

A+1=1

A0=0

A =A

( )
4
( )
5 (De Morgan)
6 ()

A + (B + C) =
(A + B) + C

A (BC) = (AB) C

A+B=AiB

AB=A+B

A + AB = A

A (A + B) = A

Boole . ( Boole)
. .

3.1

49

. ,
Boole, .
3.1.2

.

(AND) (OR), :
Y = A + AB + A B C
Boole
(OR) (AND),
:
Y = (AB + C D) ( A B + C D )
AND , OR
. ,

.
, n 2n
. 0 2n1
. , 1,
0.
.
mj, j , .
Mj.
.

 3: BOOLE

50

3.2

A BC

m0

A+B+C

M0

A BC

m1

A+B+ C

M1

ABC

m2

A+ B +C

M2

ABC

m3

A+ B + C

M3

A BC

m4

A +B+C

M4

ABC

m5

A +B+ C

M5

ABC

m6

A + B +C

M6

ABC

m7

A + B +C

M7

Boole . , 1
0 . ,
. , ,
001, 100, 111, :

Y=A BC+A BC+ABC=m1 +m 4 +m 7 = (1,4,7)

Y=A+B+C A+B+C A+B+C A+B+C(A+B+C)=
M 0 M 2 M 3 M 5 M 6 = (0,2,3,5,6)
3.1.3

Karnaugh

Karnaugh .
. ,

3.1

. ,

. ,
,
( 1)
1. Gray,
.
, , .
3.3

Karnaugh

.

. -

51

 3: BOOLE

52

1,
0.
,
.

, * .
3.1.4

Boole Boole. , Karnaugh.

. :
Karnaugh
Boole , 1 .
mj . Karnaugh
. ,
,
, . Boole

AND . , 1
,
, ... ( ) .
,
OR.

3.1

. ,
, . , ,
. ,
, .
Boole
,
, 0.
3.1.5

.
:
.
.
.
.

, .

53

 3: BOOLE

54

3.2

NOT (7404),

AND (7408),

OR (7432),

XOR (7486).

.
1.

.
De Morgan. .

()

()

3.2

55

2.

0, 1 .
.

3.

;
Boole.
.

 3: BOOLE

56

4.

. .

5.

, A B,
, G, E L, 1 , . ,
G, E, L, , , .
:

LEDs G, E, L .

3.2

57

G=
E=
L=

6.

(A, B, C, D).
1 0
/ / / /
1.
(
.)

 3: BOOLE

58

, Karnaugh, ( ) .

A

3.2

59

Karnaugh

Y=

, :



.

(half-adder)
(full-adder)
(carry)

62

4: /

4.1

4.1.1

,
. . .
4.1

10

, .
(carry).
,
. (half-adder),
(
) (full-adder).
.
4.1.2

. -

4.1

63

S (Sum: ) C (Carry: ) ,
:
4.2

, :

S=AB+AB
C=AB
4.1.3

. , , ,
Ci, , S Co. :

64

4: /

4.3

Ci

Co

( )
:

S=A BC i +ABC i +A BC i +ABC i

C o =ABC i +ABC i +ABC i +ABC i

4.1.4

, .
. , , (complements).

r, r r1. r
1 r1.
2, r=2, 2 1 .

4.1

1
1 , , 0 1 1 0.
2
1 1.
4.1.5

(borrow). , 1

. , .
(MN)
:
1. 2 .
2. , , ,
, .
3. <,
2 NM. 2 ()
.
4.1.6

, , . , . (+ ), .

,
0 1 .

65

66

4: /

,

bit
.
:
. ,

,
.

,
, .
0
, 1, . 1 2,
.
4.1.7

.
. ,
. , .
,
.
4.1.8

4.1

67

(borrow), . (D) :
4.4

Bo

Boole :

D=AB +AB
B o =AB
D
.
4.1.9

. , , , i, , D
B. :

68

4: /

4.5

Bi

:
D=A B B i +ABB i +A B B i +ABB i
B o =A B B i +ABB i +ABB i +ABB i

4.2

4.2

69

AND (7408),

OR (7432),

(7483),

XOR (7486).

.
1.

A
B S C
. ,
S C, , .
A

C=
S=

70

4: /

2.

. Ci,
.
C. , S C,
, .
A

Ci

C=
S=

4.2

3.

71

. , . .
:

72

4: /

4.

3,
/ 4 .
.
:

5.

7483 4 . i,
i
( 1 1 , LSB). i
( 1 LSB).
(C0) (C4).
/.
:

7486
7483 .
2.

0 1 .

(LED),
.

4.2

73

C0

C4

(4 bits)

(4 bits)

(1 bit)

(1+4 bits)

(
)

4+2
4+5
42
2+3
23
45

6.

(overflow); , ;

74

4: /

, :


.

21, 41 81
12, 14 18

76

5: /

5.1

5.1.1

.
21 :

5.1
21

, D0 D1, , ( A),
D0 0 D1
1. n 2n , (
), 2n1 . .
5.1

21
A

D0

D1

T 41 :

5.1

77

5.2
41

:
5.2

41
A

D0

D1

D2

D3

H
:

Y=D0 A B+D1 A B+D 2 A B+D3 AB

5.1.2

, n 2n .
. 14 :

78

5: /

5.3
14

:
5.3

14 ( 0 1)
A

Y0

Y1

Y2

Y3

, :

Y0 =IA B
Y1 =IAB
Y2 =IAB
Y3 =IAB
,
.

5.2

5.2

NAND (7400),

(7404),

NAND (7410),

OR (7432),

3--8 / 18 (74138),

81 (74151).

.
1.

41 . D0, D1, D2, D3

. .
.
:

, , D0,
D1, D2, D3 . , , D1, D1.

79

80

5: /

: , -

.
2.

74151 81.
.
G ;
( )
(D0-D7) A, B, C LED .
( .)
: 1)

74151 ,
2) 1
.
3.

. 2 3 74151.
.

5.2

4.

14.
0, 1, 2, 3.
,
, .
LED
, .
.

81

82

5: /

0 =

2 =

1 =

3 =

5.

1; .

6.

74138 38 18. .
G2A, G2B G1
.

5.2

7.

(W) 74151 (G1) 74138.

.

. 138 (
). LED.

W ;

83

84

5: /

, :


.

86

6: /

6.1

, .
, , , , .
.
.
.
.

2 . , , 4
16 .
16 . , 4 , 9, , 1001 .
10 16,
0 9.
6.1.1

,
7 (7-segment display).
7 (LEDs) ( ) ,
. , , , .. ,
( 6.1).

6.1

6.1
7

7 5 V, .
, 0, 0 V . , 0 V, . ,
1, 5 V .

87

88

6: /

6.2
7 : () ()

,
, 7 .
BCD 7 . , , , 0 ,
1 .

6.2

6.2

(7404),

NAND (7410),

38 / 18 (74138),

BCD to 7 segment (7448),

7 segment display.

.
1.

24 . A B
Y0, 1, Y2, Y3. S 1 .
; S 0;
, , S;

89

90

6: /

Y0

2.

NAND AND; ;

6.2

3.

91

74138 38 18. .
G2A, G2B
G1 . A, B, C 0-7.
;

4.

, YA
YB, 74138. .
=
=

5.

(DEC to BIN).

92

6: /

;
.

3 =
2 =
1 =
0 =

6.2

6.

7448 (BCD to 7 segment),

1 (active high) .
, 7 (7 segment displays)
( ).
(a, b, c, d, e, f g) A, B, C, D.
0
9.
: 3, 4 5 ( LT, BI/RBO, RBI )
1.
A, B, C, D.

7.

3, 4 5;
;

8.

a/b/c/d/e/f/g (
).
.

93

94

6: /

Flip-Flops

flip-flop
. flipflops .

, :
flip-flops
,
.

Flip-flops

(Latch)

96

7: FLIP-FLOPS

7.1

. , ,
. ,
.
: , . (, clock). () () .
.
,
. (feedback) . ,
(unstable).
,
.
flip-flop (FF). FFs.

7.1

7.1.1

(Latch)

7.1() , R S,
RS flip-flop , , RS (RS latch).
flip-flop
(level-sensitive clock). S R
SET RESET . SET
1, RESET . Q, (state) FF,
Q Q.

7.1
RS NOR: () , () , ()

S=1 R=0, Q
0, . , 0
Q=1. FF
FF 1 (SET). S 0 (S=0), FF, 1 [2
7.1()].
1. ,
FF .
R 1, R=1
S=0, 0 (Q=0) , , -

97

98

7: FLIP-FLOPS

1 (Q=1). ,
(RESET) FF. R 0,
S=0 R=0, FF , Q=0 Q=1. ,
FF .
, 1 0, S=1 R=0
S=0 R=1. S R
0. . , S
R 0. ,
FF 0, .
7.1.2

FFs RS

FFs RS () .
.
, FF AND NAND, 7.2.

7.2
RS FF: () NOR, () NAND, (), () , ()

7.1

, (clock, CLK) 1
(CLK=1) S R SET
RESET FF. CLK=0, S R FF,
. , AND NAND

CLK. CLK (gate enable). 7.2 7.2(), (function table) FF.
FF
. Qn. , FF ,
S, R, (Qn+1) . , S
R 0 (S=R=0), ()
, Qn+1=Qn. (SR), S.
S R 1 (S=R=1), . . , 7.2() 7.2().
CLK .
7.1.3

FF D

RS FF
, FF D 7.3. 2 3
7.2(). , D=0, Q=0, ,
D=1, Q=1. CLK=1.
Q D
1 (CLK=1).
0, Q

99

100

7: FLIP-FLOPS

, CLK 1 0.
FF D (D latch),
(data) .

7.3
FF D ( D): () , () , ()

7.1.4

JK flip-flop

RS FF
7.2() 7.4(), . JK flipflop. RS,

1. J S
R, , , J (sets)
FF, K (resets). J=K=1 , ,
1 (CLK=1), FF ,
1 0 0 1.

7.4
Flip-flop JK: () , () , ()

7.1

7.1.5

flip-flops

JK FF . CLK=1 J=K=1 ( =1),

. , 1.
FF. .
TTL 10 ns FF 30 ns. , 1
FF,
30 ns.

. :
() JK FFs - (master-slave)
() FFs
(, edge-triggered),
.
7.1.6

FFs.
FF FF .
J, K FF JK ,
0 (Qn=0), 1
(Qn+1=1); , ,
J=K=1, FF 0 1. J=1, K=0,
1 (set), . , , J=1 K=0 K=1, FF 0 1.
(=),

101

102

7: FLIP-FLOPS

J 1 FF 0 1.
FFs / . .
7.1
FFs
JK Flip-Flop
Qn

Qn+1 J

RS Flip-Flop

D Flip-Flop

Qn

Qn+1

Qn Qn+1

T Flip-Flop
Qn Qn+1 T

FF JK . , D FF D
Qn+1 , , , 0 1, 0 1 ,
.
,
FFs .

7.2

7.2

103

NAND (7400),

OR (7402),

NOT (7404),

AND (7410),

JK flip-flop PRESET CLEAR (7476).

.
1.

S & R .

104

7: FLIP-FLOPS

2.

RS
NAND. RS, :
i.

ii.

iii.

iv.

RS
; .

3.

S & R .

7.2

4.

105

3 RS
NOR.
1;
;

5.

. Qn+1
. , CLK, CLK 0,

106

7: FLIP-FLOPS

R S CLK 1
0 ( ).

6.

Qn

Qn+1

() . flip
flop D.
().
5.

7.2

107

()

7.

Qn

()
Qn+1
D

Qn+1

() . flip flop JK.

(). 5.

()
Qn
0
0
0
0
1
1
1
1

8.

J
0
0
1
1
0
0
1
1

K
0
1
0
1
0
1
0
1

()
Qn+1

J
0
0
1
1

K
0
1
0
1

Qn+1

7476 JK flip flops CLR PRE

. (Vcc GND) , -

108

7: FLIP-FLOPS

1CLK, 1CLR 1PRE 5 V. 1J 1K

()
1Q 1Q. .
7476 .
9.

1CLR 1PRE 0 V (
);

10. 7476 .
JK flip flops D
T . D T. ; flip flop;

, :

( )
.

110

8:

8.1

(counters) FFs (). .

,
, , . , .

.
,
FF . (serial)
(ripple).
(synchronous) (parallel).
FFs ,
. ,
.
8.1.1

FFs . , FFs
,
.
2, =2n, ( ), (binary counter). 2, 2n,
. .

8.1

8.1.2

8.1() 3 bits, FFs

. FF 1.
CLK FF
(toggle). Q0, Q1, Q2 FFs. FF FF, FFs.

8.1().

8.1
(mod-8):
() , ()

FFs (, reset).
, FF0
0 1. ,
1 0. CLK.

111

112

8:

FF0 (FF1). , Q0 FF1 , FF

=1. FF,
Q1 FF.
FFs Q2Q1Q0, 8.1(), 000, 001,
010, ..., 111. 0, 1, 2, ..., 7. ,
8 (mod-8). FF0
. (LSB). Q0 2- , Q0
. ,
Q1 2- Q0 , , 4-
. , Q2
8- . , ,
Q0, Q1, Q2 2, 4 8 .
:
8.1 3 FFs 8 (mod-8).
n FFs, =2n , 0 1.
(mod-N).
FF
. , FF0 ( 1 0)
FF1, , ,
( 1 0) FF2.
FF , (ripple counters).
, FF.
8.1 , (count-up). -

8.1

,
(count-down),
8.1. Q2, Q1,
Q0 FFs, Q2, Q1, Q0.
8.2() 8.1(),
FF
. Q2, Q1, Q0 FFs. 8.2().

.

8.2
(mod-8):
() , ()

FFs .
, FF0 (toggle) 0
1. (Q0) 1
0. (FF1), Q1 0 1. , Q1

113

114

8:

1 0 (FF2), ,
, . , ,
, 000 111.
, .
8 (mod-8)
, .
8.1.3

2, =2n.
, , , . , , , 2n.

NAND . NAND
FFs, FFs.
8.1.4

FFs FFs
. .
8.1.5

2, =2n. n FFs
. 8.3()

8.1

8 (mod-8) FFs .
8.3() 8.1().

8.3
(mod-8):
() , ()

: 0=1, FF0 1 0
( ). 1=1
1 0, FF1 .
FF2, 2=1. 2=Q1T1=Q1Q0, FF2 FFs
1. Tn=Qn1...Q1Q0, Tn n- FF
Qn1, ..., Q1, Q0 FFs.
8.3() Q0

115

116

8:

(LSB) Q2 (MSB) .
8.1.6

2, 2n. .
,
, FFs JK mod-N
:
1:

n FFs, 2n1<<2n.

2:

NAND
1. G NAND.

3:

FFs 1 0
1.
G AND FF.

4:

FFs 1 1
1. G OR
FF.

8.1.7

. CLK Q2
8.1() Q2 8-
CLK, Q2 8 CLK.
, Q2 8 -

8.1

. 8.3(). , ,
mod-N .

8.1, Q0 2-
. , Q0 . , FF0
mod-2. Q1,
FF1 mod-2, CLK, Q0. FF2,
Q1. , , ,
mod-2 , mod-8,
8=222. , (
) 1, 2, ..., ,
=12 .

117

118

8:

8.2

BCD to 7 segment (7448),

flip flop JK CLEAR PRESET (7476),

(7490),

7 segment display ( ),

TTL (.. 7400, 7408, 7432,

).

.
1.

7476 ,
mod-8. LED
.

2.

.
[S] Vcc ( ) NAND;

: MSB Q3 LSB Q0.

8.2

3.

1
( 765432107...);

4.

.
;

119

120

8:

5.

.
Karnaugh ,
Ji, Ki .
.

8.2

121

(
)

Q3

Q2

Q1

Q0

Q3

Q2

Q1

Q0

J3

K3

J2

K2

J1

K1

J0

K0

03

122

8:

6.

7490 . .

8.2

;
2 3 1 6
0; 6 7
1; ( . .)
:

7.

( )
7490 ,
7448 , ,
7 (7 segment display).

123

124

8:

, :



/
/
.

-
-

126

9:

9.1

FFs
. FF 1 bit
. , n FFs n bits .
(, , )
, 1 bit
, , n bits .
(, ) . ,
,
9.1: / , / , /
/ .

.
,

. , ,
m
2m, C2m. ,
, LSB
0. , m 2m,
C2m. MSB 0.
(arithmetic shift).

9.1

9.1
: () / , () /
, () / , () /

9.1.1

FFs
D . D FFs
JK RS flip-flops .
, , FF JK
RS. RS FFs ,
R= S .
9.1.2

/
FFs D, (
) . FFs .
/ bits
9.2. (
), FF
,

127

128

9:

FF, . ,
FFs 9.2() D0 (
) 1,
FFs 4 9.2(). 9.2() 9.2() , FF JK RS .
FF,
. ,
FF . 1. J0=1
K0= J 0 =0 (S0=1 R0= S0 , , RS FF), Q0=1
Q0=0. 0, Q0 0
.

9.2
/ 4 bits : () D, () JK, () RS ()

9.1

9.1.3

/
/
Q FFs . 9.3 9.2()
/ 4 bits.

9.3
/ 4 bits

- 9.3 9.2. ,
CLEAR PRESET,
FFs (
0) (
1).
9.1.4

/ 4 bits FFs RS 9.4.

129

130

9:

9.4
/ 4 bits FFs RS

:
FFs CLK.
CLEAR , FFs.
()
E. E=1, i,
i=0, 1, 2, 3. ,
AND S0, R0 FF0. E=1
G S0 0 ( S0=I0) G 0R
I0 ( R0= I0 ). , 0=1,
FF0 1 ( S0=1 R0=0), , 0=0,

9.1

FF0 0 (S0=0 R0=1). E=0,

AND 0, Ii. ,
Si=Ri=0 , , FF .
Ii E ,

.
.
9.1.5

. n , , , n .
,
. 4 bits
9.5.

9.5
/ 4 bits

4 FFs RS . Si, Ri (i=0, 1, 2, 3) FF -

131

132

9:

AND-OR. 2 1. ,
=1, AND Di
, Si=Di Ri= Di . , Di FFi. E=0, AND
, Si=Qi1 Ri=Qi1. , Qi1
FFi1 FFi.
, , . , =1 , =0
.

.

. , , / . ,
Qi ( 9.5), .
, ,
, / , / , / , / . .
,
, . , 4 bits , 9.5, 8 bits (. 9.6).
(CLK) .
.

9.1

9.6
8 bits 4 bits

133

134

9:

9.2

flip flop D CLEAR PRESET (7474),

4 bits (74194).

.
1.

7474
+5 V (VCC) 0 V (GND).
flip flops (
) . , CLR PRE +5 V.
flip flops
4 bits. , LED.

2.

5 V . 0 V.

9.2

3.

135

, ;

4.

LED Q flip flops. 2. flip flop .

LED, . ( /
) ( / ).

5.

1000.
:

.
1 0.
LED ,
.

:
CLK
010
010
010
010

136

9:

; ;
:

6.

,
/ .
.

7.

/ ( )
: / , / , / .

8.

74194. CLK
. (
74194 .)

9.

S0 S1 +5 V. A, B,
C, D 0 1. ;
;

9.2

10. 1 ;
CLR;
:

11. S0
S1 +5 0 V . SR
1. ; ;
:

12. S1
S0 +5 0 V . SL
1. ; ;
:

137

. *

* . ,
, MSc.

.
CPU,
, , ,
/ .

, :



.

(CPU)
(state diagram)
(register)
(bus)
/ (ALU)
(instruction set)

142

10:

(instruction cycle)
(fetch)
(decode)
(execute)

10.1

10.1

(CPU) .
,
, ,
, . ,
,
, , , ,
.
,
.
,

. ,
, CPU
, ISA (Instruction Set
Architecture).
ISA (state diagram) (hardware)
. CPU , . ,
(registers) ISA, (buses), /
(ALU) .

143

144

10:

10.2

ISA CPU

ISA (Instruction Set Architecture)

.
CPU,
(instruction set).
CPU ,
, , (registers).
ISA .

10.3

10.3

CPU 8 bits , .
:
:
o
o .
:
o AND
o XOR,
.
.
(accumulator).
.
, .
,
(log28=3),
.
.
5 bits (xxxxx) ( )
. , 32 bytes (25) 8 bits.

145

146

10:

, :
10.1

Instruction Instruction Code

Operation

CLR

000

AC "00000000"

AND

001

AC AC M[AAAAA]

XOR

010

AC AC M[AAAAA]

ADD

011

AC AC + M[AAAAA]

SUB

100

AC AC M[AAAAA]

LDA

101 a

AC M[a]

110

INC

111

AC AC + 1

(3) bits , bits
CLR 000, AND 001
... , 3 bits CPU (23=8)
, (8) . ,
CPU (7)
bits 110,
/ /-. 5 bits

AND C .

10.3

.
,
, .
, . , LDA
a ( 5 bits ), , ,
(AC).

147

148

10:

10.4

ISA CPU, . ,
CPU :
5-bit (Address Register AR)
5-bit (Program Counter PC)
8-bit (Data Register DR)
3-bit (Instruction Register IR)
8-bit (Accumulator AC)
(AR)
.
5 bits, CPU. , 5 bits,
32 bytes (25),
8 bits.
O (PC)
CPU. ,
(AR), 5 bits.
O (DR)
. , ,
CPU ,

, CPU.
(IR)
opcode, 3 bits. To
. ,
(control unit),
microsequencer, CPU.
, (AC) 8-bit , M (ALU).

10.4

.
CPU register file,
.

149

150

10:

10.5

(instruction cycle)
( ): (fetch), (decode)
(execute). , CPU bits . , .

( ). . , (FETCH cycle)
(FETCH 1, FETCH 2 FETCH 3),
. ,
.

10.6

10.6

CPU , . :
(i)
.
(ii) (DR).
(iii) opcode ( 3 bits) (IR)
5 bits
(AR).
, ( FETCH 1)
.
(AR).
(PC)
,
(AR), :
FETCH 1:

AR PC

(READ) ,
(DR). ,
(PC) , , ( ) (
),
. :
FETCH 2:

DR M
PC PC + 1

151

152

10:

(FETCH 3), 8 bits, (DR), . ,
, 8 bits ,
(3) bits
(R), (5) bits (R).
FETCH 3:

IR DR[7..5]
AR DR[4..0]

, FETCH 3. 3 bits (IR)

(execution cycle)
, , n . , ,
, , .

10.7

10.7

153

(Execute Cycle)

(execution
cycle), . .
10.7.1 CLR
CLR (CLR
1) , , .
:
AC "00000000"

CLR 1:

10.7.2 ND
ND
(DR) (AC), . (AND 1)
(DR), :
AD 1:

DR M

AND (AND
2),
ALU. , (AC) ALU AND
, (AC):
AD 2:

AC AC ^ DR

10.7.3 XOR
ALU
XOR. AND,

154

10:

XOR (DR) (AC). ,

(DR):
DR M

XOR 1:

,
(DR) ALU
XOR :
XOR 2:

AC AC DR

10.7.4 ADD
ADD
. (ADD 1)

(AC). (DR), :
ADD 1:

DR M

,
(DR) LU (AC),
:
ADD 2:

AC AC + DR

10.7.5 SUB
SUB ,
(ADD, AND XOR),
. , SUB :

10.7

SUB 1:

155

DR M

(SUB 2)
(DR) ALU :
SUB 2:

AC AC - DR

10.7.6 LDA
LDA (LoaD Accumulator)
. , LDA ,
.

, . ,
FETCH 3, (R)
8-bit . , (5) bits
.
, (LDA 1)
(AR)
(DR), :
LDA 1:

DR M

(LDA 2) (5) bits (DR) (AR):

LDA 2:

AR DR[4..0]

( LDA 3),
(AR),
(AC).
(DR):
LDA 3:

DR M

156

10:

(DR) (AC), :
LDA 4:

AC DR

10.7.7 NC
INC (AC). ,
:
INC 1:

AC AC + 1

10.8 CPU

10.8

CPU

,
(state diagram) CPU.
10.1, (3) bits (IR). ,
ADD (5) (FETCH 1 
FETCH 2  FETCH 3  ADD 1  ADD 2),
.

10.1
CPU

157

158

10:

10.9

(Hardware) CPU

ISA CPU, (7)

. . CPU (hardware) .
, CPU :
() / (ALU), () , ()
() , 10.2. 8 bits.
, . ,
, ,
, ALU
, , ( ) CPU, (IR).

10.2
(block diagram) CPU

10.9 (HARDWARE) CPU

CPU.
,
(datapath) CPU, . , / (ALU),
.
(control unit) . ,
CPU,
. , CPU , .

159

A/

VHDL
ALU ( )
ALU.

, :
/ (ALU)

21
41.

/ (ALU)



21/41

162

11: A/

11.1

11.1.1 / (ALU)
/ (ALU) ,
. CPU,
(ACcumulator). ALU,
,
. , ALU ( 8 bits ), 8 bits .
CPU,
8 bits, ALU. ,

(AC), .
11.1 ALU .

11.1
ALU (BUS) (AC)

11.1

163

11.1.2 ALU (AC)

ALU
(AC), .
, ALU,
(, ,
DR LDA 4)
ALU, .

ADD 2: AC AC + DR

CLR 1: AC "00000000"

SUB 2: AC AC DR

INC 1: AC AC + 1

AND 2: AC AC DR

LDA 4: AC DR

XOR 2: AC AC DR

(7) CPU
. , (4)
AC DR ( ADD, SUB, AND XOR),
(3)
, ( CLR),
( INC) DR
( LDA).

, (DR) ALU (BUS).

164

11: A/

11.1

ADD 2
SUB 2
AND 2
XOR 2
CLR 1
INC 1
LDA 4

AC AC + DR
AC AC DR
AC AC DR
AC AC DR
AC "00000000"
AC AC + 1
AC DR

AC AC + BUS
AC AC BUS AC AC + BUS + 1
AC AC BUS
AC AC BUS
AC "00000000"
AC AC + 1
AC BUS

,
AC BUS 8 bits ALU, BUS,
1 00000000. BUS BUS
*. , 00000000,
(CLR). , 1 (SUB) (NC)
ALU ( ALUS),
, .
ALU (AC)
11.2.

11.2
/ (ALU) (AC)

() x x

x.

11.1

11.1.3 ALU

ALU : (rithmetic Unit) (Logic

Unit), 21 .
, ,
AND XOR.
. 21
8 bits, .

8 bits (carry in).
SUB INC. 1
SUB INC.
, ALU 11.3. (6) (ALUS[0..5]).
ALUS0 8
bits 00000000 ( ALUS0=0)
AC ( ALUS0=1).
ALUS1 ALUS2
BUS (ALUS1=0,
ALUS2=0), BUS (ALUS1=0, ALUS2=1), , ,
00000000 (ALUS1=1, ALUS2=0 ALUS1=1, ALUS2=1).
ALUS3 Cin .
AC BUS
0 (ALUS3=0), AC BUS
1 1 (ALUS3=1).
ALUS4
AC
(ALUS4=0) (ALUS4=1).

165

166

11: A/

, ALUS5
AC BUS. ALUS5=0
AND, ALUS5=1 XOR .

11.3
/ (ALU)

11.2
ALU (ALUS5, ALUS4, , ALUS0)
ALU AC. .
, XOR 8-bit
( 11.3) ALUS5, XOR (Logic Unit),
ALUS4, ALU . ,
ALU , , ,
.

11.1

167

11.2
ALU
A

ADD

AC AC + BUS

SUB

AC AC + BUS + 1

AND

AC AC BUS

XOR

AC AC BUS

CLR

AC "00000000"

INC

AC AC + 1

LDA

AC BUS

168

11: A/

11.2
1.

VHDL 1 bit.

.
.

2.

(component)
1 bit, VHDL
8 bits . E

00010010 10010100.
.

11.2

3.

VHDL 2x1 8 bits.

(2) 8 bits.
.

4.

VHDL 4x1 8 bits.

(4) 8 bits.

. .

169

170

11: A/

5.

(components) 2x1 4x1 8 bits 8 bits,

VHDL
ALU 11.3.
( entity) AC_signal BUS_signal
( AC BUS) 8 bits,
ALU_out 8-bits, (6) ALUS0,
ALUS1,..., ALUS5. T 00000000 BUS
ALU
( signal). .

6.

(AC_signal BUS_signal) 10110001 00011001 ,

(7) .

11.2

7.

171

ADD

ALU_out AC + BUS

SUB

ALU_out AC BUS

AND

ALU_out AC BUS

XOR

ALU_out AC BUS

CLR

ALU_out "00000000"

INC

ALU_out AC + 1

LDA

ALU_out BUS

(ALU_out)

ALU, (7) (ALUS) 11.2. 0

().

, ALU.

172

11: A/

8.

(Logic Unit)
( 8 ) OR
(AC) ALU
(BUS). ALU VHDL
OR
ALU;
.

(datapath) .
,
. , , /
.

, VHDL
CPU.

(datapath)
(register file)
(bus)
(buffers)

174

12:

12.1

:
(datapath unit) (control unit).
CPU.
, . , ,
(hardware) : () (register file), ()
(functional units), /
(ALU), () (bus) (buffers),
CPU. ,
, .
ALU ,

. , .
CPU ( datapath)
() ,
. ,
12.1 .
12.1

FETCH 1
FETCH 2
FETCH 3

AR  PC
DR  M
PC  PC + 1
IR  DR[7:5]
AR  DR[4:0]

LDA 1
LDA 2
LDA 3
LDA 4

DR  M
AR  DR[4:0]
DR  M
AC  DR

12.1

175

AND 1
AND 2
XOR 1

DR  M
AC  AC ^ DR
DR  M

ADD 1
ADD 2
SUB 1

DR  M
AC  AC + DR
DR  M

XOR 2

AC  AC DR

SUB 2

AC  AC DR

CLR 1
INC 1

AC  0
AC  AC + 1

, CPU (ISA), (bus) 8 bits,

CPU (5):
5-bit (Address Register AR)
5-bit (Program Counter PC)
8-bit (Data Register DR)
3-bit (Instruction Register IR)
8-bit (Accumulator AC)

CPU 12.1,
8 bits
:
(PC), (DR) (C).
, FETCH 1
AR  PC,
(AR) . , FETCH 3, LDA 2, LDA 4, AND 2, XOR 2, ADD 2 SUB 2 (DR)
( ),
R R (AC).
(AC),
ALU. ,
, -

176

12:

( ) ( DR  M).
, (4)
CPU, (buffers). ,
. ,

. bit,
1,
, .
, bit 0,
(Hi-z). , ,
CPU.


12.1.

12.1
(buffers)

, PCBUS 1,
(PC) . ,

12.1

(DRBUS,
ACBUS MEMBUS) 0.
,
. ,
. AR PC 5 bits (5) bits ,
IR (3) bits. (AC),
ALU, .
CPU, (datapath), , , 12.1. , (LOAD). , ,
(.. AR)
(LOAD). , , (5)
: ARLOAD, PCLOAD, DRLOAD, ACLOAD IRLOAD. ,
(PCINC), PC  PC + 1,
FETCH 2. (6) ALU (ALUS0, ALUS1, , ALUS5),
(4)
(PCBUS, DRBUS, ACBUS MEMBUS), .
( READ). VHDL , , ,
CPU.
CPU,
, 12.2.

177

178

12:

12.2
(datapath) CPU

12.2

12.2
1.

VHDL
(AR) 5 bits.
(reset) 1,
(ARLOAD) . ,
.
(reset) (clock),
CPU. CPU (reset)
1 , (..
)
(clock).

2.

(AR), -

179

180

12:

. 5 bits

(clock), (reset)
(ARLOAD), . .

3.

VHDL
(PC) 5 bits.
, (reset) (PCLOAD), (PCINC). CPU, .

12.2

4.

(PC), 5-bit

(clock), (reset), (PCLOAD) (PCINC) .

.
.

181

182

12:

5.

VHDL
(DR) 8 bits , (reset) (DRLOAD).

6.

(DR), . 8 bits
(clock), (reset) (DRLOAD)
(AR), .
.

12.2

7.

VHDL (AC) 8
bits. , (AC)
(DR), 8 bits, , (reset) (load), CPU VHDL,
(C DR).

183

184

12:

8.

VHDL (IR)
, , 3 bits.
(reset)
(IRLOAD).

9.

(IR), (AR).
, .

12.2

10. 12.2,
CPU (datapath), VHDL ,

(buffers). VHDL
CASE, 4 bits,
bit
(ACBUS, DRBUS, PCBUS MEMBUS). ,
4 bits,
. ,
1000, ACBUS 1 bit ,
(AC).
0100, 0010 0001.
4 bits 00000000, 8 bits.

185

,
,
VHDL:


microsequencer.

Microsequencer
(microprogrammed)


(microprogram)

188

13:

13.1

13.1.1
(control
unit), . ,
.
(microprogrammed) , microsequencer.
13.1.2
CPU.
, (16):
: ARLOAD, PCLOAD, DRLOAD, ACLOAD, IRLOAD
: PCINC
ALU: ALUS0, ALUS1, LUS2, ALUS3, ALUS4, ALUS5
: PCBUS, DRBUS, ACBUS, MEMBUS
16 bits,
mOPs (microoperations) (microinstruction). , (state
diagram) CPU, ,
.
(mOPs), , , (microinstruction), . (microinstruction) ,
13.1. mOPs 16
22 bits . 5 bits

13.1

(ADDR),
.

13.1
(microinstruction)

(ADDR) ,
. , , (..
FETCH 1, FETCH 2, ... .) 22 bits (mOPs).
,
(microcode memory), . ,
. . , CPU (17) (. 10.1), 5 bits (log 2 17 = 4,087... 5 bits)
(address). , 25=32 , -

22 bits . 32 , , 17 , CPU. ,
FETCH 1 00001, FETCH 2 00010 ...
, (microcode) ,
, (microprogram) CPU, .
, (5) bits (
ADDR)
. , , ,
FETCH 1 0000000100000000000010,
-

189

190

13:

00010 . .
, bit (SEL) microsequencer. , ADDR
mapping (mapping logic)
.
microsequencer SEL (mOPs ADDR) .
13.1.3 microsequencer

.
microsequencer ( 13.2),
.

13.2
microsequencer

13.1

microsequencer : 21 5
bits, 5 bits (microcode memory), -

. microsequencer , ,
16 bits
(mOPs) , bit
CPU. , SEL ADDR, bits , microsequencer
.

, , CPU,
. , , (mOPs) ,
.
CPU (17) ,
,
.
5 bits (), 32 . , 3222 bits.
,
microsequencer . ,
. 5 bits
, ,
.
13.2, : ADDR
mapping , 5 bits .
21
, (SEL). FETCH 3, SEL
0, 5 bits

191

192

13:

( ADDR). FETCH 3

(7) . , , (IR). ,
SEL 1,
mapping .

13.3
mapping

mapping , 13.3,
3 bits (R) 00,
5 bits.
FETCH 3 5 bits, ADDR. ,
CPU, (
LDA).
LDA ( IR) 2 bits (00, 01, 10 11). LDA IR=101, 5 bits
. , LDA 1 10100 ,
LDA 2 10101
. , FETCH 3

microsequencer

13.1

. , ,
LDA, IR=101 SEL=1 FETCH 3,
mapping
10100, LDA 1. 10100 , bits
(mOPs)
microsequencer.
13.1.4

microsequencer,
,
. ,
(microprogram)

microsequencer , ,
, CPU.
, ,
, 13.1 .

193

194

13:

13.1
CPU

, 00001, 00010 00011 (fetch cycle) ,

. , ADDR .
, FETCH 1,
00010, FETCH 2. FETCH 2, , -

13.1

13.1,
00011,
FETCH 3. SEL 1,

mapping . , (5)
bits FETCH 3
(), . , 13.1 , (0 1).

(FETCH 1-3) 1 3 ( 00001 00011), 0 2.
mapping FETCH 3. ,
FETCH 3 IR2IR1IR000. ,
(7) CPU, 1
(2) bits 00. , CLR, (CLR 1),
00000, IR=000 CLR. , (3) bits
000,
CLR (00001, 00010 00011). ,
INC (C 1), (11101, 11110 11111) , , (FETCH cycle).

ADDR 00001. ,
CPU
(fetch-decode-execute) FETCH 1, .

195

196

13:

, .

mOPs .
(fetch cycle)
FETCH 1, AR PC,
(PC)
(AR). ,
PCBUS ( PCBUS = 1), (PC) .
, ARLOAD ( ARLOAD = 1), (AR)
(. 13.4).

13.4
FETCH 1

FETCH 2 .
( DR ),
(AR). ,
READ MEMBUS 12.2, , ,
, , . READ
CPU VHDL,
. ,
, mOPs,

13.1

13.1. , DRLOAD,
(DR).
( PC PC + 1),
PCINC (. 13.5).

13.5
FETCH 2

FETCH 3,
(DR)
(IR) (AR), IR
DR[7..5] AR DR[4..0]. ,
DRBUS,
, ARLOAD
IRLOAD, . , SEL 1
mapping (. 13.6).

13.6
FETCH 3

197

198

13:

,
(7) .
, , ADD,
8-bit . , (2) (ADD 1 ADD 2).
ADD 1 DR M,
(DR). , MEMBUS, , DRLOAD, (DR) (. 13.7).

13.7
ADD 1

ADD 2 AC C + DR,
(AC) (DR), .
ALU,
0,
(ALUS5) ,
, 0 ALUS4, (. 13.8).

13.1

13.8
ADD 2

199

200

13:

13.2
1.

VHDL 21 5 bits.
, 5 bits.

2.

VHDL
5 bits,
(reset).
, , .

13.2

3.

VHDL (microcode memory), .mif . 32 ,

5 bits.
(width) 22 bits, 1 bit
SEL, 16 bits
(mOPs) 5 bits
ADDR. 13.1, , 0 bits
(). microcode.mif.

depth = 32;
-- 5-bit address ---> 0-31 dec
width = 22;
-- 22-bit data
address_radix = bin;
data_radix = bin;
content
begin
00001 : 0000000100000100000010 ; -- FETCH 1
end;

201

202

13:

4.

VHDL
lpm_rom. A
lpm_file microcode.mif
lpm_widthad
lpm_width. FLEX10K ( Assign  Device
MAX+plus II).

5.

, , 13.1,
.
.

13.2

6.

(components)
21 5 bits, 5 bits ,
VHDL
microsequencer (. ). IR_signal, , mOPs,
, (reset) (clock).
(
component) (
signal), .
PROCESS, BEGIN
ARCHITECTURE. SEQ_out ( signal) 22 bits ( ), SEL, mOPs
ADDR. , IRMAP mapping
, . ,
port map .
p1: PROCESS (clock, reset)
BEGIN
IF reset = '1' THEN
SEL_MUX <= '0' ;
ADDR_MUX <= "00000";
ELSE
SEL_MUX <= SEL ;
ADDR_MUX <= ADDR ;
END IF;
END PROCESS ;

203

204

13:

microsequencer

13.2

7.

microsequencer .
( 1) (reset) 100 nsec, 200
nsec .
( ), mOPs - (7) , CPU
( 10.1). , mOPs (hex)
. .

205

CPU

CPU. ,
CPU ( , ) CPU.

,
,
VHDL:

CPU.

208

14: CPU

14.1

14.1.1
CPU,
ALU, , .
VHDL ,
CPU.
VHDL
. ,
, , .
14.1.2
CPU ,
( )
. .
VHDL
.mif .
external_mem.mif 32
, 8 bits . ( 8 bits),
, (hex)
CPU, .

depth = 32;
-- 5-bit address ---> 0-31 dec
width = 8;
-- 8-bit data
address_radix = bin;
data_radix = hex;
content
begin
00000 :
00001 :
00010 :

B1 ;
78 ;
32 ;

14.1

00011
00100
00101
00110

:
:
:
:

F3
53
96
1B

;
;
;
;

10001
10010
10011
10100
10110
11000
end;

:
:
:
:
:
:

54
AF
ED
17
D3
81

;
;
;
;
;
;

14.1, CPU .
,
. , 14.1 (mOPs)
(hex).
CPU mOPs .
, FETCH 1
LDA (PC) (AR) AR  PC.
( FETCH 2) 00000
(AR), (1
hex ) (DR). , (PC) ,
PC  PC+1, ..., ... , (7) CPU.

209

210

14: CPU

14.1

CPU
State

LDA

ADD

AND

INC

XOR

SUB

CLR

FETCH
FETCH
FETCH
LDA 1
LDA 2
LDA 3
LDA 4
FETCH
FETCH
FETCH
ADD 1
ADD 2
FETCH
FETCH
FETCH
AND 1
AND 2
FETCH
FETCH
FETCH
INC 1
FETCH
FETCH
FETCH
XOR 1
XOR 2
FETCH
FETCH
FETCH
SUB 1
SUB 2
FETCH
FETCH
FETCH
CLR 1

1
2
3

1
2
3

1
2
3

1
2
3
1
2
3

1
2
3

1
2
3

AR
PC
DR
AC
IR
mOPs
(bin) (bin) (hex) (hex) (bin) (hex)
00000
00000
10001
10001
10100
10100
10100
00001
00001
11000
11000
11000
00010
00010
10010
10010
10010
00011
00011
10011
10011
00100
00100
10011
10011
10011
00101
00101
10110
10110
10110
00110
00110
11011
11011

00000
00001
00001
00001
00001
00001
00001
00001
00010
00010
00010
00010
00010
00011
00011
00011
00011
00011
00100
00100
00100
00100
00101
00101
00101
00101
00101
00110
00110
00110
00110
00110
00111
00111
00111

00
B1
B1
54
54
17
17
17
78
78
81
81
81
32
32
AF
AF
AF
F3
F3
F3
F3
53
53
ED
ED
ED
96
96
D3
D3
D3
1B
1B
1B

00
00
00
00
00
00
17
17
17
17
17
98
98
98
98
98
88
88
88
88
89
89
89
89
89
64
64
64
64
64
91
91
91
91
00

000
000
101
101
101
101
101
101
101
011
011
011
011
011
001
001
001
001
001
111
111
111
111
010
010
010
010
010
100
100
100
100
100
000
000

0208
00C1
0214
0041
0204
0041
0424
0208
00C1
0214
0041
0024
0208
00C1
0214
0041
4024
0208
00C1
0214
3822
0208
00C1
0214
0041
C024
0208
00C1
0214
0041
2824
0208
00C1
0214
1C20

14.2

14.2
1.

VHDL
lpm_rom, lpm_file external_mem.mif.

2.

CPU VHDL
: () (5) (AR, PC, DR, AC IR),
() LU, () , () microsequencer,
, () .
( component)
( 16 , , , ARLOAD, LUS_0, DRBUS, ... .) ( signal). mOP (
16 bits) bit ( 13.1)
[.. MEMBUS <= mOP(0);]. (
for generate ) R, PC
IR, . ,

211

212

14: CPU

port map
(components),
CPU.
IR_signal
microsequencer,
(IR) , , .
CPU, ( entity) ,
,
clock reset. , CPU
(.. mOPs) mOP,
, 14.1,
.

3.

CPU.
200 nsec ,
100 nsec (reset).
CPU,

14.2

. , , FETCH 2
(mOPs) 00C1 (hex),
PC  PC+1 DR  . , mOPs
0214 (hex), FETCH 3. CPU , ( 14.1).

213

.
, MSc, PhD

.
/ & , MSc

. .
.

, :




.

218

15:

15.1

,
.
. , ,
.
,
.
,
. ,
, , -
(keywords), , . , .
,
.
:

15.2

15.2

(instruction)
, , , .
(instruction cycle). (instruction set).
: 8085
10000000 ( 8 bits)
(fetch) . . ,
00111110 :
.

.

219

220

15:

15.3

, . , . ,
, .
,
, ,
, , . ,
.
(),
()
.
, . (object program). ,
.
, ,
( bit) (
).
, ,
,
.

, -

15.3

. , (addition) ,
ADD (
addition).
(assembly).
.

221

222

15:

15.4

, . :

. , .
:

,
. ,

.

15.4

,
( )
.
, ,
,
.
:
/
. .
.
.

.


.

, .

.
.
, .

223

224

15:

,
.
, .
, ,
, .
,
.
.
( )
( ). .
, ,
.
, , (executable program). . ,
. (debugging) . (debuggers), .
(step-bystep) . ,
, . ,
.
,

. -

15.4

,
.
(breakpoints). ,
,
, , ,

.

225

226

15:

15.5

:
1.

(fetching) ,
.

2.

(decoding) .

3.

( bytes).

4.

(execution) .

8085,
, , .
,
8085, , , , .

,
:
8085
8085





()

, .

228

16:

8085

(editor)

16.1

16.1

16.1.1
8085
(register array) .
(), 8085, , , .
, 8085
:

8 bits (B, C, D, E, H L),

(Program Counter PC) 16 bits,

(Stack Pointer SP) 16 bits,

(Accumulator A) 8 bits

(Flags F).

(PC) (16 bits) . 8085

216=65536 . , PC
(
).

229

230

16:

(SP) . . , SP
.
.
(8 bits) 8 bits, B,
C, D, E, H L, 16 bits.
: BC, DE HL.
8085 16 bits.
/ (ALU) 8085 (
) .
8-bit (), , 8-bit (TeMporary Register TMR),
. /
(ALU) ,

.
16.1.2 8085
8085 1 3 bytes. byte
(operation code opcode),
. opcode (CPU)
bytes , ,
.
(instruction fetch), byte
,
.
PC. bytes,
bytes . ,
, , 1 byte, PC 1,

16.1

. 1 byte,
bytes .
, I/O, .
, I/O .

BC, DE HL. .
,
.
. , ,
. (clock cycle)
.
.
, - .
(instruction cycle). ,
(machines cycles) -
(.. ). ,
.
,
/ .
8085 :

231

232

16:

8085 .
16.1.3 8085
(addressing modes) (memory access).
(effective address).

.
8085 :

(Immediate addressing), .
,
(fetch) . :
MVI B,30H

LXI H,4000H

(Direct addressing),

. ,

. :
LDA 1FFFH

(Register addressing), /

16.1

233

. , . :
MOV B,D

ADD C

(Register Indirect addressing),

.
HL. , MOV A,M
HL.

(Implied addressing).
. , . :
CMA

SIM

234

16:

16.2
1.

8085:

MVI H,20H

LXI H,2010H

LXI H,2010H

MVI L,01H

MOV B,M

LDA 2001H

MOV B,M

LDAX B

STA 2010H

MOV D,B

1:

MVI H,20H
MVI L,01H

MOV B,M
MOV D,B
LXI H,2001H
MOV B,M

LDAX B
LXI H,2001H
LDA 2001H
STA 2002H

16.2

235

2:
;
.

3: 2001 ,
; .

Hex

Hex

Hex

Hex

Hex

Hex

Hex

2.

8085
:
i.

B 20H.

ii.

D 10010.

iii. D H.
iv.

44H C E 3 bytes .

236

16:

1: .

2: ;

3:
;

16.2

237

4: ;
,
.

Hex

Hex

Hex

Hex

Hex

Hex

Hex

5: flags () ; , , .

3.

AC

CY

8085
3000 ,

238

16:

, 3001.
1: . progr_1.85.
2:
.

3:

;

4: 3000 .
.

16.2

239

5: (compile program) ,
,
Compiled successfully.
6: (run program) ,
, Execution
finished .
7: , , PC
3000 3001 .

PC

3000

3001

Hex

Hex

Hex

Hex

Hex

8: ;

9: ;

10: 1000
1007. ;

11:
.

, ,
(loop) (branch),
.

, :


(loops)
(branch).

(labels)

242

17:

17.1

, .

. .

(PC Program Counter). , PC .
. , PC
.
( )
. ,
, .
.
(conditional jumps)
(unconditional jumps).
. :
17.1

NZ

, Z=0

, Z=1

NC

, CY=0

, CY=1

PO

, P=0

17.1

243

PE

, P=1

, S=0

, S=1

()
. , JNZ 200
200 0. , . , JMP 300
300 .
, , , PC (
offset).
assembly,
.
, (label) .
.
offset
. ,
.
, .
. (flags) -

244

17:

,
.
,
. - . :
:
MVI C,9H
loop: 1
2
DCR C
JNZ loop
:
MVI C,9H C 9.
(,
, ). DCR C C . ,
loop JNZ loop. ,
1 2 9 .

17.2

17.2
1.

2000
2020 FF.
1: .

2:
.

2.

20 ,
2000 2013 .
, 0. 3000 (), 3001 ()
3002 ().

245

246

17:

: DVD .
.
1: .

2:
.

3.

. 2001 2000.

17.2

3001 .
:

DVD
.
.
(
).
,
( ). , . ,
, .

1: .

2:
.
.

247

248

17:

2001

2A

3001

2002

1C

3002

2003

78

3003

2004

09

3004

2005

F3

3005

2006

29

3006

2007

D2

3007

2008

C4

3008

2009

4F

3009

200

9B

300

3: ; 1;

4: T-states ;
T-states
. .

17.2

249

T-states

5
10
15
20

:.

8085
8085
.

,
:


8085

8085.

252

18:

18.1

18.1

253

/ (ALU). ,
.
( flags), : S
(Sign) , Z (Zero) , AC (Auxiliary
Carry) , P (Parity) CY (CarrY)
.
. ,
,
( S) 1, , , 0. (P), 1
, , , 0.
(AC) ( BCD
), byte BCD (
4 ).
4 bits ( BCD ) , 5bit.
AC. CY , ,
, , .
18.1
8085
S

AC

CY

,
.

254

18:

18.2

= 1

bit
.

( ).

AC

( ) bit
bit .

CY

,
.

bits .
,
(
JMP).

18.2

18.2
1.

8085

3000 3001 3002.
1:

2:

255

256

18:

3:

3000

3001

3002

Hex

Hex

Hex

01

02

8F

83

23

32

7F

87

4:

Flags

Hex

3002
(flags).

5:

2.

BCD 8 , 3002.
3001.

18.2

3000.
8 3000 0. () 17, 21, 06, 31, 24 () 39, 25, 07, 49.
1:

2:

257

258

18:

3:

4:

;
,
.

Hex

Hex

Hex

Hex

Hex

Hex

Hex

5:

bits ()
,
.

18.2

3.

259

AC

CY

16 , 3004.
24 .
3003.
3000-3002. . , MSB
3002, LSB 3000.
, MSB 3005,
LSB 3004.

260

18:

1:

2:

3:

.
,
.

18.2

4:

4.

261

8085 .
8
3000 3001.
16
3002 (LSB) 3003 (MSB).
, (.. 3x5=3+3+3+3+3).
1:

262

18:

2:

3:

18.2

263

3000

3001

3003

3002

Hex

Hex

Hex

Hex

10

A2

9F

43

73

B2

7F

C7

4:

T-states

5:

4.

5.

8085 .

8 3000 3001.
8 3002
() 3003 (). , .
..: 18:5-> 18-5=13

=1

13-5=8

=2

8-5=3

=3 =3, 3<5,

1:

264

18:

2:

18.2

3:

265

3000

3001

3002

3003

Hex

Hex

Hex

Hex

A2

10

9F

03

73

B2

7F

17

T-states

,
.

,
:



Booth.

 19: /

268

19.1

19.1.1
.

,

.
8085 :
ANA r

r.

ANA M

HL.

AN byte

byte.

XRA r

r.

XRA M

HL.

XR byte

byte.

ORA r

r.

ORA M

HL.

OR byte

byte.

CMP r

r.

CMP M

HL.

CMP byte

byte.

19.1

269

RLC

RRC

RAL

RAR

CMA

CMC

STC

1 .

19.1.2 /

.
,
, ,
.
bit 0. , 2, , ,
2.

 19: /

270

, , .

1

19.1

271

19.1.3
:
1

1
2
3
+

. . 1, , , 0, . ,
. .
.
n m ,
n+m .
19.1.4 Booth
Booth
. .
. ,
.

 19: /

272

,
, :
)

1.

0
( 1).

:
-13 -9 ( +117).
( 5 ) 10011 10111 .

MR: 10011 ()

MD: 10111 ()

MD+1: 01001 ( )

A: 00000 ()

MRL: LSB

MRL-1: . 0.

MR,
. , MRL-1 MR . , bit .
.
:

19.1

MR,
0001110101=11710.

273

 19: /

274

19.2
1.

0A 3000H, -
3002H.
1:
.

2:

.

AC

CY

19.2

3: ;
;

2.

L .
3000H
.
3002H.

3.

. 3002 F4.
1:

275

 19: /

276

2:

bits ()
,
.

3:

AC

CY

; ;

4.

8
3000 8
3001,
16 3002 (LSB), 3003 (MSB).
16 bits, byte 0.
.
1:

19.2

2:

277

3:

Tstates:

(3000)

(3001)

(3003-3002)

FF

01

67

7C

FF

00

FF

FF

T-states

 19: /

278

5.

16 bits 3000-3001 16 bits 30023003, 3004-3005 (), 30063007 ().
1:

2:

19.2

3:

279

(3001-3000)

(3003-3002)

(3005-3004)

(3007-3006)

CDEF

AB01

FE67

0065

0167

027C

340F

0001

12FF

0000

4:

;
,
;

6.

Booth 8 .
3000 3001 . 16
3002 (LSB) 3003 (MSB). .

 19: /

280

1:

19.2

2:

281

states.

(3000)

(3001)

(3003-3002)

FF

01

67

7C

FF

00

FF

FF

T-states

. , ,
, .

, :
(stack)

(stack register)

.

(stack)


(stack register)

284

20:

20.1

20.1.1
. LIFO (Last In First Out).

. ,

.
,

. ,
(stack register) , , ,
. ( SP,
stack pointer) .
PUSH, POP.
.

.
PUSH

.
FFEF

FFF0

20.1
PUSH POP

POP

20.1

285

.
, .
PUSH
POP. :
.
.
.
PUSH H
PUSH B
POP B
POP H
.
.
.

BC DE, POP ,
. , , PUSH POP.
, SP=3010H, BC=1234H
DE=5678H (= ).

PUSH

PUSH

POP

POP

78

XX

XX

XX

56

XX

XX

34

34

34

XX

XX

12

12

12

XX

XX

XX

XX

XX SP XX

300C

XX

XX

300D

XX

300E

XX

300F
3010

SP

SP

SP

SP

286

20:

POP . . POP
.
SP. , PUSH .
20.1.2
,
, ,
.
. .
,

.
(call) .
(label) .
,
. , , , PUSH . .
CALL.
RET . POP PC,
, .
. , , , PUSH
POP , ,
,
PUSH
.

20.1

,
.
, , , . PUSH , ,
POP ( )
.
,
.

, . CALL RET. .

C<> , , ,
,
.
.

.
,
.

.
20.1.3
, , .
PUSH . , ,

287

288

20:

POP ( PUSH ) POP. RET

PUSH
, .
.

...
PUSH D

; DE

PUSH H

; HL

CALL SUB_A

; SUB_A

SUBA:
POP H

; PC HL

POP B

; HL BC

POP D

; DE

PUSH H

; PC

RET

20.1.4 postfix reverse polish

()
() . infix.

20.1

289

,
.
postfix reverse polish , .. + , + .

. infix postfix.
= + ( + CD) .
= + ( + CD) =
= + ( + CD) =
= + (CD+) =
= + CD+ =
= CD++ =
= CD++ =
= CD++ ( )
postfix notation.

.
. ( ):
1.
2.

1
- . , PUSH
. , POP ,
.

3.
4.

+1
= bytes , .
. ,
2.

290

20:

, , , + C,
postfix notation A B C +, :
PUSH A
PUSH B
PUSH C
MUL
ADD

MUL POP (B C), B x C

. , ADD
POP (A B C),
() + B C .

20.2

20.2
1.

291

HL,
DE BC 1234, 5678 9ABC SP
3010. .
1:

2:

H, L, D, E, B, C SP .

SP

Hex

Hex

Hex

Hex

Hex

Hex

Hex

292

20:

3:

2.

5 (byte)
3000.
3000 00 5 .
1:

5
(byte) 3000.

20.2

2:

3000
00 5 .

3.

16 ,
8- 3000-3001.
1:

293

294

20:

2:

3:

-1
3003 N 3002. , : 1 2,
2 3, ..., -1 . 2000. :
.

20.2

4.

, 8085 20.1.4. postfix (

3001, 3000H) .
,
, . 8 .
: 8085
16 .
PUSH byte , .. B, C
PUSH .
1:

ADDS, SUBS MULS

,
(
).
. : ,
.

295

296

20:

2:

postfix . 3001H,
3000H. ,
PUSH , , .
.

3:

. .

3000

08

0B

0E

3001

1F

2F

2D

3002

00

00

00

3003

05

0A

2E

3004

00

00

00

3005

0C

2C

30

3006

00

00

00

3007

20

0B

3008

00

00

3009

02

300A

00

20.2

300B

297

300C

300D

300E

4:

infix .

,
:


8085 .

300

21: /

21.1

21.1.1 /

. , ,
, , , , .
( bytes), .
(consequtive), , ,

. , ,
. .

. :
, .
,
1.
( )
1 .
, , ,
.
.
, , (.. ), ,
.

21.1

. , () .
,

() 1.
, ,
. ,
.
21.1.2 (bubble-sort)
bubble-sort ,
.
bubble-sort . :
. , . ,
, , .
. ,

2, 3 ...,
, .
21.1.3 (binary search)
, .
Xi. :
.

301

302

21: /

(+)/2

Y=X, . .

Y>X, .

. ,
. , ,
.
,
.

21.2

21.2
1.

.
,
. 2001 3001
,
2000 3000 .

1:

2:

2.

.
3003 3004.

303

304

21: /

3000

3001H (LSB) - 3002H (MSB).
1:

2:

21.2

3:

305

.
.

3000

34

11

25

21

3003

0A

0B

0C

0D

3004

08

08

08

08

3005

0C

0C

0C

0C

3006

11

11

11

11

3007

16

16

16

16

3008

20

20

20

20

3009

21

21

21

21

300A

25

25

25

25

300B

28

28

28

28

300C

34

34

34

34

300D

4F

4F

4F

4F

5B

5B

5B

7C

7C

3001
3002

300E
300F
3010

4:

FA

T-states
;

T-states

3.

3000H,
. 3001H.

306

21: /

3002H.
1.
1:

2:

3:

.
.

21.2

307

308

21: /

4.

bubble-sort.
.
1:

2:

3:

21.2

4:

309

bubble-sort

;

FF

01

5:

11

43

22

67

54

AC

5A

23

FF

01

11

43

22

67

54

AC

5A

23

1
2

6:

bubblesort; . ,
.



(data sheets)

7400
NAND
2

Y = (A B)

7402
NOR 2

314

Y = (A + B)

7404
NOT

= A

7408
AND 2

=AB

DATA SHEETS

7410
NAND
3

= (A B C)

7420
NAND
4

=(A B C D)

315

316

7432
OR 2

Y=A+B

DATA SHEETS

7448

BCD 7-segment
display

317

318

DATA SHEETS

319

7474
D Flip-flop
positive edge
triggered.

7476
JK Flip-flop

320

7483

DATA SHEETS

7486
XOR 2

Y=AB

321

322

7490

DATA SHEETS

74138
38

18

*G2 = G2A +G2B

74151

81

323

324

74194

4 bits


VHDL

.1

VHDL (hardware) .
VHSIC Hardware Description Language, VHSIC ,
, Very High-Speed Integrated Circuits ( ).
IBM, Texas Instruments Intermetrics
1983. 1987 (
std 1076-1987 ),
1993, ( std 1164-1993 ).
VHDL .

. , ,
,
VHDL. VHDL
(, ,
MAX+plus II) ,
.
, , :
VHDL . , , constructs VHDL .

326

VHDL ,
,
.
, VHDL ,
(object-oriented) .
VHDL
hardware . :
VHDL
VHDL
(behavioral, structural dataflow)
VHDL , .
VHDL . (features), .
,
.

 VHDL

.2

VHDL

VHDL
.
.1.

.1
XOR VHDL

XOR
VHDL. , ,
(libraries) .
(entity). , ( ).
(rchitecture) .
,
(behavioral, structural
dataflow), .6.

327

328

.3

VHDL

VHDL
(entity) *.vhd.
VHDL, .2. , XOR, (xor_gate)
, . ,
XOR xor_gate.vhd.

.2
xor_gate.vhd

, xor_arc, ,
.

 VHDL

.4

VHDL

.4.1 (comments)
VHDL (--). (compiler) ,
, :
-- this is a VHDL comment

.4.2 (data objects)

VHDL: () (constants),
() (variables) () (signals).
(constant)
.
CONSTANT _ : _ := _ ;

:
CONSTANT high : std_logic := '1' ;

, (variable) ,
, , . ,
.
VARIABLE _ : _ {:=
_} ;

:
VARIABLE count : std_logic_vector (2 downto 0) ;

(signal) VHDL . ,
.
.

329

330

signal _ : _ ;

:
signal y : std_logic ;

, (.. )
(.. ).
bit bits. VHDL bit
(1 0),
bits (.. 10010).
VHDL
. , , (compiler)
VHDL : CONSTANT,
constant Constant.
.4.3 (data types)
VHDL , ,
. STD_LOGIC STD_LOGIC_VECTOR,
SIGNED UNSIGNED, BIT BIT_VECTOR INTEGER.
BOOLEAN, Enumeration
TYPE, ARRAY SUBTYPE, , .
.4.3.1 STD_LOGIC STD_LOGIC_VECTOR
std_logic std_logic_vector,
bit,
bits. IEEE
Std 1164-1993 , ,
,
IEEE.std_logic_1164.
std_logic ,
MAX+plus II Altera (4):

 VHDL

331

0 ( ), 1 ( ), Z ( ) X
( ).
std_logic_vector,
bits (.. 01101, , , ...
.). N bits
:
std_logic_vector (N-1 downto 0);
std_logic_vector (1 to N);

:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

SIGNAL A : std_logic ;
SIGNAL B : std_logic_vector(4 downto 0) ;

A <= '0' ;
B <= "10100" ;

-- 1-bit signal
-- 5-bits signal

.4.3.2 SIGNED UNSIGNED

std_logic
std_logic_vector, , , . , IEEE.std_logic_signed, std_logic
std_logic_vector ,
, , IEEE.std_logic_unsigned, . IEEE.std_logic_arith, , (.. +). ,
(unsigned) +
IEEE.std_logic_unsigned.

332

:
LIBRARY ieee;
USE ieee.std_logic_unsigned.all;

SIGNAL A, B
: std_logic_vector(3 downto 0);
signal
SIGNAL result : std_logic_vector(3 downto 0);
signal

result <= A + B ;

-- 4-bits
-- 4-bits

.4.3.3 INTEGER
integer (default) 32 bits!
range, .
GERrange _ to _ ;

127
+127, 8 bits,
cnt 8 bits.
SIGNAL Y : INTEGER RANGE -127 TO 127;
VARIABLE cnt : INTEGER RANGE 0 TO 255;

.4.3.4 BIT BIT_VECTOR

bit bit_vector VHDL ( IEEE),

. 0
1 ( bit) bits,
bit 0 1 ( bits ).
SIGNAL f : BIT ;
SIGNAL w1 : BIT_VECTOR(3 downto 0) ;

f <= '1' ;
w1 <= "1100" ;

-- 1-bit signal
-- 4-bits signal

 VHDL

333

.4.4 (operators)
VHDL ,
(5) : () (logical), () (arithmetic),
() (relational), () (shift) () (concatenation).
MAX+plus II,
. (
MAX+plus II) .1.
.1
VHDL

AND, NAND, OR, NOR, XOR, NOT

+, -, *

<, <=, >, >=, =, /=

&

(AND, OR, XOR, ...

.),
. , (+, , *) . , ,
IEEE.std_logic_signed
IEEE.std_logic_unsigned, (signed) (unsigned) .
(<, <=, >, ... .).
<=, ,
,
.
, VHDL. -

334

<= , = C/C++, =
==.
&,
. , &
(110) (001) f ( f <= A & B)
110001, .
SIGNAL , B: std_logic_vector(2 DOWNTO 0);
SIGNAL f
: std_logic_vector(5 DOWNTO 0);
SIGNAL S, Y: std_logic_vector(2 DOWNTO 0);

A <= "110" ;
B <= "001" ;

f <= A & B;
-- f = "110001"
S <= A + B;
-- S = "111"
Y <= A AND B; -- Y = "000"

 VHDL

.5

335

VHDL

.5.1
VHDL
(libraries) . ,
,
.
Altera MAX+plus II , : ieee, lpm altera.

MAX+plus II,

\maxplus2\vhdlxx , xx 87 93.
(packages),
( ieee) ( lpm altera). , ( LIBRARY)
( USE).
LIBRARY _;
USE _._.all;

, :
USE ieee.std_logic_1164.all;
std_logic_1164 ieee.
, , *.vhd. ieee, , std1164.vhd,
std_logic_1164 , ,
.
lpm (Library of Parameterized Modules), ,
lpm_components (modules),
VHDL. , altera , macrofunctions megafunctions. -

336

, macrofunctions 300
74xx.
.2 ltera
MAX+plus II, .
.2
MAX+plus II

std1164.vhd

std_logic_1164

ieee

std_logic_unsigned

ieee

std_logic_signed

ieee

std_logic_arith

ieee

lpm_pack.vhd

lpm_components

lpm

maxplus2.vhd

maxplus2

altera

megacore.vhd

megacore

altera

std1164b.vhd
unsigned.vhd
unsignedb.vhd
signed.vhd
signedb.vhd
arith.vhd
arithb.vhd

.5.2
, VHDL
(entity). .
ENTITY _ IS
PORT ( _ {,_} : mode_
_;

 VHDL

337

_ {,_} : mode_
_);
END _ ;

: ()
, () (mode) () (..
std_logic... .).
(4) .3.
.3

IN

OUT

BUFFER
INOUT

<=

, IN , ,
OUT. , (FA) 1 bit (
.3) (, Cin )
(S Cout OUT),
std_logic.

.3
(FA) 1 bit

338

ENTITY FA IS
PORT ( A, B, Cin
S, Cout
END FA;

: IN std_logic;
: OUT std_logic );

BUFFER,
<=.
<=, , , ,
.
ENTITY test IS
PORT ( A
: IN std_logic;
S
: OUT std_logic;
Rout : BUFFER std_logic_vector(2 DOWNTO 0)
);
END test;

SIGNAL temp, temp_2 : std_logic;

temp <= A ;
S <= temp_2 ;
Rout <= Rout + 1 ;

.5.3
(architecture)
VHDL, . : () (declarative part) ()
(architecture body).
: ()
SIGNAL, () CONSTANT, () TYPE, () COMPONENT, () FUNCTION
() PROCEDURE.
SIGNAL, , COMPONENT, ,
PORT MAP, ,
.

 VHDL

BEGIN,
: () PORT MAP ( ), () (concurrent), () PROCESS, () GENERATE, ()
SELECT () (lpm).
ARCHITECTURE _ OF _
IS
SIGNAL
CONSTANT
TYPE
COMPONENT
FUNCTION
PROCEDURE
BEGIN
{PORT MAP ;}
-- COMPONENT
{ ;}
{PROCESS ;}
{GENERATE ;}
{SELECT ;}
{ lpm ;}
END _;

, VHDL
, , .
.

339

340

.6

VHDL

VHDL (levels)
:
(behavioral)
(structural)
(dataflow)

. , (structural) . ,
,
(.. , , .).
. . ,
8 bits
( [load]
[increment]) VHDL
(.. flip-flops, .).
(behavioral) .
(structural) (behavioral)

VHDL. , ,
(dataflow), Boolean .
.
, VHDL
(AND, OR, XOR .).
(dataflow) (structural)
,
, .
(behavioral) , -

 VHDL

.
, .
,
, . , .
.6.1 (behavioral model)
(behavioral) . H
VHDL
(.. C/C++), , FOR LOOP,
CASE, IF .
, . ,

, .
bits (4 bits). ( )
bits (Cin), (S, 4 bits) (Cout). VHDL +, ieee
. , , std_logic_unsigned.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY adder4_behav IS
PORT ( Cin
: IN std_logic;

341

342

A, B
: IN std_logic_vector(3 downto 0) ;
S
: OUT std_logic_vector(3 downto 0) ;
Cout
: OUT std_logic);
END adder4_behav;
ARCHITECTURE behavioral_arc OF adder4_behav IS
SIGNAL s_temp : std_logic_vector(4 downto 0) ;
BEGIN
s_temp <= A + B + Cin ;
S <= s_temp(3 downto 0);
Cout <= s_temp(4);
END behavioral_arc;

,
(entity). ,
(architecture),
. (s_temp) 5 bits,
bit [s_temp(4)] , 4
bits [bits s_temp(3) s_temp(0)] .
, :
s_temp <= A + B + Cin;
O S Cout.

4-bit . (compiler) +
, .

 VHDL

.6.1.1 PROCESS

PROCESS. : IF,
CASE FOR LOOP. O
PROCESS.
,
.
PROCESS , . , PROCESS, ,
.
: PROCESS (_ {,_})
{VARIABLE }
BEGIN
{ }
{ PROCEDURE}
{IF }
{CASE }
{FOR LOOP }
{ ;}
END PROCESS ;

PROCESS, , sensitivitylist.
, , PROCESS
.
. PROCESS
sensitivity-list
PROCESS. sensitivity-list
( IN).
.6.1.1.1 IF
IF , PROCESS. H

343

344

IF . VHDL
, , :
IF _1 THEN
;
{;}
ELSIF _2 THEN
;
{;}
{ELSIF _3 THEN
;
{;}
}
ELSE
;
{;}
END IF;

IF 21 bit, .4. ,
sel 0, ( y<=A), ( sel=1) .

.4
21 bit ( )

LIBRARY ieee;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS
PORT ( A, B
: IN std_logic ;
sel
: IN std_logic ;

 VHDL

345

: OUT std_logic

);
END mux2to1 ;
ARCHITECTURE mux2_arc OF mux2to1 IS
BEGIN
PROCESS
BEGIN
IF sel='0' THEN
y<=A;
ELSE
y<=B;
END IF;
END PROCESS;

-- sel='0'
-- sel='1'

END mux2_arc;

IF
NAND .
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT ( A, B : IN std_logic;
Y
: OUT std_logic);
END nand_gate;
ARCHITECTURE arc OF nand_gate IS
BEGIN
PROCESS
BEGIN
IF A/=B THEN
Y<='1';
ELSIF A=B THEN
IF A='1' THEN
Y<='0';
ELSE
Y<='1';
END IF;
END IF;

-- A=1 B=0, A=0 B=1

-- A=1 B=1
-- A=0 B=0

346

END PROCESS;
END arc;

.6.1.1.2 CASE
CASE VHDL .
IF, PROCESS, . :
CASE _ IS
WHEN _1 =>
{
WHEN _2 =>
{

WHEN OTHERS => ;

{ ;}
END CASE;

;
;}
;
;}

CASE
( bits) WHEN.
CASE WHEN OTHERS,
( WHEN).
CASE 21
bit IF. To CASE.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1_v2 IS
PORT ( A, B
: IN std_logic ;
sel
: IN std_logic ;
y
: OUT std_logic
);

 VHDL

347

END mux2to1_v2 ;
ARCHITECTURE mux2_arc OF mux2to1_v2 IS
BEGIN
PROCESS
BEGIN
CASE sel IS
WHEN '0'
=> y <= A;
WHEN OTHERS => y <= B;
END CASE;
END PROCESS ;

-- sel='0'
-- sel='1'

END mux2_arc;

sel : 0 1. , sel
0, y A.
sel 1, WHEN OTHERS.
.
CASE
CPU. (4) bits
(buffers),
. .5, , , B
C, bits. ,
,
S0 1. , C
S1 S2 .

348

.5
() CPU
()

,
(A, B C) , .
, CASE, (3) bits ( control) bit S0, S1 S2. ,
(8). , (001, 010 100), A, B C
, WHEN OTHERS, ( 0000).
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY system_BUS IS
PORT ( A, B, C
S0, S1, S2
data_bus
);
END system_BUS ;

: IN std_logic_vector(3 downto 0) ;
: IN std_logic ;
: OUT std_logic_vector(3 downto 0)

ARCHITECTURE BUS_arc OF system_BUS IS

 VHDL

SIGNAL sys_Bus
SIGNAL control

349

: std_logic_vector(3 downto 0);

: std_logic_vector(2 downto 0);

BEGIN
control <= S2 & S1 & S0 ;
PROCESS
BEGIN
CASE control IS
WHEN "001" =>
WHEN "010" =>
WHEN "100" =>
WHEN others =>
END CASE;
END PROCESS ;

data_bus
data_bus
data_bus
data_bus

<=
<=
<=
<=

A;
B;
C;
"0000";

END BUS_arc ;

.6.1.1.3 FOR LOOP

FOR LOOP. H ( ) ,
, .
: FOR _ _ _
LOOP
;
{;}
END LOOP ;

8 bits .
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shift_register IS
PORT ( data_in
: IN std_logic_vector(7 DOWNTO 0);
clk
: IN std_logic;

350

load
Q

: IN std_logic;
: BUFFER std_logic_vector(7 DOWNTO

0) );
END shift_register ;
ARCHITECTURE reg_arc OF shift_register IS
BEGIN
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF load = '1' then
Q <= data_in;
ELSE
f1: FOR i IN 0 TO 6 LOOP
Q(i) <= Q(i+1);
position
END LOOP;
Q(7) <= '0';
END IF;
END IF;
END PROCESS;

--shift right 1

END reg_arc;

, FOR LOOP .
Q (
) buffer :
Q(i) <= Q(i+1);
Q
<=. 8 bits ,
(7) : Q(1) Q(0), Q(2)
Q(1), ... ... ,
FOR LOOP, . , ,
bit Q(7) [Q(7)<=0].

 VHDL

VHDL .
.6.2 (structural model)
VHDL , , (.. , flip-flops).
4-bit
.
VHDL
bit (1-bit FA) (
).
( ) (component).
VHDL .vhd.
(
) COMPONENT,
PORT MAP.
, .
FOR
GENERATE. PORT MAP FOR GENERATE .
M , VHDL 4-bit 1-bit . , . ,
bit
,
.6.

351

352

.6
() bit, ()
()

VHDL 1-bit . , NAND XOR.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY FA IS
PORT ( A, B, Cin
S, Cout
END FA;

: IN std_logic;
: OUT std_logic );

 VHDL

353

ARCHITECTURE arc OF FA IS
SIGNAL x1, x2, x3

: std_logic ;

BEGIN
x1 <= A xor B ;
x2 <= A nand B ;
x3 <= Cin nand x1 ;
S <= x1 xor Cin ;
Cout <= x2 nand x3 ;
END arc;

1-bit VHDL, (4-bit )

COMPONENT PORT MAP, .
.6.2.1 COMPONENT
(component)
, .
( VHDL)
, COMPONENT.
COMPONENT _ IS
PORT ( _ {,_} : mode_
_;

_ {,_} : mode_
_);
END COMPONENT ;

,
, PORT .
, *.vhd. bit, , COMPONENT :

354

COMPONENT FA
PORT ( A, B, Cin
S, Cout
END COMPONENT;

: IN std_logic;
: OUT std_logic);

FA, VHDL bit (FA.vhd).

.6.2.2 PORT MAP
H (component) PORT MAP,
:
: _ PORT MAP(
port);

PORT MAP (label),

PORT P .
PORT COMPONENT .
, 4-bit (
.7) o VHDL :
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY adder4_struct IS
PORT ( A, B : IN std_logic_vector(3 DOWNTO 0) ;
Cin : IN std_logic ;
Sum : OUT std_logic_vector(3 DOWNTO 0);
Cout : OUT std_logic );
END adder4_struct;
ARCHITECTURE arc OF adder4_struct IS
COMPONENT FA is
PORT ( A, B, Cin
S, Cout
END COMPONENT;

: IN std_logic;
: OUT std_logic );

 VHDL

355

SIGNAL C : std_logic_vector(4 DOWNTO 0);

BEGIN
C(0)<=Cin;
FA_1:
FA_2:
FA_3:
FA_4:

FA
FA
FA
FA

PORT
PORT
PORT
PORT

MAP
MAP
MAP
MAP

(A(0),
(A(1),
(A(2),
(A(3),

B(0),
B(1),
B(2),
B(3),

C(0),
C(1),
C(2),
C(3),

Sum(0),
Sum(1),
Sum(2),
Sum(3),

C(1));
C(2));
C(3));
C(4));

Cout <= C(4);

END arc ;

.7
4-bit 1-bit

FA
C, bit . , Cin C(0), C(1)
C(3), Cout C(4).
.6.2.3 FOR GENERATE
FOR GENERATE
(concurrent) , , .
, FOR GENERATE PORT MAP:

356

_1: FOR _ IN _ TO
_ GENERATE
_2 : PORT MAP ;
{_3 : PORT MAP ; }
END GENERATE ;

FOR GENERATE
4 bits . ,
FA (4) ,
PORT MAP. FOR
GENERATE, PORT MAP
:
p1: FOR i IN 0 TO 3 GENERATE
FA_4: FA PORT MAP (A(i), B(i), C(i), Sum(i), C(i+1)
);
END GENERATE ;

.6.3 (dataflow model)

(dataflow).
,
.
( ).
.6.3.1 (Concurrent Signal
Assignment)
M
, .
Low <= '0';
f <= A AND (B XOR (NOT C));

 VHDL

357

.6.3.2 (Conditional Signal

Assignment)
,
, . :
_ <= _1 WHEN _1 ELSE
_2 WHEN _2 ELSE
...
_;

38. (output) (sel).

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
ENTITY decoder_3to8 IS
PORT( sel
: IN std_logic_vector(2 DOWNTO 0);
output : OUT std_logic_vector(7 DOWNTO 0));
END decoder_3to8 ;
ARCHITECTURE dataflow_arc OF
BEGIN
output <= "00000001" WHEN
"00000010" WHEN
"00000100" WHEN
"00001000" WHEN
"00010000" WHEN
"00100000" WHEN
"01000000" WHEN
"10000000" WHEN
"00000000";

decoder_3to8 IS
(sel
(sel
(sel
(sel
(sel
(sel
(sel
(sel

=
=
=
=
=
=
=
=

"000")
"001")
"010")
"011")
"100")
"101")
"110")
"111")

ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE

END dataflow_arc ;

.6.3.3 SELECT
M ( ). -

358

(WHEN OTHERS)
.
WITH __ SELECT
_ <= _1 WHEN _1 {|} ,
_2 WHEN _2 {|} ,
...
_ WHEN OTHERS;

SELECT
41 bit, .8.
sel 2 bits, S1 S0. (sel=11)
WHEN OTHERS.

.8
41 bit

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( A, B, C, D
S0, S1
mux_out

: IN std_logic ;
: IN std_logic ;
: OUT std_logic );

 VHDL

359

END mux4to1 ;
ARCHITECTURE dataflow_arc OF mux4to1 IS
SIGNAL sel : std_logic_vector(1 DOWNTO 0);
BEGIN
sel <= S1 & S0 ;
WITH sel SELECT
mux_out <= A
B
C
D
END dataflow_arc ;

WHEN
WHEN
WHEN
WHEN

"00",
"01",
"10",
OTHERS;

.6.4 PACKAGE
H (PACKAGE) (components) . ,
component
,
. ()
, .
COMPONENT, , (PACKAGE)
(CONSTANT, VARIABLE SIGNAL), (TYPE,
SUBTYPE), FUNCTION PROCEDURE.
PACKAGE __ IS
CONSTANT
VARIABLE
TYPE
SUBTYPE
SIGNAL
COMPONENT

360

FUNCTION
PROCEDURE
END __;

, PACKAGE, . ,
my_package (component) 1-bit (FA)
std_logic_1164 ieee,
std_logic FA. ( VHDL)
PACKAGE .
PACKAGE
.vhd. , , my_package.vhd :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
COMPONENT FA
PORT ( A, B, Cin
S, Cout
END COMPONENT;

: IN std_logic;
: OUT std_logic );

END my_package;

.6.4.1 (package)
,
,
(compilation), VHDL.
,
.
,
work.

 VHDL

LIBRARY work;
USE work.__.all;

VHDL 4-bit . ,
1 bit component. , FA
, ,
my_package.vhd, .
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
USE work.my_package.all;
ENTITY adder_4bit_v2 IS
PORT ( A, B : IN std_logic_vector(3 DOWNTO 0);
Cin : IN std_logic;
Sum : OUT std_logic_vector(3 DOWNTO 0);
Cout : OUT std_logic );
END adder_4bit_v2 ;
ARCHITECTURE arc OF adder_4bit_v2 IS
SIGNAL C : std_logic_vector(4 DOWNTO 0);
BEGIN
C(0)<=Cin;
p1: FOR i IN 0 TO 3 GENERATE
FA_4: FA PORT MAP (A(i), B(i), C(i), Sum(i), C(i+1)
);
END GENERATE ;
Cout <= C(4);
END arc ;

361

362

.7

(concurrent) (sequential) ,
.
, IF, CASE FOR LOOP, (behavioral).
.7.1 (clock)
, (clock) . , : . VHDL , .
.7.1.1 falling_edge() rising_edge()
falling_edge() rising_edge()
, , . std_logic_1164 ieee,
. (.. clock).
, D flip-flop D Q, :
IF falling_edge(clock) THEN
Q <= D;
END IF;

.7.1.2 EVENT
EVENT.
D flip-flop :

 VHDL

363

IF clock 'EVENT AND clock='0' THEN

Q <= D;
END IF;

D flip-flop
clock ( clock=1
clock=0).
.7.1.3 WAIT UNTIL
WAIT UNTIL ,

(clock) 0 1 . , :
WAIT UNTIL clock= '0';
. ,
D flip-flop WAIT UNTIL
:
WAIT UNTIL clock='0';
Q <= D;

, WAIT UNTIL EVENT ,

.
WAIT UNTIL clock'EVENT AND clock = '0';
Q <= D;

.7.2
.7.2.1 D flip-flop
D
flip-flop . flip-flop , .9, (reset)
1.

364

.9
D flip-flop

VHDL
( ),
IF. flip-flop falling_edge(). falling_edge() , , ,
. , . , , . , falling_edge().
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY d_ff IS
PORT ( D
: IN std_logic;
clock, reset : IN std_logic;
Q
: OUT std_logic);
END d_ff ;
ARCHITECTURE dff_arc OF d_ff IS
BEGIN
p1: PROCESS (clock, reset)
BEGIN
IF reset = '1' THEN
Q <= '0' ;
ELSIF falling_edge(clock) THEN
Q <= D;
END IF;

 VHDL

END PROCESS ;
END dff_arc ;

.7.2.2 D flip-flop
D flip-flop ,
, ,
.
falling_edge(). To
:
ARCHITECTURE dff_arc OF d_ff_sync IS
BEGIN
p1: PROCESS (clock, reset)
BEGIN
IF falling_edge(clock) THEN
IF reset = '1' THEN
Q <= '0' ;
ELSE
Q <= D;
END IF;
END IF;
END PROCESS ;
END dff_arc ;

.7.2.3 K 8 bits
8 bits ( .10)
VHDL D flip-flop, (Rin Rout, , D Q)
std_logic_vector std_logic. ,
(reset), (load)
(inc).

365

366

.10
8 bits

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY register_8bit IS
PORT ( reg_in
;
clock, reset
load, inc
reg_out
0)) ;
END register_8bit ;

: IN std_logic_vector(7 DOWNTO 0)
: IN std_logic ;
: IN std_logic ;
: OUT std_logic_vector(7 DOWNTO

ARCHITECTURE reg_arc OF register_8bit IS

SIGNAL reg_data : std_logic_vector(7 DOWNTO 0);
BEGIN
p1: PROCESS (clock, reset)
BEGIN
IF reset = '1' THEN
reg_data <= "00000000";
ELSIF falling_edge(clock) THEN
IF load = '1' THEN
reg_data <= reg_in;
ELSIF inc = '1' THEN
reg_data <= reg_data + 1 ;
END IF;
END IF;
END PROCESS ;
reg_out <= reg_data ;
END reg_arc ;

 VHDL

.8

367

LPM

VHDL
(parameterized modules).
,
VHDL.
LPM (Library of Parameterized
Modules),
lpm_components.
LPM ,

lpm_add_sub),

(lpm_mux,

(lpm_ff,

lpm_decode,
lpm_counter,

lpm_shiftreg), , (lpm_fifo,
lpm_ram_dq, lpm_rom).
.8.1 ROM
LPM ROM (LPM_ROM).
, VHDL.
ARRAY, , . LPM_ROM LPM.
: lpm_rom
GENERIC MAP( LPM_WIDTHAD => ,
LPM_OUTDATA => "REGISTERED",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_FILE => "_.mif",
LPM_WIDTH => ,
LPM_TYPE => "LPM_ROM",
LPM_NUMWORDS => ,
LPM_HINT => "UNUSED" )
PORT MAP (address => _1,
inclock => _2,
outclock => _3,

368

memenab => _4,

q => _5);

H LPM_ROM , , . ( GENERIC P)

(LPM_WIDTH, LPM_WIDTHAD, ... .). ( ) .

( lpm )
: LPM_WIDTH, LPM_WIDTHAD, LPM_FILE, LPM_OUTDATA
LPM_ADDRESS_CONTROL. , LPM_WIDTH LPM_WIDTHAD,
(string), LPM_FILE,
LPM_OUTDATA LPM_ADDRESS_CONTROL.
, (default) . , LPM_OUTDATA REGISTERED,

, , , UNREGISTERED
, .
( PORT MAP)
lpm .
GENERIC MAP,
.
(address) (q),
.
ROM 3x12,
3 bits 12 bits ,
LPM_WIDTHAD LPM_WIDTH , , 3
12. , ,
LPM_OUTDATA LPM_ADDRESS_CONTROL UNREGISTERED. LPM_FILE, ( .mif).

 VHDL

, address
data, address q lpm , PORT MAP.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_ROM_memory IS
PORT( address : IN std_logic_vector(2 DOWNTO 0);
-3-bit address
data
: OUT std_logic_vector(11 DOWNTO 0)); -12-bit data
END lpm_ROM_memory ;
ARCHITECTURE MEM_arc OF lpm_ROM_memory IS
BEGIN
external_mem: lpm_rom
GENERIC MAP( lpm_widthad => 3,
lpm_outdata => "unregistered",
lpm_address_control => "unregistered",
lpm_file => "memory_data.mif",
lpm_width => 12)
PORT MAP (address => address, q => data);
END MEM_arc;

.8.2 *.mif
, ROM VHDL
LPM_ROM .mif . .
.mif
. , DEPTH WIDTH,

369

370

. , ROM
312 DEPTH 8, 3-bit
23=8 , WIDTH 12,
bits . (address_radix data_radix) (radix) . : (bin), (dec), (hex) (oct).
, , , (BIN)
(HEX),
, .
ROM 312 .mif :
depth = 8;
width = 12;
address_radix = bin;
data_radix = hex;

-- 3-bit address ---> 0-7 dec

-- 12-bit data

CONTENT
BEGIN
-- address : data ;
000
001
011
100
101
111

:
:
:
:
:
:

729
12d
01a
809
632
45c

;
;
;
;
;
;

END;

lpm .
.mif ,
, . ARRAY,

 VHDL

. , ( memory_data.mif) 010 110 , 000 (hex) .

371


8085

Opcode

Opcode

.1

ADC r

8F

Add with Carry

8E

Add with Carry to ADD r

Memory

87

Add

ADD M

86

Add to Memory

ADI n

C6

Add Immediate

ANA r

A7

AND
Accumulator

ANA M

A6

AND
Accumulator and
Memory

ANI n

E6

AND Immediate CALL a

CC a

DC Call on Carry

CM a

FC Call on Minus

CMA

2F

Complement
Accumulator

CMC

3F

Complement
Carry

CMP r

BF

Compare

CMP M

BF

Compare with
Memory

CNC a

D4

Call on No Carry CNZ a

C4

Call on No Zero

CP a

F4

Call on Plus

CPE a

EC Call on Parity
Even

CPI n

FE

Compare
Immediate

CPO a

E4

Call on Parity Odd

CZ a

CC Call on Zero

DAA

27

Decimal Adjust
Accumulator

DAD B

09

DAD D

19

Double Add DE
to HL

ACI n

CE Add with Carry

Immediate

ADC M

Double Add BC
to HL

CD Call unconditional

Opcode

Opcode

374

DAD H

29

Double Add HL
to HL

DAD SP

39

Double Add SP to
HL

DCR r

3D

Decrement

DCR M

35

Decrement
Memory

DCX B

0B

Decrement BC

DCX D

1B

Decrement DE

DCX H

2B

Decrement HL

DCX SP

3B

Decrement Stack
Pointer

DI

F3

Disable Interrupts EI

FB

Enable Interrupts

HLT

76

Halt

IN p

DB Input

INR r

3C

Increment

INR M

3C

Increment
Memory

INX B

03

Increment BC

INX D

13

Increment DE

INX H

23

Increment HL

INX SP

33

Increment Stack
Pointer

JMP a

C3

Jump
unconditional

JC a

DA Jump on Carry

JM a

FA Jump on Minus

JNC a

D2

Jump on No Carry

JNZ a

C2

F2

Jump on Plus

JPE a

EA Jump on Parity
Even

JPO a

E2

Jump on Parity
Odd

JZ a

CA Jump on Zero

LDA a

3A

Load Accumulator
direct

LDAX B

0A

Load
Accumulator
indirect

LDAX D

1A

Load Accumulator
indirect

LHLD a

2A

Load HL Direct

LXI B,nn

01

Load Immediate
BC

LXI D,nn

11

Load Immediate LXI H,nn

DE

21

Load Immediate
HL

LXI SP,nn

31

Load Immediate MOV r1,r2

Stack Ptr

7F

Move register to
register

MOV M,r

77

Move register to
Memory

7E

Move Memory to
register

Jump on No Zero JP a

MOV r,M

375

Opcode

Opcode

8085

MVI r,n

3E

Move Immediate MVI M,n

36

Move Immediate
to Memory

NOP

00

No Operation

ORA r

B7

Inclusive OR
Accumulator

ORA M

B6

Inclusive OR
Accumulator

ORI n

F6

Inclusive OR
Immediate

OUT p

D3

Output

PCHL

E9

Jump HL indirect

POP B

C1

Pop BC

POP D

D1

Pop DE

POP H

E1

Pop HL

POP PSW

F1

Pop Processor
Status Word

PUSH B

C5

Push BC

PUSH D

D5

Push DE

PUSH H

E5

Push HL

PUSH PSW

F5

Push Processor
Status Word

RAL

17

Rotate
RAR
Accumulator Left

1F

Rotate
Accumulator Righ

RET

C9

Return

RC

D8

Return on Carry

RIM

20

Read Interrupt
Mask

RM

F8

Return on Minus

RNC

D0

Return on No
Carry

RNZ

C0

Return on No
Zero

RP

F0

Return on Plus

RPE

E8

Return on Parity
Even

RPO

E0

Return on Parity RZ
Odd

C8

Return on Zero

RLC

07

Rotate Left
Circular

RRC

0F

Rotate Right
Circular

RST z

C7

Restart

SBB r

9F

Subtract with
Borrow

SBB M

9E

Subtract with
Borrow

SBI n

DE Subtract with
Borrow
Immediate

SHLD a

22

Store HL Direct

SIM

30

Set Interrupt
Mask

Opcode

Opcode

376

SPHL

F9

Move HL to SP

STA a

32

Store
Accumulator

STAX B

02

Store
Accumulator
indirect

STAX D

12

Store
Accumulator
indirect

STC

37

Set Carry

SUB r

97

Subtract

SUB M

96

Subtract Memory SUI n

D6

Subtract
Immediate

XCHG

EB Exchange HL
with DE

XRA r

AF Exclusive OR
Accumulator

XRA M

AE Exclusive OR
Accumulator

XRI n

EE Exclusive OR
Immediate

XTHL

E3

Exchange stack
Top with HL

 8085

377

.2

.2.1

8085

8085:
addr: 16 bits
byte: 8 bits
word: 16 bits
port: 8-bit /
r, r1, r2: A, B, C, D, E, H, L.
rp: : B B, C,
C , D
D, E, D
E , H, L,
H L
.2.2

( )

LDA addr
Bytes:

Load Accumulator

3 addr.

.. LDA 2000H (

2000)
: 13
STA addr
Bytes:

Store Accumulator

3
addr.

.. STA 2000H (
: 13
2000)
MOV r1,r2 Move Register2 to Register1 :
Bytes:

1 r2

378

r1.

: 4 .. MOV B,D ( D
B)
MOV r,
Bytes:

Move Memory to Register

1
HL r.

.. MOV B,M (
: 7
HL B)
MOV M,r
Bytes:

Move Register to Memory

1 r
HL.

.. MOV ,B (
: 7
HL)
MVI r,byte
Bytes:

Move Immediate

2 byte r.

.. MVI B,2F ( 2F B)

: 7
MVI ,byte Move Immediate
Bytes:

2 byte
HL.

.. MVI M,2F ( 2F
: 10
HL)
LXI rp,word
Bytes:

Load Register Pair

Immediate

3 16-bit word
rp.

.. LXI H,200F ( 200F o

: 10
HL)
LHLD addr Load Accumulator Direct

 8085

Bytes:

379

HL . L
3 addr
addr+1.

.. LHLD 200 ( 200

L 201
: 16
)
SHLD addr Store H and L Direct
Bytes:

3 HL . addr
L addr+1
H.

: 16 .. SHLD 200 ( L
200 H 201)
LDAX rp
Bytes:

Load Accumulator Indirect

1
rp.
: BC DE
.

: 7 .. LDAX B (

BC)
STAX rp
Bytes:

Store Accumulator Indirect

1
rp.
: BC DE
.

: 7 .. STAX B (

BC)
XCHG
Bytes:

Exchange H and L with D

and E

1 HL
DE.

: 4 H D L .

380

.2.3

ADD r
Bytes:

Add Register

1 r .

: Z, S, P, CY AC.

: 4 .. ADD D (
D)
ADD M
Bytes:

Add Memory

1
HL.

: 7 : Z, S, P, CY AC.
ADC r
Bytes:

Add Register with Carry

1 r
.

: Z, S, P, CY AC.

: 4 .. ADC D ( D
CY)
ADC M
Bytes:

Add Memory with Carry

1
HL .

: 7 : Z, S, P, CY AC.
ADI byte
Bytes:

Add Immediate

2 8-bit byte.

: Z, S, P, CY AC.

: 7 .. ADI 2C ( 2C)
ACI byte
Bytes:

Add Immediate with Carry

2 8-bit byte
.

: Z, S, P, CY AC.

: 7 .. ACI 2C ( 2C
CY)

 8085

SUB r
Bytes:

Subtract Register

381

1 r .

: Z, S, P, CY AC.

: 4 .. SUB D (
D)
SBB r
Bytes:

Subtract Register with

Borrow

1 r
.

: Z, S, P, CY AC.

: 4 .. SBB D (
D CY)
SUB M
Bytes:

Subtract Memory

1
HL .

: 7 : Z, S, P, CY AC.
SBB M

Subtract Memory with

Borrow

1
HL

.
: 7
: Z, S, P, CY AC.
Bytes:

SUI byte
Bytes:

Subtract Immediate

2 byte .

: Z, S, P, CY AC.

: 7 .. SUI 3B ( 3B)
SBI byte
Bytes:

Subtract Immediate with

Borrow

2 byte

382

: Z, S, P, CY AC.
: 7
.. SI 3B ( 3B
CY)
INR r
Bytes:

Increment Register

1 r .

: CY.

: 4 .. INR B ( B )
INR
Bytes:

Increment Memory

1
HL .

: 10 : CY.
DCR r
Bytes:

Decrement Register

1 r .

: CY.

: 4 .. DCR B ( B )
DCR
Bytes:

Decrement Memory

1
HL .

: 10 : CY.
INX rp
Bytes:

Increment Register Pair

1 rp .

: .

: 6 .. IN D ( 16-bit DE
)
DCX rp
Bytes:

Decrement Register Pair

1 rp .

 8085

383

: .

: 6 .. DC D ( 16-bit DE
)
Add Register Pair to H and
L

DAD rp

1 rp HL,
.

Bytes:

: CY.

: 10 .. DAD D ( 16-bit DE
HL).
DA

Decimal Adjust Accumulator :

Bytes:

1
BCD.

4 bits
9, 6h. , ,

bits 9
: 4 , 60h.
.. =10001100 (9Ch), DAA
10010010 (92h)

.2.4

ANA r
Bytes:

AND Register
1

r.

.. A D ( D.
: 4
).
ANA
Bytes:

AND Memory
1

: 7

HL .
.

384

ANI byte
Bytes:

AND Immediate
1

8-bit byte.

: 7 .. AI 8D (
8D).
XRA r
Bytes:

Exclusive OR Register
1

r.

.. XR D (

: 4 D.
).
XRA
Bytes:

Exclusive OR Memory
1

: 7
XRI byte
Bytes:

HL .
.
Exclusive OR Immediate

8-bit byte.

: 7 .. XRI 8D (
8D).
ORA r
Bytes:

OR Register
1

r.

.. OR D ( D.
: 4
).
ORA

OR Memory

 8085

Bytes:

: 7
ORI byte
Bytes:

HL .
.
OR Immediate

385

8-bit byte.

: 7 .. ORI 8D (
8D).
CMP r
Bytes:

Compare Register
1

r.
r .
(CY, Z).

.. CMP C ( C.
: 4
0, , CY 1,
C> , C<.
CMP

Compare Memory

HL .
.

(CY, Z).
: 7 0, , CY 1,
> , <.
Bytes:

CP byte
Bytes:

Compare Immediate
2

byte.
byte .
(CY, Z).

.. CMP 2F ( 2F.
: 7
0, , CY 1,
2F> , 2F<.
CM
Bytes:

Complement Accumulator
1

386

.. =10001100 (9Ch), CMA

: 4 01110011 (73h)
CMC

Complement Carry

Bytes:

CY.

.. CY=1, CMC CY 0 ( )

: 4
STC

Set Carry

Bytes:

: 4

.2.5

CY 1,
.

JMP label
Bytes:

Jump

label

: 10

.. JMP rout1 (
rout1)

JNZ label
JZ label
JNC label
JC label
JPO label

Condition Jump

JPE label
JP label
JM label
Bytes:

: 7/10

label,
Z, CY, P S. :

 8085

387

Not Zero

Z=0

Parity Odd

P=0

Zero

Z=1

Parity Even

P=1

No CarrY

CY=0

Positive

S=0

CarrY

CY=1

Negative

S=1

.. JZ rout1 (
rout1 =0)

.2.6

CALL func

Call

Bytes:

func.

: 18

, PC .

RET

Return

Bytes:

: 10

.. CALL rout1 ( rout1)

:

. ,
PC .

CNZ func
CZ func
CNC func
CC func

Condition Call

CPO func

CPE func
CP func
CM func
Bytes:

func,

388

Z, CY, P
S. :

: 9/18

Not Zero

Z=0

Parity Odd

P=0

Zero

Z=1

Parity Even

P=1

No CarrY

CY=0 Positive

S=0

CarrY

CY=1 Negative

S=1

.. CZ rout1 ( rout1 =0)

RNZ func
RZ func
RNC func
RC func

Condition Return

RPO func

RPE func
RP func
RM func
Bytes:

. ,
PC .
Z,
CY, P S. :

: 6/12

Not Zero
Z=0
Parity Odd
P=0
Zero
Z=1
Parity Even
P=1
No CarrY
CY=0 Positive
S=0
CarrY
CY=1 Negative
S=1
.. RZ (
=0)

RST N

Restart

Bytes:

: 12

PC
*8.
0 7.

 8085

Jump HL Indirect/ Move

HL to PC (Program
:
Counter)

PCHL
Bytes:

: 6

HL PC.
.
.. H=9C L=A3, PCHL PC
9CA3

.2.7
PUSH rp
Bytes:
1

: 12
POP rp
Bytes:
1

: 10
XTHL

Push

rp
.
.. PUSH HL ( HL
)
Pop
:

rp
.
.. POP HL ( HL
)
Exchange stack top with H :
and L

HL
.

Bytes:
1

: 16
Move HL to SP
:
SPHL
Bytes:
1 HL
.

: 6

389

390

.2.8
RLC

Rotate Left

1
.

. CY.
: 4
.. =10011100 (9C), RLC 00111001
(39)
Bytes:

RRC

Rotate Right

1
.

. CY.
: 4
.. =10011100 (9C), RRC
01001110 (4E)
Bytes:

RAL

Rotate Left Through Carry :

Bytes:

1
.

CY,
: 4
. CY.
RAR

Rotate Right Through

Carry

1
.

CY,
: 4
. CY.
Bytes:

 8085

.2.9

391

HLT
Bytes:

Halt
1

: 4
NOP
Bytes:

.

.
No Operation

: 4

Bytes:

.
.
.
Enable Interrupts

: 4
D
Bytes:

Disable Interrupts
1

: 4
port
Bytes:

Input
2

: 10
OUT port
Bytes:

8-bit
,
port, .
Output

: 10
RIM
Bytes:

8-bit
port
.
Read Interrupt Mask

: 4

. ,
:
SID 7.5 6.5 5.5

7.5 6.5 5.5

SID= ,

392

.5= RST .5
,
= ,
.5= RST .5.
SIM
Bytes:

Set Interrupt Mask

1

: 4

RST 5,
latch RST 7.5 SOD (serial output data).
:
SOD SOE

R7.5 MS 7.5 6.5 5.5

SOD= ,
= ,
R7.5= RST 7.5,
MSE= ,
.5= RST .5.


[1] Ashenden P. J. (1990), The VHDL Cookbook, 1st Ed., Technical Report,
University of Adelaide, South Australia.
[2] Brown S. D. & Vranesic Z. G. (2000), Fundamentals of Digital Logic with
VHDL Design, McGraw-Hill.
[3] Carpinelli J. D. (2000), Computer Systems Organization and Architecture,
Addison Wesley.
[4] Hwang E. (2005), Digital Logic and Microprocessor Design with VHDL, La
Sierra University, Riverside, CA Brooks/Cole,
[http://cs.lasierra.edu/~ehwang/mybook/toc.html]
[5] Kleitz W. (1996), Digital Electronics: A Practical Approach, 4th Ed.,
Prentice-Hall.
[6] Malvino A. P. & Leach D. P. (1988), Digital Principles and Applications, 4th
Ed., McGraw-Hill.
[7] Mano M. Morris (1992), , &
Prentice Hall.
[8] Tocci R. J. & Widmer N. S. (1998), Digital Systems: Principles And
Applications, 7th Ed., Prentice-Hall.
[9] Tokheim R. L. (1991), , 3 , . .
[10] . (2000), : , .
[11] . (2000), : ,
.
[12] . (2000), : ,
.
[13] . . (1994), , 1,
, .
[14] . (2004), :
, .