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8086 Microprocessor and Applications AU CBE R2008
8086 Microprocessor and Applications AU CBE R2008
Unit III
Intel 8086:
Features:
1. 16-bit Data bus
2. Computes 16 bit / 32 bit data.
3. 20-bit address bus.
4. More memory addressing capability (220 = 1MB)
5. 16 bit Flag register with 9 Flags
6. Can be operated in Minimum mode and Maximum mode
7. Has two stage pipelined architecture
8. No internal clock generation
9. 40 pin DIP IC - HMOS technology
10. Operates on +5V supply voltage
11. Has more powerful instruction set
It can operate in two modes, i.e. single processor (minimum mode) or multiprocessor
(maximum mode) configuration.
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The remaining components in the system are latches, transceivers, clock generator,
memory or I/O devices.
The latches are used for separating the valid address from the multiplexed address/data
signals and the controlled by the ALE signal generated by 8086.
Transceivers are the bi-directional buffers. They are required to separate the valid data
from the time multiplexed address/data signal. This is controlled by two signals, DEN
& DT/R (low).
DT/R (low) indicates that the direction of data, i.e. from or to the indicator.
DEN signal indicates the valid data is available on the data bus.
The clock generator in the system is used to generate the clock and to synchronize
some external signals with the system clock.
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MRDC (low) : Memory read command It instructs the memory to put the contents of
the addressed location to the data bus.
MWTC (low) : Memory write command It instructs the memory to accept the data
on the data bus and load that data into the address memory location.
IORC (low) : I/O read command It instructs an I/O device to put the data contained
in the addressed port on the data bus.
IOWC (low) : I/O write command It instructs an I/O device to accept the data on the
data bus and load the data into the addressed port.
AIOWC (low) / AMWC (low) : Advance IO write command / Advance memory write
command These are similar to IOWC and MWTC except that they are activated one
clock pulse earlier. This gives slow interfaces an extra clock cycle to prepare to input
the data.
This system also consists of latches, tristate buffer, memory input-output device, etc.
The DEN, DT/R, ALE, etc is derived by the bus controller from the information
available on the active low status signals (S2, S1 & S0).
In this mode, Request/Grant pin (RQ/GT) is checked at each rising pulse of clock I/P
when the request is detected and if Hold request are satisfied, the processor issues a
grant pulse over RQ/GT pin immediately during T4 or next T1 state to accept the
control of the bus. Therefore, the requesting controller uses the bus till it requires.
When it is ready to relinquish the bus, it sends a release pulse to the processor using the
RQ/GT pin.
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8086 ARCHITECTURE:
The 8086 processor is divided into two independent functional units. They are,
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Segment registers
Instruction pointer
Instruction queue
Address generation
Bus control circuit
1. Segment Registers:
8086 processor has capability to address memory of size 1 MB and the memory is divided
into 16 segments of up to 64 Kbytes each. Each 64KB segment can be used to store the
code, data, stack, etc., separately and the segment address of the same is stored in
corresponding segment registers.
The four 16-bit segment registers in BIU are
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If queue is full, the BIU does not perform any bus cycle i.e., BIU does not prefetch any
instructions. Therefore, BIU may prefetch the instructions from memory until queue is
full.
While fetching the instruction from memory, if the Execution Unit (EU) interrupts the
BIU for memory access, the BIU first complete fetching and then services the EU.
If a subroutine call or Jump instructions are encountered, the BIU will reset the queue
and begin refilling after passing the new instruction to the EU.
3. Address Generation:
BIU contains an adder, which is used to produce the 20-bit physical address of memory by
addressing the contents of segment address and offset address.
4. Bus Control Logic:
The bus control logic of the BIU generates all the bus control signals such as read and write
signals for memory and I/O.
Execution Unit:
The Execution unit (EU) takes instruction from instruction queue, decodes and executes
instructions one after another.
It contains the following blocks to provide functions such as decoding and execution of
instructions.
1. 16-bit ALU
2. 8x16-bit Registers (AX, BX, CX, DX, SP, BP, SI & DI).
3. 16-bit Flag Register
1. ALU
The ALU has the capacity to handle 16-bit data and it performs several arithmetic and
logical operations on 16-bit / 32-bit data.
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2. General Registers
There are eight 16-bit general registers in EU of 8086 to store 16 bit/8 bit data. They are
AX, BX, CX, DX, SP, BP, SI & DI
The four 16-bit registers, AX, BX, CX and DX are combination of two 8-bit registers ie.,
H-higher byte and L-lower byte. These registers can be used to store a 16-bit data when
used as a whole 16-bit register or store 8-bit data when used separately.
AX - 16-bit accumulator used in the Arithmetic & Logical operations.
AL is the 8-bit accumulator.
BX - the only general-purpose 16-bit register & also used for addressing memory.
CX register is the 16-bit counter register used along with LOOP instructions.
DX is the data register is used to hold excess 16-bit result while performing multiplication,
division, etc.
SP & BP are point registers, which are used to access data in stack segment and other
segments.
3. Flag Register:
The EU also contains a 16-bit flag register which holds the status flags typically after an
ALU operation. The flag register of 8086 micro processor is,
O
D
I
S
Z
AC
P
CY
Overflow flag
Direction flag
Interrupt flag
Sign flag
Zero flag
Auxiliary carry flag
Parity flag
Carry flag
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Over flow flag (O): This flag is set, if an overflow occurs during the arithmetic
operation of two signed numbers.
Sign flag (S): This flag is set, if an MSB of the accumulator is set after any
computation.
Zero flag (Z): This flag is set, if the result of any computation is zero.
Auxiliary carry flag (AC): This flag is set, if there is a carry from the third bit, during
addition or borrow.
Parity flag (P): The flag is set, if the lower byte result contains even number of 1s.
Carry flag (CY): This flag is set, if any computation result contains a carry.
B- MACHINE CONTROL FLAGS
Direction Flag: This flag is set, if the string is processed from higher address towards
lower address. Otherwise, the flag is reset. This is used only in string manipulation
instructions.
Interrupt flag: This flag is set, only when maskable interrupts are recognized.
Trap flag: When a trap interrupt is received by the processor, this flag is set, which
indicates, the processor to execute the current instruction and to transfer the control to
trap service routine. In Other words, When 8086 enters in single step mode, this flag is
set.
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ADDRESSING MODES:
1. Addressing modes for accessing Immediate and Register data.
2. Addressing modes for accessing data in Memory.
3. Addressing modes for accessing I/O ports.
4. Relative Addressing mode.
5. Implied Addressing mode.
[BX]
MOV CL, BL
[CL]
: [BL]
: 26H
[BL]
[CX]
An Effective Address (EA), which is the offset (an unsigned 16 bit data or signed
8 bit data) from the data segment register, is directly specified in the instruction.
Eg. : MOV CX, [9823H]
The effective address is, EA = 9823H.
The base address is, BA = [DS] x 1610
The memory address, which is having the data, is, MA = [EA] + [BA].
The MA content will be copied into the register CX.
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An Effective Address (EA), which is the offset (an unsigned 16 bit data or signed
8 bit data) from the data segment register, is indirectly specified in the instruction.
The registers used to hold the effective address are BX, SI and DI.
Eg. : MOV CX, [BX]
The effective address is, EA = [BX].
The base address is, BA = [DS] x 1610
The memory address, which is having the data, is, MA = [EA] + [BA].
The MA content will be copied into the register CX.
In this addressing mode the BX or BP register is used to hold the base value for
EA and an unsigned 16 bit data or signed 8 bit displacement will be specified in
the instruction.
Eg. : MOV AX, [BX + 08H]
(ie., 08H 0008H)
The effective address is, EA = [BX] + [0008H]
The base address is, BA = [DS] x 1610
The memory address, which is having the data, is, MA = [EA] + [BA].
The MA content will be copied into the register AX.
In this addressing mode the SI or DI register is used to hold the index value for
EA and an unsigned 16 bit data or signed 8 bit displacement will be specified in
the instruction.
Eg. : MOV AX, [DI + 08H]
08H
0008H
The effective address is, EA = [DI] + [0008H]
The base address is, BA = [DS] x 1610
The memory address, which is having the data, is, MA = [EA] + [BA].
The MA content will be copied into the register AX.
In this addressing mode the SI or DI register is used to hold the index value for
EA and BX or BP register is used to hold the base value for EA an unsigned 16
bit data or signed 8 bit displacement will be specified in the instruction.
Eg. : MOV AX, [BX +DI + 08H]
08H
0008H
The effective address is, EA = [DI] + [BX] + [0008H]
The base address is, BA = [DS] x 1610
The memory address, which is having the data, is, MA = [EA] + [BA].
The MA content will be copied into the register AX.
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In this addressing mode the EA for source is stored in Si register and EA for
destination is stored in DI register.
Eg. : MOVS BYTE
The effective address for source is, EA = [SI]
The base address for source is, BA = [DS] x 1610
The memory address, which is having the data, is, MA = [EA] + [BA].
The effective address for destination is, EAD = [SI]
The base address for destination is, BAD = [ES] x 1610
The memory address in where the data to move is, MAD = [EA] D + [BA] D.
The MA content will be copied into MAD.
After moving the byte,
If DF = 1, SI and DI will be decremented by 1.
If DF = 0, SI and DI will be incremented by 1.
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It stores the 16 bit data from the destination to the stack pointer.
It increments the stack pointer by 2.
Eg. : SP = 80983H
CX = 49A3H
POP CX
[CX] SP
SP = 80985H
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OUT:
This instruction will copy data from a port to the accumulator.
The OUT instruction copies a byte from AL or a word from AX to the specified port.
B. Subtraction Instructions:
SUB
SBB
DEC
NEG
CMP
AAS
DAS
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C. Multiplication Instruction:
MUL:
It is used to multiply an unsigned byte from the source and unsigned byte in AL
register and stores the result in AX.
It is used to multiply an unsigned word from the source and unsigned word in
AX register and stores the high word of result stored in DX and low word in
AX.
Eg. : MUL BL - AL x BL, result stored in AX.
MUL BX AX x BX, High word of result stored in DX and low word in AX.
IMUL It multiplies the word or byte with sign.
AAM BCD adjust after multiply.
D. Division Instruction:
DIV
IDIV - It is used to divide a signed word (16 bit) by a byte (8 bit) or to divide a signed
double word (32 bit) by a word (16 bit).
AAD - Binary adjust before division.
CWD - It copies the D15 bit of AX into all the bits in DX.
Eg.: DX = 0000 0000 0000 0000
AX = 1111 0000 1100 0001
D15 of AX is 1.
Now, DX = 1111 1111 1111 1111
AX = 1111 0000 1100 0001
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if AL = 0110 1100
NOT AL
; AL = 1001 0011
if CX = 1010 1111 0010 0010
NOT CX
; CX = 0101 0000 1101 1001
AND: This instruction logically ANDs each bit of the source byte or word with the
corresponding bit in the destination and stores result in the destination.
Eg. : AL = 1001 0011 = 93H
BL = 0111 0101 = 75H
AND BL, AL
OR : This instruction logically ORs each bit of the source byte or word with the
corresponding bit in the destination and stores result in the destination.
Eg. : AL =1001 0011 = 93H
BL =0111 0101 = 75H
OR BL, AL
XOR : This instruction logically XORs each bit of the source byte or word with the
corresponding bit in the destination and stores result in the destination.
TEST: This instruction logically ANDs each bit of the source byte or word with the
corresponding bit in the destination and updates the flags but not stores results
in anywhere.
Eg.: AL = 1001 0011 = 93H
BL = 0111 0101 = 75H
AND BL, AL
AND BX, AX
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V. RORATE INSTRUCTIONS
ROL:
The mnemonics is ROL destination, count.
It rotates each bit in the destination to the left.
The MSB is shifted to the carry flag and to the LSB position.
ROR :
The mnemonics is ROR destination, count.
It rotates each bit in the destination to the right.
The LSB is shifted to the carry flag and to the MSB position.
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RCR:
The mnemonics is RCR destination, count.
It rotates each bit in the destination to the right along with carry.
The LSB is shifted to the carry flag and carry to the MSB position.
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These instructions are used to execute a group of instructions some number of time.
The instructions are,
S.No
Instruction Code
LOOP
LOOPE / LOOPZ
LOOPNE / LOOPNZ
Description
Loop through a
sequence of instructions
Loop through a
sequence of instructions
Loop through a
sequence of instructions
It sets the interrupt flag to one; this enables INTR interrupt of the 8086. STI
does not affect any other flag.
CLI: It resets the interrupt flag to zero. Due to this 8086 will not respond to an INTR
interrupt input. CLI does not affect any other flag.
WAIT: This cause the 8086 enter into idle condition up to TEST (low) pin low.
ESC:
LOCK:
NOP:
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X. INTERRUPT INSTRUCTIONS
INT:
INTO: If the overflow flag is set, this instruction will cause the 8086 to call a far
procedure.
IRET: It is used to end of the ISR to return execution to the main program/.
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INTERRUPT SYSTEM:
INTERRUPT is a signal applied / instruction given to the microprocessor to stop the current
process done by it and carry out a specific task requested by the interrupted device.
In response to an interrupt, the processor completes the execution of the current instruction and
transfers the program control to execute a procedure called ISR (Interrupt Service Routine).
After the complete execution of ISR, the processor returns the program control back to the
original suspended process.
A.HARDWARE INTERRUPTS:
There are two hardware interrupts in 8086 processor.
1. NMI Non maskable interrupt
2. INTR Interrupt
NMI interrupt has highest priority out of the two hardware interrupts.
When two or more interrupts are received from different I/O devices, Intel 8259 Programmable Interrupt Controller is used to handle multiple interrupts.
B.SOFTWARE INTERRUPTS:
There are 256 software interrupts with mnemonic INT followed by the interrupt
number.
Each software interrupt is two bytes long and it has a format as shown below.
Opcode for
INT
Interrupt
no. in HEX
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PREDEFINED INTERRUPTS:
The first five interrupts are reserved by INTEL for specific functions.
TYPE 0
TYPE 1
TYPE 2
TYPE 3
TYPE 4
:
:
:
:
:
INT 0
INT 1
INT 2
INT 3
INT 4
Divide by zero
Single step
Non maskable interrupt
Break point
Interrupt on Overflow
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Address
Interrupt
Description
00000H
00004H
00008H
0000CH
00010H
INT 00
INT 01
INT 02
INT 03
INT 04
00014H
INT 05 INT 1F
00080H
INT 20 INT FF
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Part A:
1. What are the segments registers in 8086?*
2. List the merits of Memory segmentation.*
3. Name the external hardware synchronization instruction 8086 processor.*
4. What is segment override prefix? Give an example.*
5. What is the function of TEST pin in 8086 processor?*
6. How does the 8086 processor access a word at on odd address?*
7. What are the differences between 8085 and 8086?*
8. Briefly explain the interrupts in 8086.
9. Draw the Flag register and label the flags with its bit positions.
10. What is minimum and maximum mode configuration?*
11. What is meant by pipelined architecture?
12. What is the significance of Trace flag in flag register of 8086?
13. What is the significance of Interrupt flag in flag register of 8086?
14. What is the significance of Direction flag in flag register of 8086?
Part B:
1. With neat diagram, explain the architecture of 8086 processor.*
2. Explain the instruction set of 8086 with examples.*
3. Explain the addressing modes of 8086 with examples.*
4. Explain the Interrupt structure of 8086 processor.*
5. Explain the memory segmentation in 8086.
6. Explain the minimum and maximum mode configuration of 8086 with neat diagrams.
(or)
Explain the working of 8086 in maximum mode.
Explain the working of 8086 in minimum mode.
7. Design an 8086 based system in minimum modes to interface 64 KB EPROM and
64KB RAM with starting address 00000H and 80000H respectively.*
* - AU questions
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