Con. N.B. ( ( 1. (a) (b) (c) (d) 2. (a) (b) 3. (a) (b) 4. (a) (b) 5. (a) (b) por RE[ETeX/ beat WIE [PEV ZO VLST. Design stick diagram 14 (Iz}1o0 6040-10. ( REVISED COURSE ) GT-8820 (3 Hours ) [ Total Marks : 100 (1) Question No. 1 is compulsory. 2) Attempt any four questions out of question nos. 2 to 7. 3) Draw neat diagrams wherever required. O° Compare lon Implantation and Diffusion © 20 Explain constant field scaling in MOS Device Draw stick Diagram for CMOS Invertor. ¢ Implement function using CMOS f = ab+abe+a_ Explain Twin tub process in detail 10 Calculate the threshold voltage Vio at Veg, a polysilicon gate N-channel 10 MOS transistor, with the following param’ Substrate doping density N, = 10° Polysilicon gate dopping density N 1020 cm-3, Gate oxide thickness tox = 300°A Oxide interface fixed charge 2 Nox = 4 x 101° cm? Draw circuit of 2 input NAND Wek Diagram and Layout 10 For a CMOS invertor find th n of operation :— 10 () Vin < Ven NK (ii) Via> Cop + Vip (iii) Vig = Va a (iv) Vig = Vin W) Va = og threshold Compare @Xgtive, Enhancement, Depletion load NMOS and CMOS invertor 10 Conside OS invertor with the following parameters -— 10 Vion = 0°6 V, ht, Cox = 60 wA/V? and (WIL), = 8 S Vip = -0-7 V, ti, Cox = 25 wA/V? and (WIL), = 12 Calculate the noise margins and the switching threshold (Vth) of this circuit. The power supply voltage is Vp, = 3:3 V. Write Verilog code of 1 Bit full adder using any style and instantiate it to design a 10 4 Bit full Adder. . Explain the method to design 4:1 MUX using pass transistor logic. Draw complete 10a s ( o s (b} 7 ed any three yh 4 Bit full Adder. Explain the method to design 4:1 MUX using pass transistor logic. DI stick diagram. Write Verilog code of 1 Bit full adder using any style and instantiate it to d co 10 Explain short channel effect in terms of :— 15 (i) Velocity Saturation S \ (ii) Mobility Degradation (iii) Channel Length Modulation (iv) Threshold Voltage. (v) Hot Electron Effect An NMOS transistor with Ey WV? and V,,, = 1-5V is operated at Vgg = 5V 5 and |p = 100 pA. S 20 RY re 2 and Butting contact Latchup in CMOS and prevention NcoMSare Semi custom and Full custom design. Generate Verilog code for 4 Bit Shift Register.