Roll No.:_ Amrita Vishwa Vidyapeetham B.Tech. Degree Examinations May 2011 a Sixth Semester EC302 VLSI Design (Common to Electronics and Communication Engineering and Electronics and Instrumentation Engineering) Time: Three hours Maximum:100 Marks Instructions: a. Questions are numbered from 1 to.19 as three parts A, B & C. Answer all questions. b. Selected important equations are given in the last page. Please make use of them. ¢. While writing the answers please write the question number properly. d. Every numerical answer must have proper unit. ©. You can use the following fundamental constants for calculating numerical answers. a. @) KT/q = 0.025V at 300° K b. 85 = 1.06 x 10? F/om c. €=3.98 where & = 8.85 x10 ™ F/em (permittivity of SiOz) @. Ni=145 x 10" em? at 300°K Answer all questions Part-A (10.x3 = 30 marks) 1. Identify the phases in VLSI design flow during which cach of the following tasks are carried out (i) Instruction set design of a processor (ii) Boolean logic minimization (iii) SPICE analysis, 2. In Fig 1, identify the region of operation of the transistor M2 and hence find the drain ‘cxrent through M2. Both the transistors have a threshold voltage of 0.3 V and B, = 600 3V 2V AL Fig. an cee MI 3. Draw the RC equivalent circuit of a metal interconnect line 50°pm lorig and 2 pm wide. ‘The thickness of the insulating oxide between the interconnect line and ground is 0.1 yim. ‘The sheet resistance of the process is 1 Ohm. The permittivity of the insulating oxide between the interconnect line and ground is 4x 107! F/m. 4, Draw the circuit of a pseudo nMOS inverter. How does noise margin get degraded in pseudo nMOS circuits? 5. Briefly explain the use of the LVS tool? 6. Determine the number of stages required in an inverter chain for minimal delay, if the input capacitance is 15 {F. The load to be driven is 200 fF. Ignore the effect of parasitics. R Page 1 of 47. The drain current in an nFET operating at saturation, changes by 150 1A for a change in Vos of 0.1 V when Vos = 2 V. Determine the value of B, for the device at this voltage if the threshold voltage Via= 0.3 V. 8. Calculate the power dissipated in a CMOS circuit operating at a frequency of 100 MHz. ‘The supply voltage is 2 V. The circuit drives a load of 100 fF. 9. How can threshold voltage be modified by (a) fabrication process (b) design 10. What is a Weinberger image array? Part-B 11. Analyze the following circuit shown in Fig 2 and identify it. aK ak a cuK | a 12, Use logical effort to determine the scaling factors of the gates in the following chain for minimum delay shown in Fig 3. (5x6=30 marks) Es ° | 2 Fig. 2 306 [~ 200 $F ent Fig3 13. (a) Draw the static characteristics of the inverter and mark the midpoint voltage. What is its significance? How are the characteristics affected by device sizing? (3 marks) (b) The unity slope points of an inverter occur at 2 V and 2.6 V. The circuit operates at a 7 supply voltage of 5 V. Draw a neat sketch marking Viz, Vo., Viry Vout and the noise margins for the circuit. @ marks) 4 Page 2 0f 414. Below is a circuit that has two registers and a combinational logic in between them. Also there is a clock skew as indicated in the Fig 4. Fig a. Whats the maximum operating frequency of the citcuit, assuming setup time and clock-to-q(ta) delay are 0's? b. Can the circuit operate with the clock period of 5 ns or lower? Justify your answer in either case of ‘yes? or ‘no’. 15. Briefly describe the operation of the 6T static RAM cell. How is the noise immunity of the system related to the “butterfly plot”? Part-C (4x 10 = 40 marks) 16. Determine the delay through the circuit given in Fig 5 for (i) a 0 to J transition at the input in (i) a 1 to 0 transition at the input in and hence the maximum frequency of operation of the circuit. All gates are scaled with respect to the minimum size itiverter. ‘The parameters for the IX minimum size inverter are given below. tho = 45 ps 5 ta = 22 ps; dan = 440; py = 880; Gate capacitances Cop = Con = 20 1F Fig5 17. Implement the truth table F (A, B, C) =¥ m(1,2,3,7) using a CMOS network. Draw its Buler graph and construct its layout. 18, (a) Draw a 3-input NAND gate using Dynamic logic gates. Discuss in detail the charge sharing problem associated with the structure. (S marks) (b) Implement the following truth table using a CMOS mirror citeiit. F (A,B, C)=E im, 1, 2,4) +E 67) marks). 19. With the help of neat sketches, describe the CMOS fabrication flow design. R > Page 3 of 4Important Equations All notations have their standard meanings NAND?2 rise and fall times t= G/2) to + (Gpu/m) Cr 5 te= 34+ Zon/m)Cr, NOR2 rise and fall times 0+ (2dtpe/m)CL, 5 te= (3/2)te + Gau/m)Cy, MOSFET current equations For nFET Ton = Bo/2 (Vesa — Vo)? Gin saturation region) = Pa/2 (20Vesn— Vin)Vosn— eae For pFET Ip = By/2 (Vsap — Vil)” (in saturation region) = By/2 [2/Vscip — [Vipl) Vsvp — Vsog") (in linear region) Inverter midpoint voltage Vae= {V0 [Vink + NB / Bp)}Ven}! (1+ Vn/ Bod treet Page 4 of 4