ECE 331 - Digital System Design: Multiplexers and Demultiplexers, and Encoders and Decoders

ECE 331 Digital System Design
Multiplexers and Demultiplexers,

and
Encoders and Decoders
(Lecture #15)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Material to be covered
Supplemental
Chapter 9: Sections 1 4
Fall 2010
ECE 331 - Digital System Design
Multiplexers
Fall 2010
Multiplexers
A multiplexer has
N control inputs
2N data inputs
1 output
A multiplexer routes (or connects) the selected

data input to the output.
Fall 2010
The value of the control inputs determines the

data input that is selected.
Multiplexers
Data
inputs
Control
input
Fall 2010
Z = A.I0 + A.I1
Multiplexers
MSB
I0
I1
I2
I3
LSB
Z = A.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

Fall 2010
Multiplexers
MSB
I0
I1
I2
I3
I4
I5
I6
I7
LSB
Z = A.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +

A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3
Fall 2010
Multiplexers
Fall 2010
8-to-1 Multiplexer in VHDL
Fall 2010
8-to-1 Multiplexer in VHDL
Fall 2010
10
Multiplexers
Exercise:
Design an 8-to-1 multiplexer using
4-to-1 and 2-to-1 multiplexers only.
Fall 2010
11
Multiplexers
Exercise:
Design a 16-to-1 multiplexer using
4-to-1 multiplexers only.
Fall 2010
12
Multiplexer (Bus)
Fall 2010
13
Demultiplexers
Fall 2010
14
Demultiplexers
A demultiplexer has
N control inputs
1 data input
2N outputs
A demultiplexer routes (or connects) the data input to

the selected output.
The value of the control inputs determines the output

that is selected.
A demultiplexer performs the opposite function of a

multiplexer.
Fall 2010
15
Demultiplexers
Out0
Out1
In
Out2
Out3
S1 S0
W
X
Y
Z
W = A'.B'.I
X = A.B'.I
Y = A'.B.I
Z = A.B.I
A B
Fall 2010
16
Decoders
Fall 2010
17
Decoders
A decoder has
N inputs
2N outputs
A decoder selects one of 2N outputs by

decoding the binary value on the N inputs.
The decoder generates all of the minterms of
the N input variables.
Exactly one output will be active for each

combination of the inputs.
What does active mean?
Fall 2010
18
Decoders
Out0
I0
Out1
I1
Out2
Out3
msb
W = A'.B'
W
X
Y
Z
X = A.B'
Y = A'.B
Z = A.B
Active-high outputs
Fall 2010
19
Decoders
Out0
I0
Out1
I1
Out2
Out3
msb
W = (A'.B')'
W
X
Y
Z
X = (A.B')'
Y = (A'.B)'
Z = (A.B)'
Active-low outputs
Fall 2010
20
Decoders
msb
Fall 2010
21
3-to-8 Decoder in VHDL
Fall 2010
22
3-to-8 Decoder in VHDL
Fall 2010
23
Decoder with Enable
Out3
W
X
Y
Z
high-level
enable
enabled
disabled
Fall 2010
I0
I1
Out0
Out1
Out2
Enable
En
En
24
Decoder with Enable
Out3
W
X
Y
Z
low-level
enable
enabled
disabled
Fall 2010
I0
I1
Out0
Out1
Out2
Enable
En
En
25
2-to-4 Decoder with Enable in VHDL
Fall 2010
26
Decoders
Exercise:
Design a 4-to-16 decoder using
2-to-4 decoders only.
Fall 2010
27
Encoders
Fall 2010
28
Encoders
An encoder has
2N inputs
N outputs
An encoder outputs the binary value of the selected

(or active) input.
An encoder performs the inverse operation of a
decoder.
Issues
Fall 2010
What if more than one input is active?
What if no inputs are active?

29
Encoders
Fall 2010
I0
I1
I2
I3
Out0
Out1
Z
Y
30
Priority Encoders
If more than one input is active, the higher-order input

has priority over the lower-order input.
The higher value is encoded on the output
A valid indicator, d, is included to indicate whether or

not the output is valid.
Output is invalid when no inputs are active
d=0
Output is valid when at least one input is active
d=1
Why is the valid indicator needed?
Fall 2010
31
Priority Encoders
msb
Valid bit
Fall 2010
32
VHDL: 4-to-2 Priority Encoder

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT (
w
y
z
END priority ;
4 input bits
: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
: OUT
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
: OUT
STD_LOGIC ) ;
valid indicator
ARCHITECTURE Behavior OF priority IS

BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END Behavior ;
2 output bits
Active-high
inputs and outputs
33
Designing logic circuits using multiplexers
Fall 2010
34
Using an n-input Multiplexer
Use an n-input multiplexer to realize a logic circuit for

a function with n minterms.
Each minterm of the function can be mapped to an

input of the multiplexer.
For each row in the truth table, for the function, where
the output is 1, set the corresponding input of the
multiplexer to 1.
m = 2n, where m = # of variables in the function
That is, for each minterm in the minterm expansion of the

function, set the corresponding input of the multiplexer to 1.
Set the remaining inputs of the multiplexer to 0.
Fall 2010
35
Using an n-input Mux
Example:
Using an 8-to-1 multiplexer, design a logic circuit
to realize the following Boolean function
F(A,B,C) = m(2, 3, 5, 6, 7)
Fall 2010
36
Using an n-input Mux
Example:
Using an 8-to-1 multiplexer, design a logic circuit
F(A,B,C) = m(1, 2, 4)
Fall 2010
37
Using an (n / 2)-input Multiplexer
Use an (n / 2)-input multiplexer to realize a logic

circuit for a function with n minterms.
m = 2n, where m = # of variables in the function
Group the rows of the truth table, for the function, into
(n / 2) pairs of rows.
Each pair of rows represents a product term of (m 1)

variables.
Each pair of rows can be mapped to a multiplexer input.
Determine the logical function of each pair of rows in

terms of the mth variable.
Fall 2010
If the mth variable, for example, is x, then the possible

values are x, x', 0, and 1.
38
Using an (n / 2)-input Mux

Example: F(x,y,z) = m(1, 2, 6, 7)
Fall 2010
39

Example: F(A,B,C,D) = m(1,3,4,11,1215)
Fall 2010
40
The design of a logic circuit using an (n / 2)-input

multiplexer can be easily extended to the use of
an (n / 4)-input multiplexer.
Fall 2010
41
Designing logic circuits using decoders
Fall 2010
42
Using an n-output Decoder
Use an n-output decoder to realize a logic circuit for a

function with n minterms.
Each minterm of the function can be mapped to an
output of the decoder.
For each row in the truth table, for the function, where
the output is 1, sum (or OR) the corresponding outputs
of the decoder.
That is, for each minterm in the minterm expansion of the

function, OR the corresponding outputs of the decoder.
Leave remaining outputs of the decoder unconnected.
Fall 2010
43
Example:
Using a 3-to-8 decoder, design a logic circuit to
realize the following Boolean function
F(A,B,C) = m(2, 3, 5, 6, 7)
Fall 2010
44
Example:
Using two 2-to-4 decoders, design a logic circuit
F(A,B,C) = m(0, 1, 4, 6, 7)
Fall 2010
45
Questions?
Fall 2010
46

ECE 331 - Digital System Design: Multiplexers and Demultiplexers, and Encoders and Decoders

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ECE 331 - Digital System Design: Multiplexers and Demultiplexers, and Encoders and Decoders

Uploaded by

Copyright:

Available Formats

ECE 331 Digital System Design

Multiplexers and Demultiplexers,

ECE 331 - Digital System Design

ECE 331 - Digital System Design

A multiplexer routes (or connects) the selected

The value of the control inputs determines the

Z = A.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

ECE 331 - Digital System Design

Z = A.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +

ECE 331 - Digital System Design

ECE 331 - Digital System Design

8-to-1 Multiplexer in VHDL

ECE 331 - Digital System Design

8-to-1 Multiplexer in VHDL

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

A demultiplexer routes (or connects) the data input to

The value of the control inputs determines the output

A demultiplexer performs the opposite function of a

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

A decoder selects one of 2N outputs by

Exactly one output will be active for each

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

3-to-8 Decoder in VHDL

ECE 331 - Digital System Design

3-to-8 Decoder in VHDL

ECE 331 - Digital System Design

Decoder with Enable

ECE 331 - Digital System Design

Decoder with Enable

ECE 331 - Digital System Design

2-to-4 Decoder with Enable in VHDL

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

An encoder outputs the binary value of the selected

What if more than one input is active?

What if no inputs are active?

ECE 331 - Digital System Design

If more than one input is active, the higher-order input

The higher value is encoded on the output

A valid indicator, d, is included to indicate whether or

Output is invalid when no inputs are active

ECE 331 - Digital System Design

ECE 331 - Digital System Design

VHDL: 4-to-2 Priority Encoder

ARCHITECTURE Behavior OF priority IS

Designing logic circuits using multiplexers

ECE 331 - Digital System Design

Using an n-input Multiplexer

Use an n-input multiplexer to realize a logic circuit for

Each minterm of the function can be mapped to an

m = 2n, where m = # of variables in the function

That is, for each minterm in the minterm expansion of the

Set the remaining inputs of the multiplexer to 0.