KIM TRA CUI K MN KIN TRC MY TNH

Hc k II, nm hc 2010-2011
Thi gian: 90 pht
Sinh vin c xem ti liu
Bi 1 (3 im):
Mt h thng my tnh c t chc cache d liu (data cache) mc 1 vi 64KB, mi block gm 32bytes.
H thng dng CPU 16 bit c 24 ng a ch truy xut b nh. Mi ln truy xut l 2 bytes (tc l
mi a ch tng ng truy xut 2 bytes).
a). Gi s cache ny c t chc theo phng thc 4-way set associative. Trnh by khung a ch, ch r
s bit cho Tag, Set, Block Offset. (1 im)
64KB = 2^16 bytes.
1 block = 32bytes = 2^5bytes.
=> S block = 2^16/2^5= 2^11
=> S set = 2^11/4 = 2^9
=> Set = d = 9 bits
V CPU truy xut 1 ln l 2 bytes nn s bit w cho Block Offset l 5 1 = 4 bits
Tag = 24 9 4 = 11 bits
b). Ngi ta thm vo mt t chc cache lnh (instruction cache) mc 1 v sau tin hnh chy 1
benchmark trn h thng my tnh ny v thng k c cc lnh truy xut b nh (lnh load v store)
chim 40% ton b lnh. T l miss o c cho cache lnh v d liu tng ng l 5% v 10%. CPU s
dng clock 2GHz. CPI (Clock Cycles Per Instruction) khi khng c miss xy ra l 1. Thi gian truy xut
b nh ngoi mt 100ns khi b miss. Tnh CPI trung bnh khi chy benchmark ny. (2 im)
2GHz ~0.5ns
Chu k truy xut b nh ngoi = 100ns/0.5ns = 200 cycles
i vi t chc cache lnh:
Khi miss xy ra, s chu k trung bnh cn phi thc hin thm l: 5% * 200 = 10 cycles
i vi t chc cache d liu:
Khi miss xy ra, s chu k trung bnh cn phi thc hin thm l: 40% * 10% * 200 = 8 cycles
Vy CPI trung bnh cho benchmark l: CPI total = 1 + 10 + 8 = 19 cycles
Bi 4 (1 im):
Ch r cc ph thuc (dependences) cho on m sau. Trong cc ph thuc , ci no s gy ra hazard.
I1: sub $4, $1, $2
I2: and $3, $4, $5
I3: or

$2, $1, $4

I4: add $13, $4, $4

I5: sw

$11, 50($4)

Tt c cc lnh sau lnh I1 c thanh ghi $4 ph thuc vo lnh sub.

Hazard s xy ra i vi lnh I2, I3, I4.
Bi 2 (3 im):
Mt my tnh s dng CPU 16 bit, CPU giao tip vi b nh chnh thng qua 16 ng a ch, 3 tn hiu
iu khin tch cc mc thp ln lt l tn hiu c (RD), tnh hiu ghi (WR), v tn hiu yu cu truy
xut b nh (MREQ). Xc nh tm a ch lm cho cc tn hiu CS1, CS2, CS3 tch cc thp ca mch
gii m sau. ADDR[0:15] l tn hiu a ch A0A15.
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CS1 = [0x0800-0x0FFF] U [0x2800-0x2FFF]

CS1 = A15 + A14 + A12 + !A11
CS2 = [0x1800-0x1FFF] U [0x3800-0x3FFF]
CS2 = A15 + A14 + !A12 +!A11
CS3 = [0xC000-0xFFFF]
CS3 = !A15 + !A14
Bi 4 (3 im):
Mt b nh my tnh c t chc cache data (D-Cache) mc 1 theo dng direct mapping, dng Write-Back
cho c Write Hit v Miss nh hnh v bn di. Trong kch thc ca Valid v Dirty l 1 bit. Mi
Read/Write trn b nh (Memory) l 1 byte. Address l 16 bit. Gi s ti thi im ny, d liu trn cache
nh hnh v. B nh lu theo dng Little-Endian.
a). Khi vi x l pht lnh Read ti a ch 0x1FE2. Cache s b Hit hay Miss. Lc ny trn Cache, Line
no s c cp nht v thng tin cp nht l g? Gi s d liu 4 byte ti a ch bt u 0x1FE0 trn b
nh l 0x22113344.
0x1FE2 = 0001111111 1000 10
c vo line 8, v Valid = 0 nn b Miss. CPU s c 4 bytes ti a ch bt u 0x1FE0 v thng tin c
cp nht li l
1 (valid) | 0 (dirty) | 0001111111 (tag) | 0x22113344 (data)
b). Vi x l pht lnh Write ti a ch 0x7501. D liu cho lnh Write ny l 1 byte 0xFF. Cache s b
Hit hay Miss. Lc ny trn Cache, Line no s c cp nht v thng tin cp nht l g?
0x7501 = 0111010100 0000 01.
Line l 0. Valid = 1, Tag = 0111010100 nn Cache s b hit. Thng tin cp nht l
1 (valid) | 1 (dirty) | 0111010100 (tag) | 0x1122FF44 (data)
c). Vi x l pht lnh Write ti a ch 0xD4E9. D liu cho lnh Write l 1 byte 0xAE. Cache s b Hit
hay Miss. Lc ny trn Cache, Line no s c cp nht v thng tin cp nht l g? Qu trnh g s din
ra trn b nh. Gi s d liu 4 byte ti a ch bt u 0xD4E8 trn b nh l 0x22222222.
0xD4E9 = 1101010011 1010 01
Line l 10, Tag = 0001010011 <> 1101010011. Cache b Miss. V Dirty bit = 1. Lc ny d liu 4 bytes
trn Line 10 = 0x12345678 s c ghi xung b nh ti a ch bt u 0x14E8. Sau d liu 4 byte ti
a ch bt u 0xD4E8 s c c ln cache. Lc ny thng tin c cp nht ti Line 10 l:
1 (valid) | 0 (dirty) | 1101010011 (tag) | 0x22222222 (data)
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Sau n s cp nht byte data 0xAE ti byte offset l 1, v cp nht dirty bit = 1
1 (valid) | 1 (dirty) | 1101010011 (tag) | 0x2222AE22 (data)
Ch : Khi Valid = 0, cache line khng hp l, lc ny truy xut s b Miss. Khi Dirty = 1, d liu ca
cache line b thay i.
Memory
16

Address

15 14 7 6

5432

10

Tag

Index

Byte
Offset

0x0000
0x0004
0x0008

0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX

0xFFF8
0xFFFC

0xXXXXXXXX
0xXXXXXXXX

Cache
Valid Dirty
10

Tag

Data

01 1101 0100

0x11223344

0
0
0
1
1
1
0
0
1
1
1
1
0
0
0

1
1
1
1
0
0
0
1
1
1
1
1
1
1
1

00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000
00 0101 0011
00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000
00 0000 0000

0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0x12345678
0x1ABFE000
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0x12345678
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF

8
Data

Write back
=
Hit/Miss

-----------------------ht----------------------Trang

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