Digital Integrated Circuits

Digital Integrated
Circuits
Jan M. Rabaey
AAnantha
Design
Perspective
Chandrakasan
Borivoje Nikolic
Introduction
July 30, 2002
EE141 Integrated Circuits2nd
Digital
1
Introduction
What is this book all about?
Introduction to digital integrated circuits.

CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design
methodologies.
What will you learn?

Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability

Digital
2
Introduction
Digital Integrated Circuits

Introduction: Issues in digital design
The CMOS inverter
Combinational logic structures
Sequential logic gates
Design methodologies
Interconnect: R, L and C
Timing
Arithmetic building blocks
Memories and array structures

Digital
3
Introduction
Introduction
Why
is designing
digital ICs different
today than it was
before?
Will it change in
future?

Digital
4
Introduction
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
Digital
5
Introduction
ENIAC - The first electronic computer (1946)

Digital
6
Introduction
The Transistor Revolution
First transistor
Bell Labs, 1948

Digital
7
Introduction
The First Integrated Circuits

Bipolar logic
1960s
ECL 3-input Gate

Motorola 1966

Digital
8
Introduction
Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

Digital
9
Introduction
Intel Pentium (IV) microprocessor

Digital
10
Introduction
Moores Law
In
1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months

Digital
11
Introduction
LOG2 OF THE NUMBER OF

COMPONENTS PER INTEGRATED FUNCTION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Digital
1975
1974
1973
1972
1971
1970
1969
1968
1967
1966
1965
1964
1963
1962
1961
1960
1959
Moores Law
Electronics, April 19, 1965.
12
Introduction
Evolution in Complexity

Digital
13
Introduction
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i386
80286
100
10
i486
Pentium III
Pentium II
Pentium Pro
Pentium
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
Digital
Courtesy, Intel
14
Introduction
Moores law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
P6
Pentium proc
386
286
0.1
8086
8085
Transistors
on Lead Microprocessors double every 2 years
0.01
8080
8008
4004
0.001
1970

Digital
1980
1990
Year
Courtesy, Intel
2000
2010
15
Introduction
Die Size Growth

Die size (mm)
100
10
8080
8008
4004
8086
8085
286
386
P6
Pentium
proc
486
~7% growth per year

~2X growth in 10 years
1
1970
1980
1990
Year
2000
2010
Die size grows by 14% to satisfy Moores Law

Digital
Courtesy, Intel
16
Introduction
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
10
8085
1
0.1
1970
8086 286
386
486
P6
Pentium proc
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years

Digital
Courtesy, Intel
17
Introduction
Power Dissipation
Power (Watts)
100
P6
Pentium proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase

Digital
Courtesy, Intel
18
Introduction
Power will be a major problem

100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
Pentium proc
100
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive

Digital
Courtesy, Intel
19
Introduction
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp

Digital
Courtesy, Intel
20
Introduction
Not Only Microprocessors

Cell
Phone
Small
Signal RF
Digital Cellular Market

(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000

Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)

Digital
21
Introduction
Challenges in Digital Design

DSM
1/DSM
Macroscopic Issues
Microscopic Problems
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.
Ultra-high speed design

Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.
Everything Looks a Little Different
?
Digital
and Theres a Lot of Them!
22
Introduction
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
Complexity
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity

Digital
Courtesy, ITRS Roadmap
23
Introduction
Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But
How to design chips with more and more functions?

Design engineering population does not double every
two years
Hence, a need for more efficient design methods

Exploit different levels of abstraction

Digital
24
Introduction
Design Abstraction Levels

SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+

Digital
D
n+
25
Introduction
Design Metrics
How
to evaluate performance of a
digital circuit (gate, block, )?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function

Digital
26
Introduction
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs

design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area

Digital
27
Introduction
NRE Cost is Increasing

Digital
28
Introduction
Die Cost
Single die
Wafer
Going up to 12 (30cm
From http://www.amd.com

Digital
29
Introduction
Cost per Transistor

cost:
-per-transistor
1
0.1
Fabrication capital cost per transistor (Moores law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985

Digital
1988
1991
1994
1997
2000
2003
2006
2009
2012
30
Introduction
Yield
No. of good chips per wafer
Y
100%
Total number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield
wafer diameter/2 2 wafer diameter

Dies per wafer
die area
2 die area

Digital
31
Introduction
Defects
defects per unit area die area

die yield 1
is approximately 3
die cost f (die area)4
Digital
32
Introduction
Some Examples (1994)

Chip
Metal Line
layers width
Wafer
cost
Def./ Area Dies/ Yield

cm2 mm2 wafer
Die
cost
386DX
0.90
$900
1.0
43
360
71%
$4
486 DX2
0.80
$1200
1.0
81
181
54%
$12
Power PC
601
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
0.70
$1700
1.6
256
48
13%
$272
Pentium
0.80
$1500
1.5
296
40
9%
$417

Digital
33
Introduction
Reliability
Noise in Digital Integrated Circuits
v(t)
i(t)
Inductive coupling

Digital
Capacitive coupling
V DD
Power and ground

noise
34
Introduction
DC Operation
Voltage Transfer Characteristic
V(y)
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)
OH
V(y)=V(x)
VM Switching Threshold
V OL
V OL
OH
V(x)
Nominal Voltage Levels

Digital
35
Introduction
Mapping between analog and digital signals

V
1
V
OH
V
IH
out
OH
Slope = -1
Undefined
Region
V
0
Slope = -1
IL
V
OL
OL
V

Digital
IL
IH
in
36
Introduction
Definition of Noise Margins

"1"
V
OH
NM H
NM L
OL
Noise margin high

IH
Undefined
Region
IL
Noise margin low
"0"
Gate Output

Digital
Gate Input
37
Introduction
Noise Budget
Allocates
gross noise margin to

expected sources of noise
Sources: supply noise, cross talk,
interference, offset
Differentiate between fixed and
proportional noise sources

Digital
38
Introduction
Key Reliability Properties
Absolute noise margin values are deceptive

a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)
Noise immunity is the more important metric

the capability to suppress noise sources
Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the

receiver;

Digital
39
Introduction
Regenerative Property
out
out
v3
v3
f(v)
v1
finv(v)
v1
finv(v)
v2
Regenerative
Digital
v3
f(v)
v0
Non-Regenerative
40
Introduction
Regenerative Property
v0
v1
v2
v3
v4
v5
v6
A chain of inverters
V (Volt)
5
v0
v1
Simulated
21
response 0

Digital
6
t (nsec)
v2
8
10
41
Introduction
Fan-in and Fan-out
Fan-out N
Digital
Fan-in M
42
Introduction
The Ideal Gate

V out
Ri =
Ro = 0
Fanout =
NMH = NML = VDD/2
g=
V in

Digital
43
Introduction
An Old-time Inverter
5.0
4.0
NM L
3.0
2.0
VM
1.0
0.0

Digital
1.0
NM H
2.0
3.0
V in (V)
4.0
5.0
44
Introduction
Delay Definitions
V in
50%
t
V out
tpHL
tpLH
90%
50%
t
10%
tf
Digital
tr
45
Introduction
Ring Oscillator
v0
v1
v0
v2
v1
v3
v4
v5
v5
T = 2 tp N
Digital
46
Introduction
A First-Order RC Network
R
vin
vout
C
tp = ln (2) = 0.69 RC
Important model matches delay of inverter

Digital
47
Introduction
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t T
1 t T
Pave
p (t )dt
isupply t dt
t
T t
T
Digital
48
Introduction
Energy and Energy-Delay

Power-Delay Product (PDP) =
E = Energy per operation = Pav tp
Energy-Delay Product (EDP) =
quality metric of gate = E tp

Digital
49
Introduction
A First-Order RC Network
Vdd
R PMOS
A1
vAinN
E0>1=C LVdd2
NETWORK
NMOS
vout supply
CVLout
CL
NETWORK
Vdd
T
T
E = P t dt = V i
t dt = V
C dV
= C V 2
0 1
dd sup ply
dd
L out
L
dd
0
0
0
T
T
Vdd
1
2
t dt = V
t dt = C V
E
= P
i
dV
= C V
ca p
cap
out ca p
L out out
dd
2 L
0
0
0

Digital
50
Introduction
Summary
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and

potential solutions is the purpose of this book
Understanding the design metrics that govern

digital design is crucial
Cost, reliability, speed, power and energy
dissipation

Digital
51
Introduction

Digital Integrated Circuits

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Digital Integrated

What is this book all about?

Introduction to digital integrated circuits.

What will you learn?

EE141 Integrated Circuits2nd