Logic Utilization:

Total Number Slice Registers:

196 out of 9,312
2%
Number used as Flip Flops:
195
Number used as Latches:
1
Number of 4 input LUTs:
324 out of 9,312
3%
Logic Distribution:
Number of occupied Slices:
222 out of 4,656
4%
Number of Slices containing only related logic:
222 out of
222 100%
Number of Slices containing unrelated logic:
0 out of
222 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs:
421 out of 9,312
4%
Number used as logic:
324
Number used as a route-thru:
97
Peak Memory Usage: 252 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion: 2 secs