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CH 01
CH 01
(A-405)
melee@kut.ac.kr
1-2
Class Overview
Contents
Chap. 1 Digital Logic Circuits
z The fundamental knowledge needed for the design of digital systems constructed with individual
gates and flip-flops.
Chap. 2 Digital Components
z The logical operation of the most common standard digital components(Decoders, Multiplexers,
Registers, Counters, and Memories).
z These digital components are used as building blocks for the design of larger units(Mano
Machine).
Chap. 3 Data Representation
z Various data types found in digital computers are represented in binary form in computer
registers.
Chap. 4 Register Transfer and Microoperations
z A register transfer language is used to express microoperations in symbolic form.
z Symbols are defined for arithmetic, logic, and shift microoperations.
z To show the hardware design of the most common microoperations, a composite arithmetic logic
shift unit is developed.
Chap. 5 Basic Computer Organization and Design
z The organization and design of a basic digital computer(Mano Machine).
z Register transfer language is used to describe the internal operation of the computer.
z By going through the detailed steps of the design presented in this chapter, the student will be
able to understand the inner workings of digital computers.
1-3
Class Overview
Chap. 6 Programming the Basic Computer
z The 25 instructions of the basic computer to illustrate techniques used in assembly language
programming.
z Programming examples are presented for a number of data processing tasks.
z The basic operations of an assembler are presented to show the translation from symbolic code
to an equivalent binary program.
Chap. 7 Microprogrammed Control
z Introduction to the concept of microprogramming.
z A specific microprogrammed control unit is developed to show by example how to write
microcode for a typical set of instructions.
z The design of the control unit is carried-out in detail.
Chap. 8 Central Processing Unit
z CPU as seen by the user(ISA).
z General register organization, the operation of memory stack, variety of addressing modes,
instruction format.
z The Reduced Instruction Set Computer(RISC) concept.
1-4
Class Overview
1-5
Class Overview
Chapter in detail
Chap. 6 : ISA
Chap. 8 and 9 : CPU
Chap. 11 : I/O
Chap. 12 : Memory
1-6
Class Overview
Computer Architecture
z Instruction Set Architecture (ISA) : S/W
z Machine Organization : H/W and Design
functional behavior, as distinct from the organization of the data flows and controls, the
logic design, and the physical implementation.
Machine Organization?
CPU(Control & Data path), Memory, Input/Output
Class Overview
1-7
8 Student Types
1-8
Insecure: 25 %
Silent: 20 %
Independent: 12 %
Friendly: 11 %
Obedient: 10 %
Heroic: 9 %
Critic: 9 %
Unmotivated: 4 %
- Michigan State University
1-9
Application S/W
API
Operating System
ROM BIOS
Computer H/W
1-10
continued
Computer Hardware(H/W)
CPU
Memory
z Program Memory(ROM)
z Data Memory(RAM)
Memory
I/O Device
z Interface: 8251 SIO, 8255 PIO,
6845 CRTC, 8272 FDC, 8237
DMAC, 8279 KDI
z
CPU
Input
Device
Interface
or IOP
Output
Device
1-11
Physical Quantity
V, A, F,
0 : 0.5v
Binary Information
Discrete Value
1 : 3v
Gate
The manipulation of binary information is done by logic circuit called
gate.
Blocks of H/W that produce signals of binary 1 or 0 when input logic
requirements are satisfied.
Digital Logic Gates : Fig. 1-2
z
x
y
xy
x
y
xy
1-12
Boolean Algebra
Deals with binary variable (A, B, x, y: T/F or 1/0) +
George Boole
Born: 2 Nov 1815 in Lincoln,
Lincolnshire, England
Died: 8 Dec 1864 in Ballintemple,
County Cork, Ireland
1-13
2n Combination
Variable n = 3
x y z
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x
y
1-14
Algebraic form
Logic diagram (input-output relationship : Fig. 1-3b)
Algebraic form
Find simpler circuits for the same function : by using Boolean algebra rules
( A U B ) c = Ac I B c
1-15
[]
F= AB + CD + AB + CD
= x + x (let x= AB + CD)
=x
= AB + CD
F= ABC + ABC + AC
(x+y+z)
x
y
z
(a) OR-invert
Fig. 1-6(a)
[]
x yz =(x+y+z)
(b) invert-AND
(xyz)
(a) AND-invert
Computer System Architecture
x
y
z
(x+y+z) = (xyz)
(b) invert-OR
Chap. 1 Digital Logic Circuits
1-16
Karnaugh Map(K-Map)
Map method for simplifying Boolean expressions
Minterm / Maxterm
Minterm : n variables product ( x=1, x=0)
Maxterm : n variables sum (x=0, x=1)
2 variables example
x
0
y
0
Minterm
x'y'
m0
Maxterm
x +y
M0
x'y
m1
x + y'
M1
x y'
m2
x'+ y
M2
x y
m3
x'+ y'
M3
F = xy + xy
m1
M0 M1 M2 M3
m3
= (1,3)
= (0,2)
Computer System Architecture
m0 + m1 + m2 + m3
( m1 +
m3 )
(Complement = M0
M2 )
1-17
Map
3 variables
2 variables
B
4 variables
C
6
A
5 variables
12 13 15 14
8
11 10
D
11 10 14 15 13 12
24 25 27 26 30 31 29 28
16 17 19 18 22 23 21 20
E
1-18
[] F= x + yz
(2) F ( x , y , z ) = (1,4,5,6,7 )
y
0
z
0
F
0
Minterm
m1
m2
m3
m4
m5
m6
m7
(3)
y
m0
F= x + yz
1-19
Adjacent Square
Number of square = 2n (2, 4, 8, .)
0
12
13
15
14
11
10
be considered to be adjacent
12
13
15
14
11
10
1-20
[] F ( A, B, C ) = (3,4,6,7)
F=AC + BC
[] F ( A, B, C , D ) = (0,1,2,6,8,9,10)
Product-of-Sums Simplification
F ( A, B, C , D ) = (0,1,2,5,8,9,10)
F=BD + BC + ACD
Product of Sum
Computer System Architecture
12
13
15
14
11
10
Sum of product
F=BD + BC + ACD
[] F ( A, B, C ) = (0,2,4,5,6)
F=C + AB
12
13
15
14
11
10
D
Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.
1-21
NAND Implementation
Sum of Product : F=BD + BC + ACD
B
D
C
A
D
NOR Implementation
Product of Sum : F=(A + B)(C + D)(B + D)
A
B
C
D
(1, 3, 5)
(0, 1, 2, 3, 6)
Chap. 1 Digital Logic Circuits
X
X
1
5
C
Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.
1-22
Combinational Circuits
A connected arrangement of logic gates with a set of inputs and outputs
in
Combinational
Circuits
(Logic Gates)
f0
f1
fm
Analysis
Logic circuits diagram
...
i0
i1
...
Design(Analysis )
Experience
1-23
Input
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
Output
C
S
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
C= xyz + xyz + xy
=z(xy + xy) + xy
=z(x y) + xy
z
s
Computer System Architecture
1-24
1-6 Flip-Flops
Flip-Flop
SR(Set/Reset) F/F
S
SET
CLR
Q
Q
S
0
0
1
1
R
0
1
0
1
Q(t)
0
1
?
D(Data) F/F
D
Q(t+1)
no change
clear to 0
set to 1
Indeterminate
SET
CLR
Q
Q
JK(Jack/King) F/F
J
SET
CLR
Q
Q
J
0
0
1
1
K
0
1
0
1
Q(t+1)
Q(t) no change
0
clear to 0
1
set to 1
Q(t)' Complement
0
1
Q(t+1)
clear to 0
set to 1
D
0
1
: 1) Disable Clock
2) Feedback output into input p.52
T(Toggle) F/F
T
SET
CLR
T
0
1
Q(t+1)
Q(t) no change
Q'(t) Complement
1-25
Edge-Triggered F/F
State Change : Clock Pulse
z Rising Edge(positive-edge transition)
z Falling Edge(negative-edge transition)
ts
th
Setup time(20ns)
z minimum time that D input must remain at constant value before the
transition.
Hold time(5ns)
z minimum time that D input must not change after the positive transition.
Propagation delay(max 50ns)
z time between the clock input and the response in Q
z gate 2-20 ns setup hold time F/F
gate .
Master-Slave F/F
z 2 F/F (Slave Master F/F) negative-edge transition
z : Race
1-26
Race
- Hold time > Propagation delay
- 0 1 Unstable
- Edge triggered F/F (with little or no hold time) Master/Slave
F/F
: 7470(J-K Edge triggered F/F), 7471(J-K Master/Slave F/F)
Excitation Table
Required input combinations for a given change of state
Present State Next State
SR F/F
Q(t) Q(t+1)
S
0
0
0
0
1
1
1
0
0
1
1
X
Dont Care
R
X
0
1
0
JK F/F
Q(t) Q(t+1)
J
0
0
0
0
1
1
1
0
X
1
1
X
0 : Set to 1
1 : Complement
K
X
X
1
0
D F/F
Q(t) Q(t+1)
0
0
0
1
1
0
1
1
D
0
1
0
1
T F/F
Q(t) Q(t+1)
0
0
0
1
1
0
1
1
T
0
1
1
0
1 : Clear to 0
0 : No change
1-27
Input
Combinational
Circuit
Output
Flip-Flops
Clock
DA
Input Equation
z DA = Ax + Bx, DB = Ax
Output Equation
z y = Ax + Bx
CLR
DB
SET
SET
Clock
CLR
circuit
1-28
State Table
State Diagram
Graphical representation of state
table
z Circle(state), Line(transition),
I/O(input/output)
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Input
x
0
1
0
1
0
1
0
1
Input Equ.
Ax
0
0
0
0
0
1
0
1
Bx
0
0
0
1
0
0
0
1
DA
0
0
0
1
0
1
0
1
Next State
DB
0
1
0
1
0
0
0
0
A
0
0
0
1
0
1
0
1
B
0
1
0
1
0
0
0
0
Output
y
0
0
1
0
1
0
1
0
0/0
00
00, 01, ..
x=0: no change
x=0 0/00
x=0
00
11
x=1
01
x=1
x=0
Computer System Architecture
x=1
0/1 1/0
Next State =
Output
Present State
x=1 1/01
K
X
X
1
0
01
0/1
0/1
1/0
10
1/0
11
State Diagram:
JK F/F
Q(t) Q(t+1)
J
0
0
0
0
1
1
1
0
X
1
1
X
1/0
10
x=0
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Input
x
0
1
0
1
0
1
0
1
Next State u
F/F Input
KA
A
B
JA
0
0
0
x
0
1
0
x
0
1
0
x
1
0
1
x
1
0
x
0
1
1
x
0
1
1
x
0
0
0
x
1
JB
0
1
x
x
0
1
x
x
KB
x
x
0
1
x
x
0
1
1-29
Logic Diagram
B
JA
A
1
X
KA
A
1
5
X
1
3
7
1 X X
5
7
6
1 X X
KB
A
JB=x
X X 1
4
5
X X 1
CLR
KA=Bx
JA=Bx
0
SET
JB
KA=x
SET
CLR
Clock
1. The Problem is stated
2. I/O variables are assigned
3. Truth table(I/O relation)
4. Simplified Boolean Function
5. Logic circuit diagram