Opcode

AND<cond><S> Rd, Rn, Rm OP #

AND<cond><S> Rd, Rn, Rm OP Rs
MUL<cond><S> Rd, Rm, Rs
STR<cond>H Rd, <address>
LDR<cond>H Rd, <address>
Undefined Instruction
LDR<cond>SB Rd, <address>
Undefined Instruction
LDR<cond>SH Rd, <address>
EOR<cond><S> Rd, Rn, Rm OP #
EOR<cond><S> Rd, Rn, Rm OP Rs
MLA<cond><S> Rd, Rm, Rs, Rn
SUB<cond><S> Rd, Rn, Rm OP #
SUB<cond><S> Rd, Rn, Rm OP Rs
RSB<cond><S> Rd, Rn, Rm OP #
RSB<cond><S> Rd, Rn, Rm OP Rs
ADD<cond><S> Rd, Rn, Rm OP #
ADD<cond><S> Rd, Rn, Rm OP Rs
UMULL<cond><S> RdLo, RdHi, Rm, Rs
ADC<cond><S> Rd, Rn, Rm OP #
ADC<cond><S> Rd, Rn, Rm OP Rs
UMLAL<cond><S> RdLo, RdHi, Rm, Rs
SBC<cond><S> Rd, Rn, Rm OP #
SBC<cond><S> Rd, Rn, Rm OP Rs
SMULL<cond><S> RdLo, RdHi, Rm, Rs
RSC<cond><S> Rd, Rn, Rm OP #
RSC<cond><S> Rd, Rn, Rm OP Rs
SMLAL<cond><S> RdLo, RdHi, Rm, Rs
TST<cond> Rn, Rm OP #
TST<cond> Rn, Rm OP Rs
MRS<cond> Rd, CPSR
SWP<cond> Rd, Rm, [Rn]
TEQ<cond> Rn, Rm OP #
TEQ<cond> Rn, Rm OP Rs
MSR<cond> CPSR_<fields>, Rm
BX<cond> Rm
CMP<cond> Rn, Rm OP #
CMP<cond> Rn, Rm OP Rs
MRS<cond> Rd, SPSR
SWP<cond>B Rd, Rm, [Rn]
CMN<cond> Rn, Rm OP #
CMN<cond> Rn, Rm OP Rs
MSR<cond> SPSR_<fields>, Rm
ORR<cond><S> Rd, Rn, Rm OP #
ORR<cond><S> Rd, Rn, Rm OP Rs
MOV<cond><S> Rd, Rm OP #
MOV<cond><S> Rd, Rm OP Rs
BIC<cond><S> Rd, Rn, Rm OP #
BIC<cond><S> Rd, Rn, Rm OP Rs
MVN<cond><S> Rd, Rm OP #
MVN<cond><S> Rd, Rm OP Rs
AND<cond><S> Rd, Rn, #
EOR<cond><S> Rd, Rn, #
SUB<cond><S> Rd, Rn, #
RSB<cond><S> Rd, Rn, #
ADD<cond><S> Rd, Rn, #
ADC<cond><S> Rd, Rn, #
SBC<cond><S> Rd, Rn, #
RSC<cond><S> Rd, Rn, #
TST<cond> Rn, #
TEQ<cond> Rn, #
MSR<cond> CPSR_f, #
CMP<cond> Rn, #
CMN<cond> Rn, #
MSR<cond> SPSR_f, #
ORR<cond><S> Rd, Rn, #
MOV<cond><S> Rd, #
BIC<cond><S> Rd, Rn, #
MVN<cond><S> Rd, #
STR<cond> Rd, Rn, #
LDR<cond> Rd, Rn, #
STR<cond>B Rd, Rn, #
LDR<cond>B Rd, Rn, #
STR<cond>T Rd, Rn, #
LDR<cond>T Rd, Rn, #
STR<cond>BT Rd, Rn, #
LDR<cond>BT Rd, Rn, #
STR<cond> Rd, Rn, #
LDR<cond> Rd, Rn, #
STR<cond>B Rd, Rn, #
LDR<cond>B Rd, Rn, #
STR<cond>T Rd, Rn, #
LDR<cond>T Rd, Rn, #
STR<cond>BT Rd, Rn, #
LDR<cond>BT Rd, Rn, #
Undefined Instruction
STM<cond><addrmode> Rm<!>, reg list
LDM<cond><addrmode> Rm<!>, reg list
STM<cond><addrmode> Rm, reg list^
UNPREDICTABLE
LDM<cond><addrmode> Rm, reg list^
UNPREDICTABLE
STM<cond><addrmode> Rm<!>, reg list^
LDM<cond><addrmode> Rm<!>, reg list^
B<cond> <target addr>
BL<cond> <target addr>
STC<cond> p<cp_num>, CRd, #
LDC<cond> p<cp_num>, CRd, #
CDP<cond> p<cp#>,<o1>,CRd,CRn,CRm,<o2>
MCR<cond> p<cp#>,<o1>,Rd,CRn,CRm,<o2>
MRC<cond> p<cp#>,<o1>,Rd,CRn,CRm,<o2>
SWI <swi_number>

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1

0
0
0
P
P
x
P
x
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
P
P
P
P
0
0
0
0
P
P
P
P
0
0
0
0
x
P
P
P
x
P
x
P
P
0
1
P
P
0
0
0
1

0
0
0
U
U
x
U
x
U
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
x
U
U
U
x
U
x
U
U

0
0
0
I
I
x
I
x
I
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
0
0
1
1
1
1
1
1

0 S
0 S
0 S
W 0
W 1
x 0
W 1
x 0
W 1
1 S
1 S
1 S
0 S
0 S
1 S
1 S
0 S
0 S
0 S
1 S
1 S
1 S
0 S
0 S
0 S
1 S
1 S
1 S
0 1
0 1
0 0
SBZ
1 1
1 1
1 0
1 0
0 1
0 1
0 0
SBZ
1 1
1 1
1 0
0 S
0 S
1 S
1 S
0 S
0 S
1 S
1 S
0 S
1 S
0 S
1 S
0 S
1 S
0 S
1 S
0 1
1 1
1 0
0 1
1 1
1 0
0 S
1 S
0 S
1 S
W 0
W 1
W 0
W 1
1 0
1 1
1 0
1 1
W 0
W 1
W 0
W 1
1 0
1 1
1 0
1 1
x x
W 0
W 1
0 0
1 0
0 1
1 1
W 0
W 1

U N W
U N W
op1
op1
op1

0
1
0
1

Rn
Rn
Rd
Rn
Rn
x x x x
Rn
x x x x
Rn
Rn
Rn
Rd
Rn
Rn
Rn
Rn
Rn
Rn
RdHi
Rn
Rn
RdHi
Rn
Rn
RdHi
Rn
Rn
RdHi
Rn
Rn
SBO
Rn
Rn
Rn
field_mask
SBO
Rn
Rn
SBO
Rn
Rn
Rn
field_mask
Rn
Rn
SBZ
SBZ
Rn
Rn
SBZ
SBZ
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
field_mask
Rn
Rn
field_mask
Rn
SBZ
Rn
SBZ
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
x x x x
Rn
Rn
Rn
x x x x
Rn
x x x x
Rn
Rn

Rn
Rn
CRn
CRn
CRn

Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
SBZ
Rs
1 0 0 1
Rm
Rd
addr_mode 1 0 1 1 addr_mode
Rd
addr_mode 1 0 1 1 addr_mode
x x x x x x x x 1 1 0 1 x x x x
Rd
addr_mode 1 1 0 1 addr_mode
x x x x x x x x 1 1 1 1 x x x x
Rd
addr_mode 1 1 1 1 addr_mode
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
Rn
Rs
1 0 0 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
RdLo
Rs
1 0 0 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
RdLo
Rs
1 0 0 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
RdLo
Rs
1 0 0 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
RdLo
Rs
1 0 0 1
Rm
SBZ
shift #
shift 0
Rm
SBZ
Rs
0 shift 1
Rm
Rd
SBZ
Rd
SBZ
1 0 0 1
Rm
SBZ
shift #
shift 0
Rm
SBZ
Rs
0 shift 1
Rm
SBO
SBZ
0
Rm
SBO
SBO
0 0 0 1
Rm
SBZ
shift #
shift 0
Rm
SBZ
Rs
0 shift 1
Rm
Rd
SBZ
Rd
SBZ
1 0 0 1
Rm
SBZ
shift #
shift 0
Rm
SBZ
Rs
0 shift 1
Rm
SBO
SBZ
0
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
Rd
shift #
shift 0
Rm
Rd
Rs
0 shift 1
Rm
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
SBZ
rotate
#
SBZ
rotate
#
SBO
rotate
#
SBZ
rotate
#
SBZ
rotate
#
SBO
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
rotate
#
Rd
#
Rd
#
Rd
#
Rd
#
Rd
#
Rd
#
Rd
#
Rd
#
Rd
shift #
shift 0
Rm
Rd
shift #
shift 0
Rm
Rd
shift #
shift 0
Rm
Rd
shift #
shift 0
Rm
Rd
shift #
shift 0
Rm
Rd
shift #
shift 0
Rm
Rd
shift #
shift 0
Rm
Rd
shift #
shift 0
Rm
x x x x x x x x x x x 1 x x x x
register list
register list
0
register list
x x x x x x x x x x x x x x x x
0
register list
x x x x x x x x x x x x x x x x
1
register list
1
register list
24_bit_offset
24_bit_offset
CRd
cp_num
#
CRd
cp_num
#
CRd
cp_num
op2
0
CRm
Rd
cp_num
op2
1
CRm
Rd
cp_num
op2
1
CRm
swi_number

Meaning
Equal
Not Equal
Carry Set
Carry Clear
Unsigned Higher or Same
Unsigned Lower
Minus/Negative
Plus/Positive or Zero
Overflow
No Overflow
Unsigned Higher
Unsigned Lower or Same
Signed Greater than or Equal
Signed Less than
Signed Greater than
Signed Less than or Equal
Always
Never

Mnemonic
EQ
NE
CS
CC
HS
LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
NE

Opcode
ADC<cond><S> Rd, Rn, <sh_op>
ADD<cond><S> Rd, Rn, <sh_op>
AND<cond><S> Rd, Rn, <sh_op>
B<cond> <target_addr>
BIC<cond><S> Rd, Rn, <sh_op>
BL<cond> <target_addr>
BX<cond> Rm
CDP<cond> p<cp#>,o1,CRd,CRn,CRm,o2
CMN<cond> Rn, <sh_op>
CMP<cond> Rn, <sh_op>
EOR<cond><S> Rd, Rn, <sh_op>
LDC<cond> p<cp_num>, CRd, #
LDM<cond><adm> Rm, {reg list}^
LDM<cond><adm> Rm<!>, {reg list}
LDM<cond><adm> Rm<!>, {reg list}^
LDR<cond> Rd, Rn, #
LDR<cond>B Rd, Rn, #
LDR<cond>BT Rd, Rn, #
LDR<cond>H Rd, <address>
LDR<cond>SB Rd, <address>
LDR<cond>SH Rd, <address>
LDR<cond>T Rd, Rn, #
MCR<cond> p<cp#>,o1,Rd,CRn,CRm,o2
MLA<cond><S> Rd, Rm, Rs, Rn
MOV<cond><S> Rd, <sh_op>
MRC<cond> p<cp#>,o1,Rd,CRn,CRm,o2
MRS<cond> Rd, CPSR
MRS<cond> Rd, SPSR
MSR<cond> CPSR_<fields>, Rm
MSR<cond> CPSR_f, #
MSR<cond> SPSR_<fields>, Rm
MSR<cond> SPSR_f, #
MUL<cond><S> Rd, Rm, Rs
MVN<cond><S> Rd, <sh_op>
ORR<cond><S> Rd, Rn, <sh_op>
RSB<cond><S> Rd, Rn, <sh_op>
RSC<cond><S> Rd, Rn, <sh_op>
SBC<cond><S> Rd, Rn, <sh_op>
SMLAL<cond><S> RdLo, RdHi, Rm, Rs
SMULL<cond><S> RdLo, RdHi, Rm, Rs
STC<cond> p<cp_num>, CRd, #
STM<cond><adm> Rm, {reg list}^
STM<cond><adm> Rm<!>, {reg list}
STM<cond><adm> Rm<!>, {reg list}^
STR<cond> Rd, Rn, #
STR<cond>B Rd, Rn, #
STR<cond>BT Rd, Rn, #
STR<cond>H Rd, <address>
STR<cond>T Rd, Rn, #
SUB<cond><S> Rd, Rn, <sh_op>
SWI <swi_number>
SWP<cond> Rd, Rm, [Rn]
SWP<cond>B Rd, Rm, [Rn]
TEQ<cond> Rn, <sh_op>
TST<cond> Rn, <sh_op>
UMLAL<cond><S> RdLo, RdHi, Rm, Rs
UMULL<cond><S> RdLo, RdHi, Rm, Rs
Data Processing Opcode
Load/Store Opcode
Branching Opcode
Multiplication Opcode
Other Opcodes
CoProcessor Opcodes

Opcode
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Status Flags
Z=1
Z=0
C=1
C=0
C=1
C=0
N=1
N=0
V=1
V=0
C = 1, Z = 0
C = 0, Z = 1
N=V
N != V
Z = 0, N = V
Z = 1, N != V
-

Notes
"!" Keeps last Rm Value
word
byte
translate byte
half word
signed byte
signed half word
translate word
if Rd = r15 then flags
affected
64bit target
64bit target
"!" Keeps last Rm Value
word
byte
translate byte
half word
translate word
64bit target
64bit target
Flag Settings
s - if flag set
x - always
* - special

Z
s
s
s

C
s
s
s

N V
s s
s s
s

s s s

x x x x
x x x x
s s s

s s s
s s s
* * * *

s
s
s
s
s
s
s
s

s
s
s
s
s
s
s
s

s
s
s
s
s
s
s
s

s
s
s
s
s

s s s s

x
x
s
s

x
x
s
s

x
x
s s
s s

Opcode
ADC<cond><S> Rd, Rn, <sh_op>
ADD<cond><S> Rd, Rn, <sh_op>
AND<cond><S> Rd, Rn, <sh_op>
B<cond> <target_addr>
BIC<cond><S> Rd, Rn, <sh_op>
BL<cond> <target_addr>
BX<cond> Rm
CDP<cond> p<cp#>,o1,CRd,CRn,CRm,o2
CMN<cond> Rn, <sh_op>
CMP<cond> Rn, <sh_op>
EOR<cond><S> Rd, Rn, <sh_op>
LDC<cond> p<cp_num>, CRd, #
LDM<cond><adm> Rm, {reg list}^
LDM<cond><adm> Rm<!>, {reg list}
LDM<cond><adm> Rm<!>, {reg list}^
LDR<cond> Rd, Rn, #
LDR<cond>B Rd, Rn, #
LDR<cond>BT Rd, Rn, #
LDR<cond>H Rd, <address>
LDR<cond>SB Rd, <address>
LDR<cond>SH Rd, <address>
LDR<cond>T Rd, Rn, #
MCR<cond> p<cp#>,o1,Rd,CRn,CRm,o2
MLA<cond><S> Rd, Rm, Rs, Rn
MOV<cond><S> Rd, <sh_op>
MRC<cond> p<cp#>,o1,Rd,CRn,CRm,o2
MRS<cond> Rd, CPSR
MRS<cond> Rd, SPSR
MSR<cond> CPSR_<fields>, Rm
MSR<cond> CPSR_f, #
MSR<cond> SPSR_<fields>, Rm
MSR<cond> SPSR_f, #
MUL<cond><S> Rd, Rm, Rs
MVN<cond><S> Rd, <sh_op>
ORR<cond><S> Rd, Rn, <sh_op>
RSB<cond><S> Rd, Rn, <sh_op>
RSC<cond><S> Rd, Rn, <sh_op>
SBC<cond><S> Rd, Rn, <sh_op>
SMLAL<cond><S> RdLo, RdHi, Rm, Rs
SMULL<cond><S> RdLo, RdHi, Rm, Rs
STC<cond> p<cp_num>, CRd, #
STM<cond><adm> Rm, {reg list}^
STM<cond><adm> Rm<!>, {reg list}
STM<cond><adm> Rm<!>, {reg list}^
STR<cond> Rd, Rn, #
STR<cond>B Rd, Rn, #
STR<cond>BT Rd, Rn, #
STR<cond>H Rd, <address>
STR<cond>T Rd, Rn, #
SUB<cond><S> Rd, Rn, <sh_op>
SWI <swi_number>
SWP<cond> Rd, Rm, [Rn]
SWP<cond>B Rd, Rm, [Rn]
TEQ<cond> Rn, <sh_op>
TST<cond> Rn, <sh_op>
UMLAL<cond><S> RdLo, RdHi, Rm, Rs
UMULL<cond><S> RdLo, RdHi, Rm, Rs
Data Processing Opcode
Load/Store Opcode
Branching Opcode
Multiplication Opcode
Other Opcodes
CoProcessor Opcodes

Mnemonic
ADC
ADD
AND
B
BIC
BL
BX
CDP
CMN
CMP
EOR
LDC
LDM
LDR
LDRB
LDRBT
LDRH
LDRSB
LDRSH
LDRT
MCR
MLA
MOV
MRC
MRS

Description
Add with Carry
Add
Logical AND
Branch
Bit Clear
Branch and Link
Branch and Exchange
Coprocessor Data Processing
Compare Negative
Compare
Logical Exclusive OR (XOR)
Load Coprocessor
Load Multiple
Load Register
Load Register Byte
Load Register Byte Translate
Load Register Half Word
Load Register Signed Byte
Load Register Signed Half Word
Load Register Translate
Move to Coprocessor from ARM reg
Multiply Accumulate
Move
Move to ARM reg from Coprocessor
Move from Status Register

Operation
Rd = Rn + <s_op> + C
Rd = Rn + <s_op>
Rd = Rn & <s_op>
PC = PC + <offset>
Rd = Rn & !<s_op>
LR = PC+4; PC = PC + <offset>
PC = Rm; Mode=THUMB
execute coprocessor opcode
<flags> = Rn + <s_op>
<flags> = Rn - <s_op>
Rd = Rn ^ <s_op>
load coprocessor register with #
special, see doc
for each in <reglist> = [Rn+=4]
special, see doc
Rd = [Rn + #]
Rd = [Rn + #]
Rd = [Rn + #]
Rd = [address]
Rd = [address]
Rd = [address]
Rd = [Rn + #]
move from co-cpu reg to ARM reg
Rd = Rm * Rs + Rn
Rd = <s_op>
move from ARM reg to co-cpu reg
Rd = CPSR
Rd = SPSR
CPSR = Rm (fields pick bytes to copy)
CPSR = # (fields pick bytes to copy)
SPSR = Rm (fields pick bytes to copy)
SPSR = # (fields pick bytes to copy)
Rd = Rm * Rs
Rd = -<s_op>
Rd = Rn | <s_op>
Rd = <s_op> - Rn
Rd = <s_op> - Rn + C
Rd = Rn - <s_op> + C
RdHi..RdLo = Rm*Rs+(RdHi..RdLo)
RdHi..RdLo = Rm*Rs
Store coprocessor Reg with #
special, see doc
[Rm+=4] = for each in <reglist>
special, see doc
[Rn + #] = Rd
[Rn + #] = Rd
[Rn + #] = Rd
[address] = Rd
[Rn + #] = Rd
Rd = Rn - <s_op>
call software interrupt
Rd = [Rn]; [Rn] = Rm
Rd = [Rn]; [Rn] = Rm
<flags> = Rn ^ <s_op>
<flags> = Rn & <s_op>
RdHi..RdLo = Rm*Rs+(RdHi..RdLo)
RdHi..RdLo = Rm*Rs

F lag
Z
C
N
V

Mnemonic
MSR
MUL
MVN
ORR
RSB
RSC
SBC
SMLAL
SMULL
STC
STM
STR
STRB
STRBT
STRH
STRT
SUB
SWI
SWP
SWPB
TEQ
TST
UMLAL
UMULL

D escrip tio n
Z ero F lag
C arry F lag
N egative F lag
O verflow F lag

Description
Move to Status Register
Multiply
Move Negative
Logical OR
Reverse Subtract
Reverse Subtract with Carry
Subtract with Carry
Signed Long Multiply Accumulate
Signed Long Multiply
Store Coprocessor
Store Multiple
Store Register
Store Register Byte
Store Register Byte Translate
Store Register Half Word
Store Register Translate
Subtract
Software Interrupt
Swap
Swap Byte
Test Equivalence
Test
Unsigned Long Multiply Accumulate
Unsigned Long Multiply

Opcode
ADC<cond><S> Rd, Rn, #
ADC<cond><S> Rd, Rn, Rm OP #
ADC<cond><S> Rd, Rn, Rm OP Rs
ADD<cond><S> Rd, Rn, #
ADD<cond><S> Rd, Rn, Rm OP #
ADD<cond><S> Rd, Rn, Rm OP Rs
AND<cond><S> Rd, Rn, #
AND<cond><S> Rd, Rn, Rm OP #
AND<cond><S> Rd, Rn, Rm OP Rs
B<cond> <target addr>
BIC<cond><S> Rd, Rn, #
BIC<cond><S> Rd, Rn, Rm OP #
BIC<cond><S> Rd, Rn, Rm OP Rs
BL<cond> <target addr>
BX<cond> Rm
CDP<cond> p<cp#>,<o1>,CRd,CRn,CRm,<o2>
CMN<cond> Rn, #
CMN<cond> Rn, Rm OP #
CMN<cond> Rn, Rm OP Rs
CMP<cond> Rn, #
CMP<cond> Rn, Rm OP #
CMP<cond> Rn, Rm OP Rs
EOR<cond><S> Rd, Rn, #
EOR<cond><S> Rd, Rn, Rm OP #
EOR<cond><S> Rd, Rn, Rm OP Rs
LDC<cond> p<cp_num>, CRd, #
LDM<cond><addrmode> Rm, reg list^
LDM<cond><addrmode> Rm<!>, reg list
LDM<cond><addrmode> Rm<!>, reg list^
LDR<cond> Rd, Rn, #
LDR<cond> Rd, Rn, #
LDR<cond>B Rd, Rn, #
LDR<cond>B Rd, Rn, #
LDR<cond>BT Rd, Rn, #
LDR<cond>BT Rd, Rn, #
LDR<cond>H Rd, <address>
LDR<cond>SB Rd, <address>
LDR<cond>SH Rd, <address>
LDR<cond>T Rd, Rn, #
LDR<cond>T Rd, Rn, #
MCR<cond> p<cp#>,<o1>,Rd,CRn,CRm,<o2>
MLA<cond><S> Rd, Rm, Rs, Rn
MOV<cond><S> Rd, #
MOV<cond><S> Rd, Rm OP #
MOV<cond><S> Rd, Rm OP Rs
MRC<cond> p<cp#>,<o1>,Rd,CRn,CRm,<o2>
MRS<cond> Rd, CPSR
MRS<cond> Rd, SPSR
MSR<cond> CPSR_<fields>, Rm
MSR<cond> CPSR_f, #
MSR<cond> SPSR_<fields>, Rm
MSR<cond> SPSR_f, #
MUL<cond><S> Rd, Rm, Rs
MVN<cond><S> Rd, #
MVN<cond><S> Rd, Rm OP #
MVN<cond><S> Rd, Rm OP Rs
ORR<cond><S> Rd, Rn, #
ORR<cond><S> Rd, Rn, Rm OP #
ORR<cond><S> Rd, Rn, Rm OP Rs
RSB<cond><S> Rd, Rn, #
RSB<cond><S> Rd, Rn, Rm OP #
RSB<cond><S> Rd, Rn, Rm OP Rs
RSC<cond><S> Rd, Rn, #
RSC<cond><S> Rd, Rn, Rm OP #
RSC<cond><S> Rd, Rn, Rm OP Rs
SBC<cond><S> Rd, Rn, #
SBC<cond><S> Rd, Rn, Rm OP #
SBC<cond><S> Rd, Rn, Rm OP Rs
SMLAL<cond><S> RdLo, RdHi, Rm, Rs
SMULL<cond><S> RdLo, RdHi, Rm, Rs
STC<cond> p<cp_num>, CRd, #
STM<cond><addrmode> Rm, reg list^
STM<cond><addrmode> Rm<!>, reg list
STM<cond><addrmode> Rm<!>, reg list^
STR<cond> Rd, Rn, #
STR<cond> Rd, Rn, #
STR<cond>B Rd, Rn, #
STR<cond>B Rd, Rn, #
STR<cond>BT Rd, Rn, #
STR<cond>BT Rd, Rn, #
STR<cond>H Rd, <address>
STR<cond>T Rd, Rn, #
STR<cond>T Rd, Rn, #
SUB<cond><S> Rd, Rn, #
SUB<cond><S> Rd, Rn, Rm OP #
SUB<cond><S> Rd, Rn, Rm OP Rs
SWI <swi_number>
SWP<cond> Rd, Rm, [Rn]
SWP<cond>B Rd, Rm, [Rn]
TEQ<cond> Rn, #
TEQ<cond> Rn, Rm OP #
TEQ<cond> Rn, Rm OP Rs
TST<cond> Rn, #
TST<cond> Rn, Rm OP #
TST<cond> Rn, Rm OP Rs
UMLAL<cond><S> RdLo, RdHi, Rm, Rs
UMULL<cond><S> RdLo, RdHi, Rm, Rs
Undefined Instruction
Undefined Instruction
Undefined Instruction
UNPREDICTABLE
UNPREDICTABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond

0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0

1
0
0
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0

0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
P
P
P
P
P
P
P
P
0
0
P
P
P
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
P
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
x
x
x
x
x

1
1
1
1
1
1
0
0
0

0
0
0
0
0
0
0
0
0

1
1
1
0
0
0
0
0
0

S
S
S
S
S
S
S
S
S

Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn

1 1 0 S
1 1 0 S
1 1 0 S

Rn
Rn
Rn

0 0 1
op1
0 1 1
0 1 1
0 1 1
0 1 0
0 1 0
0 1 0
0 0 1
0 0 1
0 0 1
U N W
U 1 0
U 0 W
U 1 W
U 0 W
U 0 W
U 1 W
U 1 W
U 1 1
U 1 1
U I W
U I W
U I W
U 0 1
U 0 1
op1
0 0 1
1 0 1
1 0 1
1 0 1
op1
0 0 0
0 1 0
0 0 1
0 0 1
0 1 1
0 1 1
0 0 0
1 1 1
1 1 1
1 1 1
1 0 0
1 0 0
1 0 0
0 1 1
0 1 1
0 1 1
1 1 1
1 1 1
1 1 1
1 1 0
1 1 0
1 1 0
1 1 1
1 1 0
U N W
U 1 0
U 0 W
U 1 W
U 0 W
U 0 W
U 1 W
U 1 W
U 1 1
U 1 1
U I W
U 0 1
U 0 1
0 1 0
0 1 0
0 1 0

0
0
0
0
0
0
0
0
1
1
x
x
x
x
x

0
1
0
0
0
0
0
0
0
0
x
x
x
1
1

0
1
1
1
1
1
1
S
S
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
S
S
S
S
1
0
0
0
0
0
0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
0
0
0
0
0
0
0
0
0
0
0
0
0
S
S
S

SBZ
SBZ
1 1
1 1
1 1
0 1
0 1
0 1
1 S
0 S
x 0
x 0
x x
1 0
1 1

SBO
CRn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
CRn
Rd
SBZ
SBZ
SBZ
CRn
SBO
SBO
field_mask
field_mask
field_mask
field_mask
Rd
SBZ
SBZ
SBZ
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
RdHi
RdHi
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn

x
x
x
x
x

Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
RdHi
RdHi
x x
x x
x x
x x
x x

x
x
x
x
x

0
1

0
1

x
x
x
x
x

Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
24_bit_offset
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
24_bit_offset
SBO
SBO
0 0 0
CRd
cp_num
op2
SBZ
rotate
SBZ
shift #
shift
SBZ
Rs
0 shift
SBZ
rotate
SBZ
shift #
shift
SBZ
Rs
0 shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
CRd
cp_num
register list
register list
register list
Rd
#
Rd
shift #
shift
Rd
#
Rd
shift #
shift
Rd
#
Rd
shift #
shift
Rd
addr_mode 1 0 1
Rd
addr_mode 1 1 0
Rd
addr_mode 1 1 1
Rd
#
Rd
shift #
shift
Rd
cp_num
op2
Rn
Rs
1 0 0
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
Rd
cp_num
op2
Rd
SBZ
Rd
SBZ
SBO
SBZ
SBO
rotate
SBO
SBZ
SBO
rotate
SBZ
Rs
1 0 0
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
RdLo
Rs
1 0 0
RdLo
Rs
1 0 0
CRd
cp_num
register list
register list
register list
Rd
#
Rd
shift #
shift
Rd
#
Rd
shift #
shift
Rd
#
Rd
shift #
shift
Rd
addr_mode 1 0 1
Rd
#
Rd
shift #
shift
Rd
rotate
Rd
shift #
shift
Rd
Rs
0 shift
swi_number
Rd
SBZ
1 0 0
Rd
SBZ
1 0 0
SBZ
rotate
SBZ
shift #
shift
SBZ
Rs
0 shift
SBZ
rotate
SBZ
shift #
shift
SBZ
Rs
0 shift
RdLo
Rs
1 0 0
RdLo
Rs
1 0 0
x x x x x x x 1 1 0
x x x x x x x 1 1 1
x x x x x x x x x x
x x x x x x x x x x
x x x x x x x x x x

#
0
1

Rm
Rm
#

0
1

Rm
Rm
#

0
1

Rm
Rm
#

0
1

Rm
Rm

1
0

Rm
CRm
#

0
1

Rm
Rm
#

0
1

Rm
Rm
#

0
1

Rm
Rm
#

Rm

Rm

0
Rm
1 addr_mode
1 addr_mode
1 addr_mode
0
1
1

Rm
CRm
Rm
#

0
1
1

Rm
Rm
CRm

Rm
#

Rm
#

Rm
#

0
1

Rm
Rm
#

0
1

Rm
Rm
#

0
1

Rm
Rm
#

0
1

Rm
Rm

#
0
1
1
1

Rm
Rm
Rm
Rm
#

Rm

Rm

0
Rm
1 addr_mode
0

Rm
#

0
1

Rm
Rm

1
1

Rm
Rm
#

0
1

Rm
Rm
#

0
1
1
1
1
1
1
x
x

x
x
x
x
x

Rm
Rm
Rm
Rm
x x
x x
x x
x x
x x

x
x
x
x
x